TWI439192B - Interposer substrate, electronic device package, and electronic component - Google Patents
Interposer substrate, electronic device package, and electronic component Download PDFInfo
- Publication number
- TWI439192B TWI439192B TW101116874A TW101116874A TWI439192B TW I439192 B TWI439192 B TW I439192B TW 101116874 A TW101116874 A TW 101116874A TW 101116874 A TW101116874 A TW 101116874A TW I439192 B TWI439192 B TW I439192B
- Authority
- TW
- Taiwan
- Prior art keywords
- wiring
- main surface
- substrate
- electronic component
- present
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K7/00—Constructional details common to different types of electric apparatus
- H05K7/005—Constructional details common to different types of electric apparatus arrangements of circuit components without supporting structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Description
本發明係有關於一種具有貫通配線之貫通配線基板、使用該貫通配線基板之電子元件封裝體、及電子零件，且該貫通配線基板可實現電子元件、光學元件、MEMS(微機電系統)元件等之高密度封裝，或將該等元件系統化於一封裝體內之SiP(系統級封裝)。The present invention relates to a through wiring board having a through wiring, an electronic component package using the through wiring substrate, and an electronic component, wherein the through wiring substrate can realize an electronic component, an optical component, a MEMS (Micro Electro Mechanical System) component, or the like. High-density packaging, or systemizing these components into SiP (system-in-package) in a package.
近年來，隨著行動電話等電子機器之高功能化，用於該等電子機器之電子元件等也因而須具有再上一層之高速化、高功能化。為實現這些需求，其技術開發不僅止於元件自身之高速化、高功能化，還必須著眼元件之封裝體由於配線圖案之微細化等造成之配線高密度化。實現高密度封裝之技術，已有人提出使用微細貫通配線以積層封裝晶片之三維封裝，或者使用形成有貫通配線之貫通配線基板之SiP。為實現三維封裝和SiP而用之貫通配線或貫通配線基板之形成技術目前正興盛地開發研究中。In recent years, with the increase in the functionality of electronic devices such as mobile phones, electronic components and the like used in such electronic devices have to be upgraded and functionalized. In order to realize these demands, the development of the technology is not limited to the high speed and high functionality of the components themselves, and it is necessary to pay attention to the high density of the wiring due to the miniaturization of the wiring pattern. In order to realize a high-density package, it has been proposed to use a fine through wiring to laminate a three-dimensional package of a wafer, or to use a SiP formed with a through wiring of a through wiring. A technique for forming a through wiring or a through wiring substrate for realizing three-dimensional packaging and SiP is currently under development.
具有形成於與基板主面垂直之方向之習知貫通配線之貫通配線基板，當配置成積層多個基板時，因接合外力造成之損傷常導致貫通配線電極脫落或界面剝離。When a plurality of substrates are disposed so as to have a plurality of substrates which are formed in a direction perpendicular to the main surface of the substrate, the damage caused by the bonding external force often causes the through wiring electrodes to fall off or the interface to peel off.
為解決此問題，日本專利公報第3896038號揭示一具有相對與基板主面垂直之方向傾斜形成之貫通配線之貫通配 線基板。In order to solve this problem, Japanese Patent Publication No. 3896038 discloses a through-distribution of through wiring formed obliquely with respect to a direction perpendicular to a main surface of a substrate. Line substrate.
前述貫通配線基板使用複數貫通配線進行更高密度三維封裝時，有技術上的難題。When the above-mentioned through-wiring substrate is used for higher-density three-dimensional packaging using a plurality of through wirings, there is a technical problem.
利用示意顯示習知貫通配線基板一構成例之第13~15圖來進行說明。在此，第13圖係顯示於習知貫通配線基板表面排列配置複數端子群之狀態之平面圖。第14圖係沿第13圖之M4-M4線截取之截面圖，第15圖係沿第13圖之N4-N4線截取之截面圖。Description will be made by referring to Figs. 13 to 15 of a configuration example of a conventional through wiring substrate. Here, Fig. 13 is a plan view showing a state in which a plurality of terminal groups are arranged on the surface of a conventional through wiring substrate. Fig. 14 is a cross-sectional view taken along line M4-M4 of Fig. 13, and Fig. 15 is a cross-sectional view taken along line N4-N4 of Fig. 13.
如第13及14圖所示，其構造係等間隔排列配置於基板110之第一主面110a之複數端子130A、130B、130C…，與排列配置於基板110之第二主面110b之複數端子130A’、130B’、130C’…，藉貫通配線120A’、120B’、120C’…電連接成端子標號對應之狀態。具體而言，在基板110之第二主面110b，複數端子130A’、130B’、130C’…以與端子130A、130B、130C…相同之佈置來配置。第二主面110b之複數端子130A’、130B’、130C’…之位置於X方向上，與端子130A、130B、130C…之位置不同。在此，如第15圖所示貫通配線之線徑R固定，且相鄰貫通配線間之距離(貫通配線之邊緣間之距離)L也固定。As shown in FIGS. 13 and 14, the structure is a plurality of terminals 130A, 130B, 130C, which are arranged at equal intervals on the first main surface 110a of the substrate 110, and a plurality of terminals arranged in the second main surface 110b of the substrate 110. 130A', 130B', 130C'... are electrically connected to each other in a state in which the terminal numbers correspond to each other through the wirings 120A', 120B', 120C'. Specifically, at the second main surface 110b of the substrate 110, the plurality of terminals 130A', 130B', 130C' are arranged in the same arrangement as the terminals 130A, 130B, 130C, . The positions of the plurality of terminals 130A', 130B', 130C', ... of the second main surface 110b are different from the positions of the terminals 130A, 130B, 130C, ... in the X direction. Here, as shown in Fig. 15, the wire diameter R of the through wiring is fixed, and the distance between adjacent through wires (the distance between the edges of the through wires) L is also fixed.
此時，自第15圖清楚可見，在基板110內部，貫通配線20A、120B、120於基板厚度方向上，直線狀等間隔排列，且隨著貫通配線之數量增加，基板110之厚度也增加。然而，為求維持相鄰貫通配線間之電絕緣性，避免相互干擾之錯亂，不能無限制地縮小貫通配線分隔之距離L。因此， 隨著封裝之元件之端子數增加，貫通配線之數量也增加時，基板厚度就會隨之增加。基板厚度如此增加，就高密度封裝之小型化、薄型化而言，並不適宜。At this time, as is clear from Fig. 15, in the substrate 110, the through wirings 20A, 120B, and 120 are linearly arranged at equal intervals in the thickness direction of the substrate, and as the number of through wirings increases, the thickness of the substrate 110 also increases. However, in order to maintain electrical insulation between adjacent through wirings and to avoid mutual interference, it is not possible to reduce the distance L of the through wiring separation without limitation. therefore, As the number of terminals of the packaged component increases and the number of through wires increases, the thickness of the substrate increases. The thickness of the substrate is increased in this way, and it is not suitable for miniaturization and thinning of the high-density package.
本發明係用以解決前述習知課題而作成者，第一目的在於提供一種貫通配線基板，係即使貫通配線之數量增加，仍可抑制基板厚度之增加，且配線構造之設計自由度高，並可達成小型且高密度之三維封裝者。The present invention has been made to solve the above problems, and a first object of the present invention is to provide a through-wiring substrate in which the increase in the thickness of the substrate can be suppressed even if the number of through wirings is increased, and the degree of freedom in designing the wiring structure is high. A small, high-density three-dimensional package can be achieved.
又，本發明之第二目的在於提供一種電子元件封裝體，係配線構造之設計自由度高，並可達成小型且高密度之三維封裝者。Further, a second object of the present invention is to provide an electronic component package which has a high degree of freedom in designing a wiring structure and can realize a small-sized and high-density three-dimensional package.
又，本發明之第三目的在於提供一種電子零件，係配線構造之設計自由度高，並可達成小型且高密度之三維封裝者。Further, a third object of the present invention is to provide an electronic component which has a high degree of freedom in designing a wiring structure and can realize a small-sized and high-density three-dimensional package.
為達成前述目的，本發明第1態樣之貫通配線基板，包含有：單一基板，係具有第一主面及第二主面者；及複數貫通配線，係具有相互平行延伸設置之第一部位，並連結前述第一主面及前述第二主面者，且彼此相鄰之前述貫通配線，設置成其相對前述第一主面及前述第二主面之至少其中之一為垂直延伸而貫穿前述第一部位之中心之假想軸，相互平行且分隔。In order to achieve the above object, a through wiring board according to a first aspect of the present invention includes: a single substrate having a first main surface and a second main surface; and a plurality of through wirings having first portions extending in parallel with each other And connecting the first main surface and the second main surface, and the through wirings adjacent to each other are disposed so as to extend perpendicularly to at least one of the first main surface and the second main surface The imaginary axes of the centers of the first portions are parallel and spaced apart from each other.
依本發明第1態樣之貫通配線基板，相鄰之前述貫通配線錯開配置成當假定相對前述基板之主面為垂直並貫穿前 述第一部位之中心之軸(假想軸)時，兩者之軸相互平行且分隔。因此，相較於貫通配線排列配置成與本發明第1態樣相同數量之貫通配線以相同間隔分隔且未於相對主面為垂直之方向上錯開之構造，本發明第1態樣之貫通配線基板可抑制貫通配線之基板之厚度增加。於是，依本發明，可提供一種貫通配線基板，係即使貫通配線之數量增加，仍可抑制基板厚度之增加，具有配線構造之設計自由度高，並可達成小型且高密度之三維封裝之貫通配線者。According to the first aspect of the present invention, in the through wiring board, the adjacent through wirings are arranged to be shifted so as to be perpendicular to the main surface of the substrate. When the axis (imaginary axis) of the center of the first portion is described, the axes of the two are parallel and spaced apart from each other. Therefore, the through wiring of the first aspect of the present invention is arranged in such a manner that the same number of through wirings are arranged at the same interval and are not shifted in the direction perpendicular to the main surface as compared with the through wiring arrangement. The substrate can suppress an increase in the thickness of the substrate through which the wiring is passed. Therefore, according to the present invention, it is possible to provide a through-wiring substrate which can suppress an increase in the thickness of the substrate even if the number of through-wiring increases, and has a high degree of freedom in designing the wiring structure, and can realize a small-sized and high-density three-dimensional package. Wiring person.
本發明第1態樣之貫通配線基板，宜前述第一部位配置成相對前述第一主面及前述第二主面之至少其中之一為略平行。In the first aspect of the present invention, the first portion is disposed so as to be slightly parallel to at least one of the first main surface and the second main surface.
依此，由於第一部位之位置相對基板之深度方向恆為固定，所以可有效抑制基板在厚度方向之增加。Accordingly, since the position of the first portion is constant with respect to the depth direction of the substrate, the increase in the thickness direction of the substrate can be effectively suppressed.
本發明第1態樣之貫通配線基板，宜前述貫通配線具有形成前述第一部位之兩端之第二部位及第三部位，且前述第二部位之長向相對前述第一主面為略垂直，且前述第三部位之長向相對前述第二主面為略垂直。In the first aspect of the present invention, the through wiring may have a second portion and a third portion forming both ends of the first portion, and the long direction of the second portion is slightly perpendicular to the first main surface. And the length direction of the third portion is slightly perpendicular to the second main surface.
依此，即使當基板原本之厚度不均一時，或者前述基板之研磨步驟之加工精度造成厚度不均一時，因為設在前述貫通配線基板之主面之開口部之位置不會變動，所以可精度佳地確實形成前述貫通配線。According to this, even when the original thickness of the substrate is not uniform, or the processing accuracy of the polishing step of the substrate causes the thickness to be uneven, the position of the opening provided on the main surface of the through wiring substrate does not fluctuate, so that the accuracy is possible. It is preferable to form the aforementioned through wiring.
本發明第1態樣之貫通配線基板，宜前述複數貫通配線之長度相互略同。In the through wiring board according to the first aspect of the present invention, it is preferable that the lengths of the plurality of through wirings are substantially the same.
依此，可使複數貫通配線之電阻略均一。即，由於可 抑制貫通配線間之配線電阻之不均一，所以本發明可促進封裝於貫通配線基板之元件之電氣特性穩定。Accordingly, the resistance of the plurality of through wirings can be made slightly uniform. That is, because Since the unevenness of the wiring resistance between the through wirings is suppressed, the present invention can promote the stability of the electrical characteristics of the components packaged in the through wiring substrate.
本發明第1態樣之貫通配線基板，宜於前述第一主面設有墊件，用以電連接構成前述貫通配線之前述第二部位，且於前述第二主面設有墊件，用以電連接構成前述貫通配線之前述第三部位。In the first aspect of the present invention, it is preferable that the first main surface is provided with a spacer for electrically connecting the second portion constituting the through wiring, and the second main surface is provided with a spacer. The third portion of the through wiring is electrically connected.
依此，例如當於貫通配線基板之兩面封裝元件時，前述元件之電極與前述墊件電連接而無須藉由表面配線，所以基板與元件(電子零件)之間之連接容易，且可以幾乎最短距離連結兩元件之電極間。又，依本發明，例如即使使用電極以任何佈置狀態高密度配置之小型元件，仍可自由設計變更以使前述墊件對應元件之電極位置，所以可將小型元件封裝於貫通配線基板。According to this, for example, when the components are packaged on both sides of the wiring substrate, the electrodes of the components are electrically connected to the pad without the need for surface wiring, so that the connection between the substrate and the component (electronic component) is easy and can be almost the shortest. The distance between the electrodes connecting the two components. Further, according to the present invention, for example, even if a small element having a high density of electrodes arranged in any arrangement state is used, the electrode position of the pad corresponding member can be freely designed and changed, so that the small component can be packaged in the through wiring substrate.
本發明第1態樣之貫通配線基板，宜前述基板具有冷卻該基板之冷卻部。In the first aspect of the present invention, it is preferable that the substrate has a cooling portion for cooling the substrate.
依此，例如即使高密度配置電極且發熱量大之元件封裝於貫通配線基板時，仍可有效降低溫度上升情形。According to this, for example, even when an element having a high-density electrode and a large amount of heat is packaged on the through-wiring substrate, the temperature rise can be effectively reduced.
本發明第2態樣之電子元件封裝體，包含有：前述第1態樣之貫通配線基板；及電子元件，係封裝在前述貫通配線基板之前述第一主面及前述第二主面之至少其中之一者。An electronic component package according to a second aspect of the present invention includes: the through wiring substrate of the first aspect; and the electronic component packaged on at least the first main surface and the second main surface of the through wiring substrate One of them.
依此，可促進具有前述電子元件封裝體之電子裝置之薄型化、小型化、高速化等等。According to this, it is possible to promote thinning, miniaturization, high speed, and the like of the electronic device having the electronic component package.
本發明第2態樣之電子元件封裝體，宜前述貫通配線基板之前述貫通配線具有形成前述第一部位之兩端之第二部 位及第三部位，且前述第二部位之端部及前述第三部位之端部之至少其中之一，配置在與前述電子元件之端子相對向之位置，且前述電子元件之前述端子，與前述第二部位之前述端部及前述第三部位之前述端部之至少其中之一電連接。In the electronic component package according to the second aspect of the present invention, it is preferable that the through wiring of the through wiring substrate has a second portion forming both ends of the first portion. And a third portion, wherein at least one of an end portion of the second portion and an end portion of the third portion is disposed at a position facing a terminal of the electronic component, and the terminal of the electronic component is At least one of the end portion of the second portion and the end portion of the third portion is electrically connected.
依此，封裝於貫通配線基板之元件之電極與前述墊件電連接而無須藉由表面配線，所以即使使用電極以任何佈置狀態高密度配置之小型元件，仍可自由連接元件之電極與前述墊件。又，當元件封裝於基板之兩面時，可將前述第二部位及第三部位之端部，配置成相對其個別之元件之端子且與該等端子電連接，所以可以幾乎最短距離連結兩元件之電極間，於是能提供小型且高性能之電子元件封裝體。According to this, the electrode of the element packaged in the through-wiring substrate is electrically connected to the pad member without the surface wiring, so that the electrode of the element and the pad can be freely connected even if a small element having a high density arrangement of the electrode in any arrangement state is used. Pieces. Moreover, when the components are packaged on both sides of the substrate, the ends of the second portion and the third portion can be arranged to be electrically connected to the terminals of the respective components and to the terminals, so that the two components can be connected at almost the shortest distance. Between the electrodes, a small and high-performance electronic component package can be provided.
本發明第3態樣之電子零件，係至少包含有前述第2態樣之電子元件封裝體者。An electronic component according to a third aspect of the present invention is the electronic component package including at least the second aspect.
依此，可促進包含有前述電子元件封裝體之電子裝置(電子零件)之薄型化、小型化、高速化等等。According to this, it is possible to promote thinning, miniaturization, high speed, and the like of the electronic device (electronic component) including the electronic component package.
依本發明，即使貫通配線之數量增加，仍可抑制基板厚度之增加，且配線構造之設計自由度高，並可達成小型且高密度之三維封裝。According to the present invention, even if the number of through wirings is increased, the increase in the thickness of the substrate can be suppressed, and the degree of freedom in designing the wiring structure is high, and a small-sized and high-density three-dimensional package can be achieved.
又，依本發明，可提供一種配線構造設計之自由度高，小型且可高密度三維封裝之電子元件封裝體。Moreover, according to the present invention, it is possible to provide an electronic component package having a high degree of freedom in wiring structure design and a small size and high-density three-dimensional package.
又，依本發明，可提供一種配線構造設計之自由度高，小型且可高密度三維封裝之電子零件。Moreover, according to the present invention, it is possible to provide an electronic component having a high degree of freedom in wiring structure design and a small size and high-density three-dimensional package.
第1圖係示意顯示本發明貫通配線基板之第1實施態樣 之平面圖。Fig. 1 is a view schematically showing a first embodiment of a through wiring substrate of the present invention Floor plan.
第2圖係沿第1圖之M1-M1線截取之截面圖。Fig. 2 is a cross-sectional view taken along the line M1-M1 of Fig. 1.
第3圖係沿第1圖之N1-N1線截取之截面圖。Fig. 3 is a cross-sectional view taken along the line N1-N1 of Fig. 1.
第4圖係用以說明本發明貫通配線基板之第1實施態樣中貫通配線配置之放大截面圖。Fig. 4 is an enlarged cross-sectional view showing the arrangement of the through wiring in the first embodiment of the through wiring board of the present invention.
第5圖係示意顯示本發明貫通配線基板之第2實施態樣之截面圖。Fig. 5 is a cross-sectional view showing a second embodiment of the through wiring substrate of the present invention.
第6圖係示意顯示本發明貫通配線基板之第4實施態樣之平面圖。Fig. 6 is a plan view schematically showing a fourth embodiment of the through wiring substrate of the present invention.
第7圖係沿第6圖之M2-M2線截取之截面圖。Fig. 7 is a cross-sectional view taken along line M2-M2 of Fig. 6.
第8圖係沿第6圖之N2-N2線截取之截面圖。Figure 8 is a cross-sectional view taken along line N2-N2 of Figure 6.
第9A圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9A is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第9B圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9B is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第9C圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9C is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring board.
第9D圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9D is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第10圖係示意顯示本發明電子元件封裝體之一例之平面圖。Fig. 10 is a plan view schematically showing an example of the electronic component package of the present invention.
第11圖係沿第10圖之M3-M3線截取之截面圖。Figure 11 is a cross-sectional view taken along line M3-M3 of Figure 10.
第12圖係沿第10圖之N3-N3線截取之截面圖。Fig. 12 is a cross-sectional view taken along line N3-N3 of Fig. 10.
第13圖係示意顯示習知貫通配線基板之一例之平面圖。Fig. 13 is a plan view showing an example of a conventional through wiring substrate.
第14圖係沿第13圖之M4-M4線截取之截面圖。Figure 14 is a cross-sectional view taken along line M4-M4 of Figure 13.
第15圖係沿第13圖之N4-N4線截取之截面圖。Figure 15 is a cross-sectional view taken along line N4-N4 of Figure 13.
以下，配合參照圖式，說明本發明貫通配線基板之較佳實施態樣。Hereinafter, a preferred embodiment of the through wiring substrate of the present invention will be described with reference to the drawings.
第1~4圖係示意顯示本發明貫通配線基板之第1實施態樣一構成例之圖。在此，第1圖係顯示本發明貫通配線基板之第1實施態樣中，於表面配置複數端子群之狀態之平面圖。又，第2圖係沿第1圖之M1-M1線截取之截面圖，第3圖及第4圖係係沿第1圖之N1-N1線截取之截面圖。1 to 4 are views showing a configuration example of a first embodiment of the through wiring board of the present invention. Here, Fig. 1 is a plan view showing a state in which a plurality of terminal groups are arranged on the surface in the first embodiment of the through wiring substrate of the present invention. Further, Fig. 2 is a cross-sectional view taken along line M1-M1 of Fig. 1, and Fig. 3 and Fig. 4 are cross-sectional views taken along line N1-N1 of Fig. 1.
此貫通配線基板1A(1)包含有複數貫通配線20A、20B、20C...(20)，用以連結構成單一基板10之主面(第一主面10a及第二主面10b)。The through wiring substrate 1A (1) includes a plurality of through wirings 20A, 20B, 20C (20) for connecting the main surfaces (the first main surface 10a and the second main surface 10b) constituting the single substrate 10.
基板10之材料例舉如玻璃、塑膠、陶瓷等絕緣體或矽(Si)等半導體。使用半導體基板作為基板10之材料時，宜於貫通孔21之內壁或主面等形成絕緣層，以確保貫通配線20與基板10之間之電絕緣性。使用絕緣性基板作為基板10之材料時，由於無須再於貫通孔21之內壁形成絕緣層，所以更為適合。The material of the substrate 10 is exemplified by an insulator such as glass, plastic or ceramic, or a semiconductor such as germanium (Si). When a semiconductor substrate is used as the material of the substrate 10, it is preferable to form an insulating layer on the inner wall or the main surface of the through hole 21 to ensure electrical insulation between the through wiring 20 and the substrate 10. When an insulating substrate is used as the material of the substrate 10, it is more suitable because the insulating layer is not required to be formed on the inner wall of the through hole 21.
貫通孔21具有開口於基板10之一主面(第一主面)10a之第一開口部21a，及開口於基板10之另一主面(第二主面)10b之第二開口部21b，且該貫通孔21之內部配置有導體22。由該導體22構成貫通配線20。貫通配線20具有第一部位24(部 位α)、第二部位25(部位β)、及第三部位26(部位γ)。以第一部位24之長向相對前述基板10之主面為略平行狀態，第一部位24延伸於前述基板10之內部。第二部位25及第三部位26位於第一部位24之兩端。換言之，第二部位25構成貫通配線20之第一端部(一端部)，而第三部位26構成貫通配線20之第二端部(另一端部)。即，第二部位25之端部(第一端部)位於第一主面10a(露出於面臨第一主面10a之空間)，第三部位26(第二端部)位於第二主面10b(露出於面臨第二主面10b之空間)。The through hole 21 has a first opening portion 21a that opens to one main surface (first main surface) 10a of the substrate 10, and a second opening portion 21b that opens to the other main surface (second main surface) 10b of the substrate 10, A conductor 22 is disposed inside the through hole 21. The through wiring 20 is constituted by the conductor 22. The through wiring 20 has a first portion 24 (part Position α), second part 25 (part β), and third part 26 (part γ). The length of the first portion 24 is slightly parallel to the main surface of the substrate 10, and the first portion 24 extends inside the substrate 10. The second portion 25 and the third portion 26 are located at both ends of the first portion 24. In other words, the second portion 25 constitutes the first end portion (one end portion) of the through wiring 20, and the third portion 26 constitutes the second end portion (the other end portion) of the through wiring 20. That is, the end portion (first end portion) of the second portion 25 is located on the first main surface 10a (exposed to the space facing the first main surface 10a), and the third portion 26 (second end portion) is located on the second main surface 10b. (exposed to the space facing the second main face 10b).
第一部位24與第二部位25藉由彎曲部28連接。第一部位24與第三部位26藉由彎曲部29連接。彎曲部28、29之形狀並無特別限定。彎曲部在其縱截面上亦可係具有角之形狀，或者亦可係未具有角之略圓弧狀。就高速傳輸之觀點而言，使用未具有角之略圓弧狀彎曲部更為適宜。The first portion 24 and the second portion 25 are connected by a curved portion 28. The first portion 24 and the third portion 26 are connected by a curved portion 29. The shape of the curved portions 28 and 29 is not particularly limited. The curved portion may have a shape of a corner in its longitudinal section, or may have a slightly arc shape without a corner. From the viewpoint of high-speed transmission, it is more preferable to use a slightly arc-shaped bent portion having no corner.
又，第二部位25及第三部位26之長向，宜各自相對前述主面10a、10b為略垂直。第二部位25之長向相對第一主面10a為略垂直，第三部位26相對第二主面10b為略垂直。依此，即使當基板10之原本厚度不均一時，或者前述基板10之研磨步驟之加工精度造成厚度不均一時，設在基板10之主面之開口部21a、21b之位置仍不會變動。因此，可精度佳地確實形成貫通配線20。Further, it is preferable that the longitudinal directions of the second portion 25 and the third portion 26 are slightly perpendicular to the main surfaces 10a and 10b. The length of the second portion 25 is slightly perpendicular to the first major surface 10a, and the third portion 26 is slightly perpendicular to the second major surface 10b. Accordingly, even when the original thickness of the substrate 10 is not uniform, or the processing accuracy of the polishing step of the substrate 10 causes the thickness to be uneven, the positions of the openings 21a and 21b provided on the main surface of the substrate 10 do not change. Therefore, the through wiring 20 can be surely formed with high precision.
用於貫通配線20之導體22，例舉如銅(Cu)或鎢(W)等金屬、金錫(Au-Sn)等合金、或者聚矽等非金屬之導體。作為將導體充填至貫通孔21之方法或形成導體之膜之方法，可適當使用鍍敷法、熔融金屬充填法、CVD(化學氣相沈積 法)、超臨界成膜法等等。The conductor 22 for the through wiring 20 is exemplified by a metal such as copper (Cu) or tungsten (W), an alloy such as gold-tin (Au-Sn), or a non-metallic conductor such as polyfluorene. As a method of filling the conductor to the through hole 21 or a method of forming a film of the conductor, plating, molten metal filling, CVD (chemical vapor deposition) can be suitably used. Method), supercritical film forming method, and the like.
貫通配線基板1A(1)於表面排列配置有複數端子群。配置於基板10之第一主面10a(第一主面10a側)之複數端子，與配置於基板10另一第二主面10b(第二主面10b側)之複數端子藉由複數貫通配線20而電連接。The plurality of terminal groups are arranged on the surface of the through wiring substrate 1A (1). The plurality of terminals disposed on the first main surface 10a (on the first main surface 10a side) of the substrate 10 and the plurality of terminals disposed on the other second main surface 10b (the second main surface 10b side) of the substrate 10 are connected by a plurality of through wiring 20 and electrically connected.
例如第1圖及第2圖所示，於基板10之第一主面10a，配置有以等間隔排列之第一端子群30A、30B、30C...。於基板10之第二主面10b，配置有與第一端子群相同之佈置，且在第二主面10b之位置於X方向上相異排列之第二端子群30A’、30B’、30C’...。此外，第一端子群30A、30B、30C...與第二端子群30A’、30B’、30C’...，藉由貫通配線20A、20B、20C...電連接成分別之端子標號對應。For example, as shown in FIGS. 1 and 2, first terminal groups 30A, 30B, 30C, ... arranged at equal intervals are disposed on the first main surface 10a of the substrate 10. The second main surface 10b of the substrate 10 is disposed with the same arrangement as the first terminal group, and the second terminal groups 30A', 30B', 30C' are arranged differently in the X direction at the position of the second main surface 10b. .... Further, the first terminal groups 30A, 30B, 30C, ... and the second terminal groups 30A', 30B', 30C', ... are electrically connected to the respective terminal numbers by the through wirings 20A, 20B, 20C, ... correspond.
即，第一端子30A與第二端子30A’藉由貫通配線20A電連接。又，第一端子30B與第二端子30B’藉由貫通配線20B電連接。又，第一端子30C與第二端子30C’藉由貫通配線20C電連接。That is, the first terminal 30A and the second terminal 30A' are electrically connected by the through wiring 20A. Further, the first terminal 30B and the second terminal 30B' are electrically connected by the through wiring 20B. Further, the first terminal 30C and the second terminal 30C' are electrically connected by the through wiring 20C.
然後，如第3圖所示，於本發明第1實施態樣之貫通配線基板1A(1)，相鄰之貫通配線20A、20B、20C...(20)設置成其相對前述基板10之主面(第一主面10a及第二主面10b)為垂直延伸而貫穿前述第一部位24之中心之假想軸S1、S2，相互平行且分隔。在此，複數軸S1、S2係於貫通配線基板1A(1)假定之軸。又，第3圖顯示第一部位24之橫截面，假想軸S1、S2貫穿第一部位24之橫截面之中心。Then, as shown in FIG. 3, in the through wiring substrate 1A (1) according to the first embodiment of the present invention, the adjacent through wirings 20A, 20B, 20C (20) are disposed opposite to the substrate 10 The main surfaces (the first main surface 10a and the second main surface 10b) are imaginary axes S1 and S2 extending vertically and penetrating the center of the first portion 24, and are parallel and spaced apart from each other. Here, the plurality of axes S1 and S2 are connected to the axis assumed by the wiring board 1A (1). Further, Fig. 3 shows a cross section of the first portion 24, and the imaginary axes S1, S2 penetrate the center of the cross section of the first portion 24.
以下，敘述貫通配線20A與貫通配線20B之間關係，用 以說明相鄰貫通配線之位置關係。例如第3圖所示，貫通配線20A之軸S1(假想軸)與貫通配線20B之軸S2(假想軸)，相互平行且分隔。即，在本發明第1實施態樣之貫通配線基板1，配置有貫通配線20A、20B，俾至少相鄰配線之貫通配線20A、20B之位置相互錯開。Hereinafter, the relationship between the through wiring 20A and the through wiring 20B will be described. The positional relationship of the adjacent through wirings will be described. For example, as shown in FIG. 3, the axis S1 (imaginary axis) of the through wiring 20A and the axis S2 (imaginary axis) of the through wiring 20B are parallel to each other and separated. In other words, in the through wiring board 1 according to the first embodiment of the present invention, the through wirings 20A and 20B are disposed, and the positions of the through wirings 20A and 20B of at least adjacent wirings are shifted from each other.
如第4圖之放大截面圖所示，相鄰貫通配線20A、20B其中之一之貫通配線(20B)配置成自相對主面為垂直之方向偏移角度θ。在此，貫通配線20A、20B之線徑R為固定。又，相鄰貫通配線20A、20B分隔之距離(相鄰貫通配線相互接近之邊緣分隔之距離)以L顯示，該距離為固定。此時，維持相鄰貫通配線20A、20B間之距離L之狀態，貫通配線20B設在自相對主面為垂直之方向偏移角度θ之位置。基板10之厚度方向(相對主面為垂直之方向)之長度，外觀上減少(1-cosθ)L。依此，相較於與本實施態樣相同數量之貫通配線20分隔相同距離L，且未自相對主面為垂直之方向錯開排列貫通配線之構造(於垂直方向上配列相鄰貫通配線20A、20B)，可有效抑制基板10厚度之增加。As shown in the enlarged cross-sectional view of Fig. 4, the through wiring (20B) of one of the adjacent through wirings 20A and 20B is disposed to be offset by an angle θ from a direction perpendicular to the main surface. Here, the wire diameter R of the through wires 20A and 20B is fixed. Further, the distance between the adjacent through wirings 20A and 20B (the distance at which the adjacent through wirings are close to each other) is indicated by L, and the distance is fixed. At this time, the state in which the distance L between the adjacent through wirings 20A and 20B is maintained is maintained, and the through wiring 20B is provided at a position shifted by an angle θ from the direction perpendicular to the main surface. The length of the substrate 10 in the thickness direction (the direction perpendicular to the main surface) is reduced in appearance (1-cos θ) L. With this configuration, the same number of through wires 20 as the present embodiment are separated by the same distance L, and the through wiring is not arranged in a direction perpendicular to the main surface (the adjacent through wiring 20A is arranged in the vertical direction, 20B), the increase in the thickness of the substrate 10 can be effectively suppressed.
因此，本發明第1實施態樣中，即使貫通配線之數量增加，仍可抑制基板厚度之增加，並可達成高密度三維封裝或電子元件封裝體之薄型化。Therefore, in the first embodiment of the present invention, even if the number of through wirings is increased, the increase in the thickness of the substrate can be suppressed, and the high-density three-dimensional package or the thinning of the electronic component package can be achieved.
接著，說明本發明第2實施態樣。Next, a second embodiment of the present invention will be described.
如第5圖所示，在本發明第2實施態樣之貫通配線基板1A(1)，亦可分別於前述基板10之主面10a、10b設置墊件2、 3，用以與構成前述貫通配線20之前述第一部位25及前述第三部位26電連接。當於貫通配線基板1A(1)之兩面封裝元件時，前述元件之電極與前述墊件電連接而無須藉由表面配線，所以即使使用電極以任何佈置狀態高密度配置之小型元件，仍可將小型元件與貫通配線基板連接。As shown in Fig. 5, in the through wiring substrate 1A (1) according to the second embodiment of the present invention, the spacer 2 may be provided on the main surfaces 10a and 10b of the substrate 10, respectively. 3, for electrically connecting to the first portion 25 and the third portion 26 constituting the through wiring 20. When the components are packaged on both sides of the wiring substrate 1A (1), the electrodes of the foregoing components are electrically connected to the pad without the need for surface wiring, so even if small components of electrodes arranged at high density in any arrangement state are used, The small component is connected to the through wiring substrate.
又，在貫通配線基板1A(1)，宜前述貫通配線20A、20B、20C...之長度相互略同。依此，可使複數貫通配線20A、20B、20C...之電阻略均一，提高封裝於貫通配線基板1A(1)之元件之電氣特性。又，亦可抑制當訊號高速傳輸時，在複數貫通配線發生線路延遲不均一之情形。Further, in the through wiring substrate 1A (1), the lengths of the through wirings 20A, 20B, 20C, ... are preferably the same. Thereby, the resistance of the plurality of through wirings 20A, 20B, 20C, ... can be made slightly uniform, and the electrical characteristics of the components packaged in the through wiring substrate 1A (1) can be improved. Moreover, it is also possible to suppress a situation in which the line delay is uneven in the plurality of through wirings when the signal is transmitted at a high speed.
接著，說明本發明第3實施態樣。Next, a third embodiment of the present invention will be described.
又，在貫通配線基板1A(1)，亦可前述基板10具有冷卻該基板10之冷卻部。Further, in the wiring board 1A (1), the substrate 10 may have a cooling portion that cools the substrate 10.
此種冷卻基板10之冷卻部，例舉如第5圖所示，供冷卻用流體流通之流路40。依此，藉著使冷媒流通前述流路40，則即使是於貫通配線基板封裝發熱量大之元件時，仍可有效降低溫度上升情形。In the cooling portion of the cooling substrate 10, as shown in Fig. 5, a flow path 40 through which a cooling fluid flows is exemplified. According to this, by allowing the refrigerant to flow through the flow path 40, the temperature rise can be effectively reduced even when the element having a large amount of heat generation is sealed through the wiring board.
流路40於流路40兩端具有冷卻用流體出入之出入口40a、40b。亦可設置複數流路40。又，流路40亦可設成蛇形狀，俾一條流路40便可冷卻基板10整體。又，流路40之出入口40a、40b亦可開口於基板10之主面。The flow path 40 has inlets and outlets 40a and 40b through which the cooling fluid enters and exits at both ends of the flow path 40. A plurality of flow paths 40 may also be provided. Further, the flow path 40 may be formed in a serpentine shape, and the entire flow path 40 may cool the entire substrate 10. Further, the inlets and outlets 40a and 40b of the flow path 40 may be opened to the main surface of the substrate 10.
又，流路40之圖案(路徑)或截面形狀並不限於前述構造，而是可適當進行設計。不過，較佳地，流路40於三維 空間上在與面平行之方向或厚度方向保持預定間隔，以免連通具有貫通配線20之貫通孔21。Further, the pattern (path) or cross-sectional shape of the flow path 40 is not limited to the above configuration, but may be appropriately designed. Preferably, however, the flow path 40 is in three dimensions The space is kept at a predetermined interval in a direction parallel to the surface or in the thickness direction so as not to connect the through hole 21 having the through wiring 20.
可藉由與用以形成配置貫通配線20之貫通孔21之方法，形成流路40。此時，較佳地，當形成供貫通配線20形成之貫空孔21時，同時形成進行形成作為流路40用之貫通孔。若同時形成貫通配線20之貫通孔21與作為流路40用之貫通孔，便可簡略製程，使成本降低。又，還可輕易控制貫通孔21與流路40之間位置關係，避免貫通孔21與流路40出錯而連通。The flow path 40 can be formed by a method for forming the through hole 21 through which the through wiring 20 is disposed. At this time, it is preferable to form a through hole for forming the flow path 40 at the same time when the through hole 21 for forming the through wiring 20 is formed. When the through hole 21 penetrating the wiring 20 and the through hole for the flow path 40 are simultaneously formed, the process can be simplified and the cost can be reduced. Moreover, the positional relationship between the through hole 21 and the flow path 40 can be easily controlled, and the through hole 21 and the flow path 40 can be prevented from communicating with each other.
接下來，說明本發明第4實施態樣。Next, a fourth embodiment of the present invention will be described.
本發明亦適用於構造係基板表面之複數端子之配置，自第一主面及第二主面之垂直方向觀看，不僅於X軸方向不同，複數端子之配置於Y軸方向也不同。The present invention is also applicable to the arrangement of a plurality of terminals on the surface of the structure substrate. When viewed from the vertical direction of the first main surface and the second main surface, the arrangement of the plurality of terminals is different not only in the X-axis direction but also in the Y-axis direction.
在此，第6圖係顯示在本發明第4實施態樣之貫通配線基板1B(1)，於表面排列配置複數端子群之狀態之平面圖。又，第7圖係沿第6圖之M2-M2線截取之截面圖，第8圖係沿第6圖之N2-N2線截取之截面圖。Here, FIG. 6 is a plan view showing a state in which a plurality of terminal groups are arranged on the surface of the wiring board 1B (1) according to the fourth embodiment of the present invention. Further, Fig. 7 is a cross-sectional view taken along line M2-M2 of Fig. 6, and Fig. 8 is a cross-sectional view taken along line N2-N2 of Fig. 6.
第4實施態樣之貫通配線基板1B(1)，第6圖及第8圖所示貫通配線之配置，自垂直方向觀看第一主面及第二主面，並非是一貫通配線迂迴繞另一貫通配線之配置(參照第1圖)。具體而言，相鄰貫通配線20A、20B、20C相對X軸方向及Y軸方向傾斜地延伸。依此，相鄰貫通配線20A、20B、20C配置成相互錯開(必然)。因此，如第8圖所示，於基板 10沿垂直方向形成貫通配線到達期望深度，便可實現本發明第4實施態樣之貫通配線基板1B(1)。又，未使用如第1圖所示迂迴繞一貫通配線以配置另一貫通配線之構造，所以可以較第1圖貫通配線短之距離連結第一主面與第二主面。In the fourth embodiment, the through wiring substrate 1B (1) and the arrangement of the through wiring shown in FIGS. 6 and 8 are viewed from the vertical direction, and the first main surface and the second main surface are not viewed as a through wiring. The arrangement of a through wiring (refer to Fig. 1). Specifically, the adjacent through wirings 20A, 20B, and 20C extend obliquely with respect to the X-axis direction and the Y-axis direction. Accordingly, the adjacent through wirings 20A, 20B, and 20C are arranged to be shifted from each other (inevitable). Therefore, as shown in Fig. 8, on the substrate When the through wiring is formed in the vertical direction to reach a desired depth, the through wiring substrate 1B (1) according to the fourth embodiment of the present invention can be realized. Further, since the structure in which one through-wiring is arranged to circumscribe one other through-wiring as shown in Fig. 1 is not used, the first main surface and the second main surface can be connected at a shorter distance than the through-wiring line in Fig. 1 .
接著，說明前述貫通配線基板1A(1)之製造方法。Next, a method of manufacturing the through wiring substrate 1A (1) will be described.
第9A圖~第9D圖係示意顯示貫通配線基板1A(1)之製造方法之步驟順序之截面圖。本實施態樣中，使用厚度500μm之玻璃(石英)基板作為基材。又，本實施態樣之微細孔之製造方法，係使用雷射將石英基板一部分改質後，藉蝕刻法除去改質之部分。9A to 9D are schematic cross-sectional views showing the steps of the manufacturing method of the through wiring substrate 1A (1). In this embodiment, a glass (quartz) substrate having a thickness of 500 μm is used as a substrate. Further, in the method of manufacturing the micropores of the present embodiment, a part of the quartz substrate is modified by using a laser, and the modified portion is removed by etching.
首先，如第9A圖所示，對石英形成之基板10照射雷射光80以於基板10內形成改質部82，該雷射光照射處是將藉後續步驟形成至少微細孔之處。本實施態樣中，使用飛秒雷射作為雷射光80，對基板10內部照射雷射光束以形成焦點81，獲得例如具有數μm~數十μm之直徑之改質部。此時，藉著控制焦點81與基板位置，可形成各種形狀之改質部82。另，形成微細孔之基板10並不限於石英基板，也可使用例如藍寶石等絕緣基板10，或具有含鹼成分等這類其他成分之玻璃基板。玻璃基板之厚度亦可在約150μm~1mm之範圍內適當設定。First, as shown in Fig. 9A, the substrate 10 formed of quartz is irradiated with the laser light 80 to form a modified portion 82 in the substrate 10, and the laser light irradiation portion is formed by at least a fine hole by a subsequent step. In the present embodiment, a femtosecond laser is used as the laser light 80, and the inside of the substrate 10 is irradiated with a laser beam to form a focal point 81, and a modified portion having a diameter of, for example, several μm to several tens of μm is obtained. At this time, by controlling the focus 81 and the substrate position, the modified portions 82 of various shapes can be formed. Further, the substrate 10 on which the micropores are formed is not limited to the quartz substrate, and an insulating substrate 10 such as sapphire or a glass substrate having other components such as an alkali component may be used. The thickness of the glass substrate can also be appropriately set within a range of about 150 μm to 1 mm.
接著，如第9B圖所示，將形成有改質部82之基板10浸漬於倒入容器90內之預定藥液91中。依此，改質部82藉藥液被濕蝕刻而自基板10內被除去。於是，如第9C圖所示，存在有改質部82之部分，可形成微細孔83(貫通孔21)。本實 施態樣中，使用主成分為氟酸之酸溶液作為藥液。Next, as shown in FIG. 9B, the substrate 10 on which the modified portion 82 is formed is immersed in a predetermined chemical liquid 91 poured into the container 90. Accordingly, the modified portion 82 is removed from the substrate 10 by wet etching. Then, as shown in Fig. 9C, the portion of the reforming portion 82 is present, and the fine holes 83 (through holes 21) can be formed. Real In the embodiment, an acid solution having a main component of hydrofluoric acid is used as a chemical solution.
本實施態樣所用蝕刻方式，係利用改質部82較未改質部分快許多被蝕刻之現象，最後可形成具有依循改質部82之形狀之微細孔83。本實施態樣中，微細孔83之孔徑為50μm。另，藥液並不限於氟酸，還可使用例如於氟酸添加適量硝酸等之硝酸系混合酸等，或氫氧化鉀溶液此類鹼溶液等。又，微細孔之孔徑，可因應貫通配線用途而在約10μm~300μm之範圍內適當設定。此外，藉前述方法形成之微細孔83，並不限於貫通基板10之貫通孔，亦可是未貫通基板10之非貫通孔。The etching method used in the present embodiment is such that the modified portion 82 is etched much faster than the unmodified portion, and finally, the fine holes 83 having the shape of the modified portion 82 can be formed. In the present embodiment, the pore diameter of the fine pores 83 is 50 μm. Further, the chemical solution is not limited to hydrofluoric acid, and for example, a nitric acid mixed acid or the like in which an appropriate amount of nitric acid or the like is added to the hydrofluoric acid, or an alkali solution such as a potassium hydroxide solution may be used. Further, the pore diameter of the fine pores can be appropriately set in the range of about 10 μm to 300 μm in accordance with the use of the through wiring. Further, the micropores 83 formed by the above method are not limited to the through holes penetrating through the substrate 10, and may be non-through holes that do not penetrate the substrate 10.
藉前述方法，可形成於石英構成之基板10內部具有三維自由構造之微細孔83。According to the above method, the micropores 83 having a three-dimensional free structure inside the substrate 10 made of quartz can be formed.
然後，如第9D圖所示，於微細孔83之內部充填導電性物質84(導體22)。本實施態樣中，係使用金錫(Au-Sn)作為導電性物質84(導體22)，且藉熔融金屬充填法充填於微細孔內部。熔融金屬充填法，係利用壓力差而可在短時間內氣密性佳地充填微細孔內部之方法。另，本實施態樣係使用金錫(Au-Sn)作為充填金屬，不過並不限於此。可使用具有不同組成之金錫合金或錫(Sn)、銦(In)等金屬，以及錫鉛(Sn-Pb)系、錫(Sn)基、鉛(Pb)基、金(Au)基、銦(In)基、鋁(Al)基等焊料。又，充填方法雖是使用熔融金屬吸入法，不過不限於此，也可適當使用鍍敷法之金屬充填、CVD(化學氣相沈積法)、超臨界成膜法之金屬膜形成法、印刷法之導電性糊充填法，或者組合該等方法之方法等。Then, as shown in Fig. 9D, the inside of the micropores 83 is filled with a conductive material 84 (conductor 22). In the present embodiment, gold-tin (Au-Sn) is used as the conductive material 84 (conductor 22), and the inside of the fine pores is filled by a molten metal filling method. The molten metal filling method is a method in which the inside of the fine pores can be filled with a good airtightness in a short time by using a pressure difference. Further, in the present embodiment, gold-tin (Au-Sn) is used as the filler metal, but it is not limited thereto. Metal tin alloys having different compositions or metals such as tin (Sn), indium (In), tin-lead (Sn-Pb), tin (Sn), lead (Pb), gold (Au), Solder such as indium (In) based or aluminum (Al) based. Further, although the filling method is a molten metal suction method, it is not limited thereto, and a metal filling method by a plating method, a CVD (chemical vapor deposition method), a metal film forming method by a supercritical film forming method, and a printing method can be suitably used. The conductive paste filling method, or a method of combining the methods, and the like.
藉以上方法，可提供具有複數貫通配線20之貫通配線基板1A(1)。According to the above method, the through wiring substrate 1A(1) having the plurality of through wirings 20 can be provided.
另，前述實施態樣中，採用微細孔83貫通基板10之構造，不過本發明並不限於此構造。舉例而言，亦可先於基板10形成非貫通孔之微細孔83，再將金屬充填於微細孔後，研磨基板10以形成貫通配線20。Further, in the above embodiment, the structure in which the micropores 83 penetrate the substrate 10 is employed, but the present invention is not limited to this configuration. For example, the micropores 83 of the non-through holes may be formed on the substrate 10, and after the metal is filled in the micropores, the substrate 10 may be polished to form the through wirings 20 .
接著，說明使用前述本發明貫通配線基板1A(1)之電子元件封裝體。Next, an electronic component package using the above-described through wiring substrate 1A (1) of the present invention will be described.
第10圖~第12圖係示意顯示本發明電子元件封裝體之實施態樣(構成例)之平面圖。又，第11圖係沿第10圖之M3-M3線截取之截面圖。第12圖係沿第10圖之N3-N3線截取之截面圖。10 to 12 are plan views schematically showing an embodiment (constitution example) of the electronic component package of the present invention. Further, Fig. 11 is a cross-sectional view taken along line M3-M3 of Fig. 10. Fig. 12 is a cross-sectional view taken along line N3-N3 of Fig. 10.
此電子元件封裝體50係於貫通配線基板1之至少一主面封裝電子元件。如前述，至少相鄰貫通配線20相互錯開配置於貫通配線基板1，所以即使貫通配線之數量增加，仍可抑制基板10之厚度增加。藉此，可促進具有前述電子元件封裝體之電子裝置之薄型化、小型化、高速化等等The electronic component package 50 is formed by packaging electronic components on at least one main surface of the wiring board 1. As described above, at least the adjacent through wirings 20 are disposed so as to be shifted from each other across the wiring board 1. Therefore, even if the number of through wirings is increased, the thickness of the substrate 10 can be suppressed from increasing. Thereby, it is possible to promote thinning, miniaturization, high speed, and the like of the electronic device having the electronic component package.
此電子元件封裝體50包含有：貫通配線基板1，係具有貫通配線20者，且該貫通配線20是於形成在基板10之貫通孔21充填導體或形成導體之膜；第一元件51，係配置於基板10之第一主面10a者；及第二元件53，係配置於基板10之第二主面10b側者。第一元件51之電極配置與第二元件53之電極配置是相互不同。The electronic component package 50 includes a through wiring substrate 1 having a through wiring 20, and the through wiring 20 is a film formed by filling a conductor or forming a conductor in the through hole 21 of the substrate 10; the first element 51 is The second main element 53 is disposed on the first main surface 10a of the substrate 10; and the second element 53 is disposed on the second main surface 10b side of the substrate 10. The electrode configuration of the first member 51 and the electrode configuration of the second member 53 are different from each other.
藉貫通配線基板1，配置於基板10之第一主面10a之第一元件51之複數電極52A、52B、52C...與配置於基板10之第二主面10b之第二元件53之複數電極54A、54B、54C...，藉由複數貫通配線20A、20B、20C...而電連接。The plurality of electrodes 52A, 52B, 52C, ... disposed on the first element 51 of the first main surface 10a of the substrate 10 and the second element 53 disposed on the second main surface 10b of the substrate 10 are interposed by the wiring board 1. The electrodes 54A, 54B, 54C, ... are electrically connected by a plurality of through wirings 20A, 20B, 20C.
元件51、53可例舉如記憶體(記憶構件)和邏輯(邏輯構件)等積體電路(IC)、感測器等MEMS(微機電系統)元件、發光部件和受光部件等光學元件。元件51、53之電極配置若不相同，元件51、53之功能可相異或相同。尤其係以高密度集積異質元件，可實現三維系統級封裝(SiP)。The elements 51 and 53 may be, for example, an integrated circuit such as a memory (memory member) and a logic (logic member), an MEMS (Micro Electro Mechanical System) device such as a sensor, or an optical element such as a light-emitting member or a light-receiving member. If the electrode configurations of the elements 51, 53 are different, the functions of the elements 51, 53 may be different or the same. In particular, high-density accumulating heterogeneous components enables three-dimensional system-in-package (SiP).
又，如第11圖所示，在電子元件封裝體50，露出之第二部位25之端部及第三部位26之端部之至少其中之一，配置於相對所封裝元件51、53之電極52、54之位置。前述元件51、53之電極與前述第二部位25之端部及第三部位26之端部之至少其中之一，宜電連接。依此，封裝於貫通配線基板1之兩面之元件51之電極52(52A、52B、52C)與元件53之電極54(54A、54B、54C)，可電連接而無須藉由表面配線，所以即使是電極以任何佈置狀態高密度配置之小型元件，仍可自由連接電極52與電極54。Further, as shown in FIG. 11, at least one of the end portion of the exposed second portion 25 and the end portion of the third portion 26 in the electronic component package 50 is disposed on the electrode of the packaged component 51, 53. 52, 54 position. Preferably, the electrodes of the elements 51, 53 and at least one of the ends of the second portion 25 and the ends of the third portion 26 are electrically connected. Accordingly, the electrodes 52 (52A, 52B, 52C) of the element 51 packaged on both sides of the wiring board 1 and the electrodes 54 (54A, 54B, 54C) of the element 53 can be electrically connected without the need for surface wiring, so even It is a small component in which the electrodes are arranged at a high density in any arrangement state, and the electrode 52 and the electrode 54 can still be freely connected.
本發明之電子零件，至少包含有前述本發明之電子元件封裝體50。依此，依此，可促進包含有前述電子元件封裝體之電子裝置(電子零件)之薄型化、小型化、高速化等等。The electronic component of the present invention includes at least the electronic component package 50 of the present invention described above. According to this, it is possible to promote thinning, miniaturization, high speed, and the like of the electronic device (electronic component) including the electronic component package.
以上，說明關於本發明之貫通配線基板、電子元件封裝體及電子零件，不過本發明技術範圍並不限於前述實施態 樣，而是可在未脫離本發明主旨之範圍內，加入各種變更。Although the through wiring substrate, the electronic component package, and the electronic component of the present invention have been described above, the technical scope of the present invention is not limited to the above embodiment. Various changes may be added without departing from the spirit and scope of the invention.
本發明廣泛適用於具有貫通配線之貫通配線基板，及使用該貫通配線基板之電子元件封裝體、電子零件。The present invention is widely applicable to a through wiring board having through wiring, and an electronic component package and an electronic component using the through wiring board.
1,1A,1B‧‧‧貫通配線基板1,1A, 1B‧‧‧through wiring board
10‧‧‧基板10‧‧‧Substrate
10a,110a‧‧‧第一主面10a, 110a‧‧‧ first main face
10b,110b‧‧‧第二主面10b, 110b‧‧‧ second main surface
2,3‧‧‧墊件2,3‧‧‧ cushions
20‧‧‧貫通配線20‧‧‧through wiring
20A,20B,20C,120A’,120B’,120C’‧‧‧貫通配線20A, 20B, 20C, 120A', 120B', 120C'‧‧‧through wiring
21‧‧‧貫通孔21‧‧‧through holes
21a,21b‧‧‧開口部21a, 21b‧‧‧ openings
22‧‧‧導體22‧‧‧Conductor
24‧‧‧第一部位24‧‧‧ first part
25‧‧‧第二部位25‧‧‧Second part
26‧‧‧第三部位26‧‧‧ third part
28,29‧‧‧彎曲部28,29‧‧‧Bend
30A,30B,30C‧‧‧第一端子30A, 30B, 30C‧‧‧ first terminal
30A’,30B’,30C’‧‧‧第二端子30A', 30B', 30C'‧‧‧ second terminal
40‧‧‧流路40‧‧‧flow path
40a,40b‧‧‧出入口40a, 40b‧‧‧ entrance
50‧‧‧電子元件封裝體50‧‧‧Electronic component package
51‧‧‧第一元件51‧‧‧ first component
52A,52B,52C,54A,54B,54C‧‧‧電極52A, 52B, 52C, 54A, 54B, 54C‧‧‧ electrodes
53‧‧‧第二元件53‧‧‧second component
80‧‧‧雷射光80‧‧‧Laser light
81‧‧‧焦點81‧‧‧ focus
82‧‧‧改質部82‧‧‧Transformation Department
83‧‧‧微細孔83‧‧‧Micropores
84‧‧‧導電性物質84‧‧‧ Conductive substances
90‧‧‧容器90‧‧‧ container
91‧‧‧藥液91‧‧‧ liquid
130A,130B,130C,130A’,130B’,130C’‧‧‧端子130A, 130B, 130C, 130A', 130B', 130C'‧‧‧ terminals
S1,S2‧‧‧軸(假想軸)S1, S2‧‧‧ axis (imaginary axis)
第1圖係示意顯示本發明貫通配線基板之第1實施態樣之平面圖。Fig. 1 is a plan view schematically showing a first embodiment of a through wiring board of the present invention.
第2圖係沿第1圖之M1-M1線截取之截面圖。Fig. 2 is a cross-sectional view taken along the line M1-M1 of Fig. 1.
第3圖係沿第1圖之N1-N1線截取之截面圖。Fig. 3 is a cross-sectional view taken along the line N1-N1 of Fig. 1.
第4圖係用以說明本發明貫通配線基板之第1實施態樣中貫通配線配置之放大截面圖。Fig. 4 is an enlarged cross-sectional view showing the arrangement of the through wiring in the first embodiment of the through wiring board of the present invention.
第5圖係示意顯示本發明貫通配線基板之第2實施態樣之截面圖。Fig. 5 is a cross-sectional view showing a second embodiment of the through wiring substrate of the present invention.
第6圖係示意顯示本發明貫通配線基板之第4實施態樣之平面圖。Fig. 6 is a plan view schematically showing a fourth embodiment of the through wiring substrate of the present invention.
第7圖係沿第6圖之M2-M2線截取之截面圖。Fig. 7 is a cross-sectional view taken along line M2-M2 of Fig. 6.
第8圖係沿第6圖之N2-N2線截取之截面圖。Figure 8 is a cross-sectional view taken along line N2-N2 of Figure 6.
第9A圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9A is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第9B圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9B is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第9C圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9C is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring board.
第9D圖係示意顯示貫通配線基板之製造方法之步驟之截面圖。Fig. 9D is a cross-sectional view schematically showing the steps of a method of manufacturing a through wiring substrate.
第10圖係示意顯示本發明電子元件封裝體之一例之平面圖。Fig. 10 is a plan view schematically showing an example of the electronic component package of the present invention.
第11圖係沿第10圖之M3-M3線截取之截面圖。Figure 11 is a cross-sectional view taken along line M3-M3 of Figure 10.
第12圖係沿第10圖之N3-N3線截取之截面圖。Fig. 12 is a cross-sectional view taken along line N3-N3 of Fig. 10.
第13圖係示意顯示習知貫通配線基板之一例之平面圖。Fig. 13 is a plan view showing an example of a conventional through wiring substrate.
第14圖係沿第13圖之M4-M4線截取之截面圖。Figure 14 is a cross-sectional view taken along line M4-M4 of Figure 13.
第15圖係沿第13圖之N4-N4線截取之截面圖。Figure 15 is a cross-sectional view taken along line N4-N4 of Figure 13.
1,1A‧‧‧貫通配線基板1,1A‧‧‧through wiring board
10‧‧‧基板10‧‧‧Substrate
10a‧‧‧第一主面10a‧‧‧ first main face
10b‧‧‧第二主面10b‧‧‧second main face
20A,20B,20C‧‧‧貫通配線20A, 20B, 20C‧‧‧through wiring
24‧‧‧第一部位24‧‧‧ first part
S1,S2‧‧‧軸(假想軸)S1, S2‧‧‧ axis (imaginary axis)
Claims (10)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011107580 | 2011-05-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201306678A TW201306678A (en) | 2013-02-01 |
| TWI439192B true TWI439192B (en) | 2014-05-21 |
Family
ID=47139316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW101116874A TWI439192B (en) | 2011-05-12 | 2012-05-11 | Interposer substrate, electronic device package, and electronic component |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20130335936A1 (en) |
| JP (2) | JPWO2012153842A1 (en) |
| CN (1) | CN103430636A (en) |
| TW (1) | TWI439192B (en) |
| WO (1) | WO2012153842A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6449132B2 (en) * | 2015-11-04 | 2019-01-09 | アルプス電気株式会社 | Signal processing device |
| JP6727937B2 (en) * | 2016-06-10 | 2020-07-22 | 日本電波工業株式会社 | Electronic device |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5222014A (en) * | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
| US5810607A (en) * | 1995-09-13 | 1998-09-22 | International Business Machines Corporation | Interconnector with contact pads having enhanced durability |
| US6246247B1 (en) * | 1994-11-15 | 2001-06-12 | Formfactor, Inc. | Probe card assembly and kit, and methods of using same |
| JP3681542B2 (en) * | 1998-07-01 | 2005-08-10 | 富士通株式会社 | Printed circuit boards and relay boards for multistage bumps |
| US7579848B2 (en) * | 2000-05-23 | 2009-08-25 | Nanonexus, Inc. | High density interconnect system for IC packages and interconnect assemblies |
| US6441629B1 (en) * | 2000-05-31 | 2002-08-27 | Advantest Corp | Probe contact system having planarity adjustment mechanism |
| US6344684B1 (en) * | 2000-07-06 | 2002-02-05 | Advanced Micro Devices, Inc. | Multi-layered pin grid array interposer apparatus and method for testing semiconductor devices having a non-pin grid array footprint |
| US6970362B1 (en) * | 2000-07-31 | 2005-11-29 | Intel Corporation | Electronic assemblies and systems comprising interposer with embedded capacitors |
| US6914786B1 (en) * | 2001-06-14 | 2005-07-05 | Lsi Logic Corporation | Converter device |
| US7327554B2 (en) * | 2003-03-19 | 2008-02-05 | Ngk Spark Plug Co., Ltd. | Assembly of semiconductor device, interposer and substrate |
| JP2005093946A (en) * | 2003-09-19 | 2005-04-07 | Ngk Spark Plug Co Ltd | Ceramic wiring board and component mounted wiring board using it |
| JP5180634B2 (en) * | 2007-04-24 | 2013-04-10 | パナソニック株式会社 | Differential transmission line |
| EP2453725A1 (en) * | 2009-07-10 | 2012-05-16 | Fujikura, Ltd. | Through-wiring board and method of manufacturing same |
| CN102598879A (en) * | 2009-10-23 | 2012-07-18 | 株式会社藤仓 | Device mounting structure and device mounting method |
-
2012
- 2012-05-11 WO PCT/JP2012/062157 patent/WO2012153842A1/en active Application Filing
- 2012-05-11 TW TW101116874A patent/TWI439192B/en not_active IP Right Cessation
- 2012-05-11 JP JP2013514072A patent/JPWO2012153842A1/en active Pending
- 2012-05-11 CN CN201280012422XA patent/CN103430636A/en active Pending
-
2013
- 2013-08-16 US US13/968,886 patent/US20130335936A1/en not_active Abandoned
-
2014
- 2014-08-27 JP JP2014173294A patent/JP2014225702A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012153842A1 (en) | 2012-11-15 |
| US20130335936A1 (en) | 2013-12-19 |
| JP2014225702A (en) | 2014-12-04 |
| CN103430636A (en) | 2013-12-04 |
| JPWO2012153842A1 (en) | 2014-07-31 |
| TW201306678A (en) | 2013-02-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI656615B (en) | Three-dimensional integrated heat dissipation gain type semiconductor group and manufacturing method thereof | |
| TW201304107A (en) | Interposer substrate, electronic device package, and electronic component | |
| EP2234158A1 (en) | A three-dimensional electronics package | |
| US10446526B2 (en) | Face-to-face semiconductor assembly having semiconductor device in dielectric recess | |
| TWI596680B (en) | Low cte component with wire bond interconnects | |
| JP5384700B2 (en) | Device mounting structure and device mounting structure manufacturing method | |
| JP6153471B2 (en) | Microelectronic units, stacked assemblies, systems, and modules | |
| JP4942857B2 (en) | Device mounting structure and device mounting method | |
| US20120205148A1 (en) | Device packaging structure and device packaging method | |
| KR20130054424A (en) | Method of making a multi-chip module having a reduced thickness and related devices | |
| TWI439192B (en) | Interposer substrate, electronic device package, and electronic component | |
| US20120103677A1 (en) | Through wiring substrate and manufacturing method thereof | |
| JP2011155199A (en) | Circuit mounting substrate | |
| JP2008203336A (en) | Opto-electric composite substrate, manufacturing method thereof and electronic equipment | |
| US20140254120A1 (en) | Device packaging structure and device packaging method | |
| KR101068305B1 (en) | Stack semiconductor package and manufacturing method therof | |
| JP2011018672A (en) | Semiconductor device, and method of manufacturing the same | |
| CN115172328A (en) | Conductive assembly for multi-chip packaging and manufacturing method thereof | |
| CN114823387A (en) | Board-level system-in-package method and package structure | |
| JP2006013305A (en) | Semiconductor device, circuit substrate, and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |