TWI439057B - Data selector used in digital-to-analog converter and the digital-to-analog converter - Google Patents

Description

Data selector for digital analog converter and the digital analog converter

The present invention relates to a digital analog converter, and more particularly to a digital analog converter suitable for a liquid crystal display (LCD) driving circuit.

The liquid crystal display is a flat ultra-thin display device, and the screen is composed of a pixel array. The structure of the pixel includes transparent electrodes on both sides and a liquid crystal molecular layer suspended therein, and polarizing filters perpendicular to each other on both sides. The direction of polarization of the light passing through a layer of polarizing filters is rotated by the layer of liquid crystal molecules and then transmitted through another layer of polarizing filters. The polarization direction of the liquid crystal molecular layer is adjusted with the voltage of the electrodes on both sides. If no electrode is applied to both sides of the liquid crystal molecular layer, the light that has penetrated through the liquid crystal molecular layer is bound to be blocked by the polarizing filter of the other layer.

The color filter can form three primary colors of red (R), green (G), and blue (B), and the voltage supplied to the pixel electrodes on both sides of the liquid crystal molecular layer can determine the gray scale of the colors of R, G, and B. Values, which in turn produce different colors. The driving circuit in the liquid crystal display is used to provide different driving voltages to the pixel electrodes to adjust the degree of rotation of the liquid crystal molecular layer. The drive circuit is mainly divided into a gate driver and a source driver (also called a column driver), and the timing control between the two is controlled by a timing controller.

The source driver has a digital analog converter that converts the digital signal to a different pixel voltage for output to the pixel electrode. Digital analog converters in source drivers are currently dominated by 8-bit, but high color depth liquid crystal displays require higher bit source drivers, such as 10-bit. The high-order source driver is usually implemented by a two-stage resistor string, for example, the first-stage resistor string corresponds to a higher-priority 6-bit, and the second-stage resistor string corresponds to a lower-weight 4-bit. Bit. Since different channel circuits can share the voltage division of the same first-stage resistor string, such a circuit structure can reduce the circuit area and reduce the circuit design cost. However, when the second-stage resistor string is connected in parallel to the voltage dividing point of the first-stage resistor string, current is shunted to the second-stage resistor string, thus affecting the accuracy of the voltage division. Therefore, a circuit of a unit gain amplifier is provided between the first-stage resistor string and the second-stage resistor string to isolate the two resistor strings, but the circuit area of the unity gain amplifier is large and the circuit design cost is high. If a unity gain amplifier is placed between the two-stage resistor strings, the circuit area and cost of the high-order digital analog converter will be greatly increased.

The invention provides a digital analog converter with a circuit for compensating current, which can be used to compensate the current required by the second resistor string (channel resistor string), so that there is no need to provide an isolated buffer between the two resistor strings. This reduces wafer area and power consumption.

The invention provides a digital analog converter comprising a first resistor string and at least one channel circuit. The first resistor string has a plurality of first resistors connected in series to generate a plurality of first partial voltages. The channel circuit includes a first data selector, a second resistor string and a second data selector. The first data selector is coupled to the first resistor string for selecting two adjacent partial voltages of the first partial voltages to generate a voltage interval. The second resistor string has a plurality of second resistors connected in series, and the second resistor string is coupled to the first data selector for dividing the voltage interval into a plurality of second partial voltages. The second data selector is coupled to the second resistor string for selecting and outputting one of the second partial voltages. The current source circuit is coupled to the two ends of the second resistor string, and generates a compensation current through the second resistor string according to the selected two adjacent voltage dividers to reduce the shunt current flowing from the first resistor string to the second resistor string. .

The invention further provides a digital analog converter comprising a first resistor string, a current source circuit and at least one channel circuit. The first resistor string has a plurality of first resistors connected in series, the first resistor string having a plurality of voltage dividing points to generate a plurality of first partial voltages. The current source circuit has a plurality of sub current sources coupled to each of the voltage dividing points of the first resistor string. The channel circuit includes a first data selector, a second resistor string and a second data selector. The first data selector is coupled to the first resistor string for selecting two adjacent partial voltages of the first partial voltages to generate a voltage interval. The second resistor string has a plurality of second resistors connected in series, and the second resistor string is coupled to the first data selector for dividing the voltage interval into a plurality of second partial voltages. The second data selector is coupled to the second resistor string for selecting and outputting one of the second partial voltages. Wherein, the current source circuit adjusts the current value of each of the sub current sources according to the voltage interval to compensate the shunt current flowing from the first resistor string to the second resistor string.

The invention further proposes a digital analog converter which is a resistive digital analog converter. The voltage division generated by the first resistor string in the digital analog converter is simultaneously provided to multiple channel circuits. Each channel circuit has a second resistor string that generates a plurality of partial voltages according to the selected voltage interval. The digital analog converter includes a general purpose current source for generating a reference current corresponding to the first resistor string and the second resistor string. The channel circuit maps the reference current to generate a compensation current through the second resistor string to reduce the shunt current flowing from the first resistor string to the second resistor string.

In summary, the digital analog converter of the present invention utilizes a compensation current to form a desired voltage division on the second resistor string, thereby simplifying the circuit structure to reduce the circuit area and design cost of the resistive digital analog converter.

The above described features and advantages of the present invention will be more apparent from the following description.

In the following, the invention will be described in detail by the embodiments of the invention, and the same reference numerals are used in the drawings.

(First Embodiment)

1 is a circuit diagram of a digital analog converter according to a first embodiment of the present invention. The digital analog converter 100 includes a first resistor string 111 and at least one channel circuit 120. The first resistor string 111 has a plurality of first resistors R1 connected in series, and the upper and lower ends thereof are respectively coupled to the reference voltage VRH and the reference voltage VRL. A plurality of first partial voltages are generated for use by the channel circuit 120. The channel circuit 120 includes a second resistor string 121, a first data selector 122, a second data selector 123, and a current source circuit including a first current source 124 and a second current source 125. The second resistor string 121 includes a plurality of second resistors R2 connected in series for generating a plurality of second divided voltages. The second data selector 123 is coupled to the voltage dividing point of the second resistor string 121, and selects a corresponding second divided voltage output to the buffer 126 according to the received digital signal to generate a corresponding output voltage OUT1. It should be noted that the first resistor string 111 can be regarded as a common resistor string, and the generated first voltage divider can be simultaneously provided to the plurality of channel circuits 120-140 to reduce the circuit volume. The circuit structures of the channel circuits 120-140 are similar. The channel circuit 120 is taken as an example to describe the operation mode of the circuit.

The digital analog converter 100 in this embodiment is, for example, a resistor-resistor-type DAC (RRDAC), which is a digital analogy that combines two sets of resistive digital analog converters to form higher bits. converter. The first resistor string 111 is responsible for the division of the higher bits, while the second resistor string 121 is responsible for the division of the lower bits. For example, the digital analog converter 100 can be a 10-bit digital analog converter, wherein the higher 6-bit partial voltage is generated by the first resistor string 111, and the second 4-bit divided voltage is generated by the second resistor. String 121 is generated. The number of resistors R1 in the first resistor string 111 is related to the number of bits required. For example, in the case of 6 bits, the first resistor string 111 will have at least 64 resistors R1 to generate 64 divided voltages.

The first data selector 122 is coupled to the voltage dividing point of the first resistor string 111, that is, the connection point of the adjacent resistor R1 to obtain the voltage of each voltage dividing point (ie, the first voltage dividing). The first data selector 122 is, for example, a multiplexer, and can select two adjacent partial voltages from the first resistor string 111 according to the first 6 bits of the digit signal and output through the first output terminal PIN1 and the second output terminal PIN2. The second resistor string 121 is defined to define reference voltages VH, VL across the second resistor string 121. The resistor R2 in the second resistor string 121 divides the voltage interval formed by the reference voltages VH, VL into a plurality of second divided voltages. Taking 4-bit as an example, the second resistor string 121 will have 16 resistors R2 to generate 16 divided voltages. The second data selector 123 is coupled to the second resistor string 121, and can select a corresponding one of the last four bits of the digit signal to the second voltage divider to output to the buffer 126 to generate the output voltage OUT1.

The channel circuit 120 has a current source circuit, and can provide a compensation current I _COMP to the second resistor string 121. The first current source 124 and the second current source 125 are exemplified by the second current source 125. end. The first current source 124 is coupled between the voltage source VDD and the first end of the second resistor string 121 (the reference voltage VH terminal) for mapping a reference current to generate the compensation current I _COMP to the second resistor string 121. The second current source 125 is coupled between the second end of the second resistor string 121 (the reference voltage VL terminal) and the ground GND for mapping the reference current to generate the compensation current I _COMP to the ground GND. The reference current is corresponding to the amount of current shunted by the first resistor string 111 to the second resistor string 121. The compensation current I _COMP generated by the first current source 124 and the second current source 125 can cause the voltage drop across the second resistor string 121 to conform to the required reference voltages VH, VL, thereby reducing the shunt from the first resistor string 111 to the first The current of the two resistor strings 121.

For example, if there is no first current source 124 and second current source 125, when the first data selector 122 couples two voltage dividers of the first resistor string 111 to the second resistor string 121, the second resistor The string 121 shunts a portion of the current from the first resistor string 111 to maintain the voltage across the terminals as reference voltages VH, VL. This is similar to the fact that the second resistor string 121 is connected in parallel to the voltage dividing point of the first resistor 111, which not only affects the current in the first resistor string 111, but also affects the resistance value thereof, resulting in a voltage division error. In the prior art, a buffer is usually used to isolate two resistor strings to avoid mutual influence. In the present invention, the buffer is replaced by a compensation current, thereby reducing the current shunted from the first resistor string 111 to the second resistor string 121.

The compensation current I _COMP is equivalent to the current value originally shunted by the first resistor string 111 to the second resistor string 121, whereby the current 1 shunted by the first resistor string 111 to the second resistor string 121 can approach zero. For example, if the voltage difference (VH-VL) of the divided voltage adjacent to the first resistor string 111 is V and the second resistor string 121 is composed of 16 resistors R2, the compensation current I _COMP is V/(16*R2). ). Since the compensation current I _COMP can already generate the required voltage division of the second resistor string 121, the shunt current shunted by the first resistor string 111 to the second resistor string 121 can be reduced.

The first current source 124 and the second current source 125 may be implemented using a current mirror architecture, but the invention is not limited thereto. Please refer to FIG. 2A. FIG. 2A is a schematic diagram of a current source circuit according to a first embodiment of the present invention. The digital analog converter 100 can include a universal current source 210 coupled to the first resistor string 111 to generate a reference current, and then mapped to the first current source 124 and the second current source 125 to generate a compensation current I _COMP . The general-purpose current source 210 includes PMOS transistors P1 to P3, NMOS transistors N1 to N3, operational amplifiers 211 and 212, and a reference resistor string 221 formed by connecting a plurality of second resistors R2 in series. In this embodiment, the universal current source 210 can generate the reference current I _REF according to the two divided voltages generated by the first resistor string 111 and a reference resistor string 221, wherein the selected two partial voltages do not include the partial voltage Maximum and minimum values. The reference resistor string 221 and the resistance value are associated with the second resistor string 121. In addition, the universal current source 210 can also generate the reference current I _REF directly from the two reference voltages.

In the general-purpose current source 210, the source of the PMOS transistor P1 is coupled to a voltage source VDD; the source of the PMOS transistor P2 is coupled to the drain of the PMOS transistor P1, and the gate is coupled to the bias voltage VB1. The drain of the NMOS transistor N1 is coupled to the drain of the PMOS transistor P2 and the gate of the PMOS transistor P1, and the source thereof is coupled to the first end of the reference resistor string 221. The non-inverting input of the operational amplifier 211 is coupled to the first resistor string 111, and the inverting input is coupled to the source of the NMOS transistor N1, and the output end thereof is coupled to The gate of the NMOS transistor N1. The source of the PMOS transistor P3 is coupled to the second end of the reference resistor string 221. The inverting input terminal of the operational amplifier 212 is coupled to the second terminal of the reference resistor string 221, the non-inverting input terminal is coupled to the first resistor string 111, and the output terminal thereof is coupled to the gate of the PMOS transistor P3. The drain of the NMOS transistor N2 is coupled to the drain of the PMOS transistor P3, and the gate is coupled to the bias voltage VB2. The drain of the NMOS transistor N3 is coupled to the source of the NMOS transistor N2, the source of which is coupled to the ground GND, and the gate of the NMOS transistor N3 is coupled to the drain of the NMOS transistor N2.

There are n first resistors R1 between the operational amplifier 211 and the operational amplifier 212, so the voltage difference is the sum of n partial voltages, where n is a positive integer. Assuming that the second resistor string 121 represents a 4-bit data, each divided voltage in the first resistor string 111 corresponds to 16 second resistors R2. Therefore, the reference resistor string 221 includes (16×n) second resistors R2 to generate a corresponding reference current I _REF . The reference current I _REF flows through the reference resistor string 221 such that the voltage across the reference resistor string 221 is equal to the two divided voltages selected by the operational amplifier 211 and the operational amplifier 212 in the channel circuit 210. The first current source 124 is composed of PMOS transistors P21 and P22 connected in series, and is respectively coupled to the gate of the PMOS transistor P1 and the gate of the PMOS transistor P2 to form a current mirror, thereby mapping the reference current I _REF to generate Compensation current I _COMP . The second current source 125 is composed of NMOS transistors N21 and N22 connected in series, which are respectively coupled to the gate of the NMOS transistor N2 and the gate of the NMOS transistor N3 to form a current mirror, thereby mapping the reference current I _REF to generate compensation. Current I _COMP . The ratio between the reference current I _REF and the compensation current I _COMP and the ratio of the channel aspect ratio of the PMOS transistors P21 and P22 to the channel aspect ratio of the PMOS transistors P1 and P2, and the NMOS transistors N21 and N22 The channel aspect ratio is related to the ratio between the channel aspect ratios of the NMOS transistors N2, N3, and those skilled in the art should be able to infer the calculation thereof via FIG. 2A, which will not be described here.

The reference current I _REF generated by the universal current source 210 can be provided to all of the channel circuits 120-140 to generate a corresponding compensation current I _COMP . A current source structure similar to the first current source 124 and the second current source 125 is disposed at both ends of the second resistor string 121 in each of the channel circuits 120-140, and can be used to map the reference current I _REF to generate a corresponding compensation current. I _COMP . Since the voltage outputted by each of the channel circuits 120-140 is mainly generated by the compensation current I _COMP flowing through the second resistor string 121, the current and the voltage division on the first resistor string 111 are not affected. There is also no need to provide a buffer or unit gain amplifier between the first resistor string 111 and the second resistor string 121 to isolate the resistors on both sides. As shown in FIG. 1, the current I of the first resistor string 111 shunted to the second resistor string 121 approaches zero. Thereby, the circuit area and power consumption can be reduced.

The first data selector 122 can select two partial voltages as the reference voltages VH, VL according to the digital signal, and an embodiment of the internal circuit is as shown in FIG. 2B, and FIG. 2B is the first data according to the first embodiment of the present invention. The internal circuit diagram of the selector 122. As shown in FIG. 2B, the first material selector 122 includes a decoding unit 127 and a switching unit S24. The decoding unit 127 further includes a first decoder D21, a second decoder D22, and a third decoder D23. It is assumed that the first resistor string 111 has 65 voltage dividing points to correspond to the data of 6 bits (000000 to 111111). The input ends of the first decoder D21, the second decoder D22, and the third decoder D23 are respectively coupled to all the voltage dividing points ND1 ND ND65 of the first resistor string 111, and the coupling relationship thereof is as shown in FIG. 2B. The input ends of the first decoder D21 and the third decoder D23 are respectively coupled to the odd-numbered voltage dividing points (ND1, ND3, ..., ND65), wherein the voltage dividing points of the first decoder D21 are ND1~ND63, and The voltage dividing points coupled to the third decoder D23 are ND3~ND65. In addition to the voltage dividing points ND1 and ND65, the first decoder D21 overlaps with the voltage dividing point to which the third decoder D23 is coupled. The second decoder D23 is coupled to the even voltage dividing points (ND2, ND4, . . . ND64) of the first resistor string 111.

In FIG. 2B, the first data selector 122 can generate a desired voltage interval based on a 6-bit digital signal. The first decoder D21, the second decoder D22, and the third decoder D23 are implemented using a decoder suitable for 5 bits, and the output divided voltage can be selected based on a 5-bit digital signal. In this embodiment, the 6-bit digital signal received by the first data selector 122 is divided into a 5-bit most significant byte and a Least Significant Bit (LSB). The most significant byte refers to 5 bits except the least significant bit. The first decoder D21, the second decoder D22, and the third decoder D23 select three adjacent voltage dividing points according to the most significant byte group, and output the divided voltages to the switching unit S24. Each decoder outputs a partial voltage corresponding to the most significant byte.

For example, the input pins of the first decoder D21, the second decoder D22, and the third decoder D23 have values corresponding to the digital signals from bottom to top, as in the multiplexer. For example, when the most significant byte is 00000, the first decoder D21 outputs the divided voltage of the voltage dividing point ND1, the second decoder D22 outputs the voltage dividing of the voltage dividing point ND2, and the third decoder D23 outputs The partial pressure of the partial pressure point ND3. When the most significant byte is 00001, the partial voltages on the voltage dividing points ND3, ND4, and ND5 are respectively output, and such a heap is not described here.

When the least significant bit of the digital signal is 0, the switching unit S24 outputs the output of the first decoder D21 as the reference voltage VL, and outputs the output of the second decoder D22 as the reference voltage VH. When the least significant bit of the digital signal is 1, the switching unit S24 outputs the output of the second decoder D22 as the reference voltage VL, and outputs the output of the third decoder D23 as the reference voltage VH. Due to the coupling manner of the first decoder D21, the second decoder D22 and the third decoder D23 and each of the voltage dividing points ND1 ND ND65, the voltage dividing points of the outputs are adjacent. The switching unit S24 outputs two of the three partial pressures to the first output terminal PIN1 and the second output terminal PIN2 of the first data selector 122 as the reference voltages VH, VL according to the least significant bit.

The first decoder D21, the second decoder D22, and the third decoder D23 are, for example, 32-to-1 multiplexers, and the conduction path can be selected according to the most significant byte of 5 bits. In the application of the present invention, the main difference is that the input and the voltage dividing points of the multiplexer are distributed differently than conventionally. After the description of the above embodiments, those skilled in the art should be able to infer how to implement the first decoder D21, the second decoder D22 and the third decoder D23 by using a multiplexer, which will not be described here. In this embodiment, by using the interleaved configuration fraction and the utilization switching unit S24, the required voltage interval can be output correspondingly. The circuit of the switching unit S24 is formed by four switches forming different switching paths. For convenience of explanation, the 2-bit decoder is used to illustrate the architecture of the switching circuit. Please refer to FIG. 2C. FIG. 2C is a schematic diagram of an internal circuit of a decoder and a switching unit according to an embodiment of the present invention. In Figure 2C, the 3-bit digital signal is represented by b2b1b0, where b0 is the least significant bit and b2b1 is the most significant byte. The input ends of the first decoder DX21, the second decoder DX22, and the second decoder DX23 are respectively coupled to the nine voltage dividing points ND1 ND ND9, and the coupling manner thereof is as described above in FIG. 2B, and is not described here. .

The enabling relationship of each of the first decoder DX21, the second decoder DX22 and the second decoder DX23 and the most significant byte b2b1 is as shown in FIG. 2C, and each of the switches is based on the corresponding bit. Element b2, b1, non-b2 (negation of b2 or b2 bar), non-b1 (negation of b1 or b1 bar) are turned on. The switching unit SX24 includes a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The first switch SW1 is coupled to the output end of the third decoder DX23 and the first output terminal PIN1 of the first data selector 122. The second switch SW2 is coupled to the output of the first decoder DX21 and the second output PIN2 of the first data selector 122. The third switch SW3 is coupled to the output end of the second decoder DX22 and the first output terminal PIN1 of the first data selector 122. The fourth switch SW4 is coupled to the output end of the second decoder DX22 and the second output terminal PIN2 of the first data selector 122. Wherein, when the least significant bit is 1, the first switch SW1 and the fourth switch SW4 are turned on, and when the least significant bit is 0, the second switch SW2 and the third switch SW3 are turned on. The circuit architecture of the switching unit SX24 can be directly applied to the switching unit S24 in FIG. 2B, and its coupling relationship with the first decoder D21, the second decoder D22 and the third decoder D23 is as shown in FIG. 2C, and has a technical field in the art. Generally, the knowledge person should be able to infer the calculation method according to FIG. 2, which is not described here.

The buffer 126 is formed by a negative feedback operational amplifier, and its internal circuit is formed, for example, by a cascode class-AB amplifier. The circuit is shown in FIG. 3. FIG. 3 illustrates the first embodiment of the present invention. A schematic diagram of the circuit configuration of a cascaded configuration class AB amplifier. The operational amplifier forming the buffer 126 is composed of transistors M1~M20, wherein the transistors M1~M3, M7, M8, M11, M14, M15, M18, M19 are P-type transistors; the transistors M4~M6, M9, M10, M12, M13, M16, M17, and M20 are N-type transistors. The gate of the transistor M1 is coupled to the bias voltage VB31; the gate of the transistor M4 is coupled to the bias voltage VB32; the gates of the transistors M11 and M15 are coupled to the bias voltage VB33; and the gates of the transistors M13 and M17 are coupled. Connected to the bias voltage VB34. The transistors M1~M6 are differential input stage circuits, wherein the transistors M1~M3 are P-type transistors, and the transistors M5~M6 are N-type transistors, wherein the gates of the transistors M3 and M6 are extremely non-inverting of the operational amplifier. The input is represented by the end point in+; the gates of the transistors M2 and M5 are the inverting input of the operational amplifier, indicated by the end point in-. The source of the transistor M1 is coupled to the voltage source VDD; the source of the transistor M4 is coupled to the ground GND. The transistor M11~M18 is a circuit structure of a cascade configuration class AB amplifier, which can accurately control the quiescent current of the output transistor, and can reduce the sensitivity of the static circuit to the voltage source. The transistors M7, M8, M9, and M10 are current mirror structures, and the transistors M19 and M20 are output stage circuits, and the common contacts (drains) of the transistors M19 and M20 are used to generate the output voltage OUT1. The circuit architecture of the operational amplifier is shown in Figure 3 and will not be described here. There are many ways to implement an operational amplifier circuit. Those skilled in the art will be able to deduce other embodiments of the operational amplifier after the description of the above embodiments, and will not be described here.

(Second embodiment)

Please refer to FIG. 4. FIG. 4 is a schematic circuit diagram of a digital analog converter 400 according to a second embodiment of the present invention. The main difference between FIG. 4 and FIG. 1 above is the coupling relationship between the first data selector 122 and the second resistor string 121. In FIG. 1 , the first data selector 122 has two outputs coupled to the two ends of the second resistor string 121 . In FIG. 4, the first data selector 122 has only one output terminal coupled to the first end of the second resistor string 121 (reference voltage VH terminal) to output the selected divided voltage to the second resistor string 121. As the reference voltage VH. In comparison with FIG. 1, in FIG. 4, the first data selector 122 outputs the selected one divided voltage (from the first resistor string 111) to the second resistor string 121 as the reference voltage VH. Since the first current source 124 and the second current source 125 generate the compensation current I _COMP , each voltage division in the second resistor string 121 is correspondingly generated as long as the voltage level of the reference voltage VH is determined.

In another embodiment of the present invention, the output of the first data selector 122 is not necessarily coupled to the first end of the second resistor string 121 (reference voltage VH terminal), and it may be coupled to the second Any point in the resistor string 121 (any one of the voltage dividing points), of course, also includes the second end of the second resistor string 121 (reference voltage VL terminal). First, since the current source 124 and the second current source 125 still generate the compensation current I _COMP , each voltage division in the second resistor string 121 is generated correspondingly as long as the voltage level at any point on the second resistor string 121 is determined. . In the channel circuits 420-440 of FIG. 4, except for the coupling relationship between the first data selector 122 and the second resistor string 121, the remaining circuit architecture is similar to that of FIG. 1. Those skilled in the art should be able to It is inferred from the description of the first embodiment that it will not be described here.

(Third embodiment)

Since the second resistor string 121 is coupled to the voltage dividing point of the first resistor string 111, the resistance value between the voltage dividing points and the current shunting are affected. To avoid the above situation, the present invention uses a current compensation technique to reduce The influence of the second resistor string 121 on the first resistor string 111. As shown in FIG. 1 above, current sources 124, 125 are disposed in channel circuit 120 to generate a compensation current I _COMP , thereby reducing the current shunted from first resistor string 111 to second resistor string 121. The design principle of the current sources 124, 125 can also be applied to the first resistor string 111 to prevent the second resistor string 121 from affecting the first resistor string 111.

Please refer to FIG. 5. FIG. 5 is a schematic circuit diagram of a digital analog converter according to a third embodiment of the present invention. The main difference between FIG. 5 and FIG. 1 is that the current source circuit 510 is disposed on the first resistor string 111 instead of the second resistor string 121. Current source circuit 510 includes a plurality of sub-current sources 151, 152, controller 511 and current mode digital analog converter 512. Each of the voltage dividing points of the first resistor string 111 has a sub current source I51 and a sub current source I52. The current direction of the sub current source I51 flows into the voltage dividing point, and the current direction of the sub current source I52 flows out from the voltage dividing point. Each of the sub-current sources I51, I52 is a variable current source that can adjust the current. The controller 511 is coupled to the current mode digital analog converter 512, and the current mode digital analog converter 512 is coupled to each of the sub current sources I51, I52 to control the current value of each of the sub current sources I51, I52. The first data selection 122 is coupled between the first resistor string 111 and the second resistor string 121, and selects two divided voltages of the first resistor string 111 according to the received digit signal to output to both ends of the second resistor string 121. . The second data selector 123 selects a divided voltage from the second resistor string 121 to output to the buffer 126, and then generates an output voltage OUT1. The divided voltage selected by the second data selector 123 according to the digital signal is an analog output voltage corresponding to the digital signal. For example, the digital signal may be a grayscale value corresponding to a pixel, and the output voltage OUT1 is a pixel voltage corresponding to the grayscale value.

The controller 511 generates a control signal to the current mode digital analog converter 512 based on the input signal INT. The input signal INT corresponds to the two divided points selected. The current mode digital analog converter 512 calculates how much current will be shunted by each voltage dividing point to the second resistor string 121 based on the control signal, and how much current is returned from the second resistor string 121 for each voltage dividing point. Then, each of the sub current sources I51, I52 is controlled to generate a corresponding current to cancel the influence of the second resistor string 121 on the first resistor string 111. For example, if the voltage dividing points selected by the channel circuit 520 are N51 and N52, the current mode digital analog converter 512 calculates the shunt current value required by the second resistor string 121, and then controls the coupling to the voltage dividing point N51. The sub current source I51 and the sub current source I52 coupled to the voltage dividing point N52 generate a corresponding compensation current to compensate the shunt current flowing from the first resistor string 111 to the second resistor string 121.

For example, if the current flowing through the second resistor string 121 is shunted into the compensation current I _COMP , the sub current source I51 generates a compensation current I _COMP flowing into the voltage dividing point N51, and the sub current source N52 also generates a corresponding value. The compensation current I _COMP flows out from the voltage dividing point N52. Thereby, the current shunt that is shunted from the first current string 111 to the second resistor string 121 is compensated. Since the current directions of the sub current source I51 and the sub current source I52 are respectively flowing in and out, the voltage division of the resistors other than the voltage dividing points N51 and N52 is not affected by the compensation current I _COMP , and the original partial voltage can be maintained. . The current shunt required by the second resistor string 121 is directly provided by the compensating current I _COMP generated by the sub current source I51 and the sub current source I52, so the second resistor string 121 does not affect the original fraction of the first resistor string 111. Pressure. In addition, when the second resistor string 121 is coupled to the voltage dividing points N51 and N52 of the first resistor string 111, the resistance between the two ends of the voltage dividing points N51 and N52 may be due to the parallel connection of the resistors. Parallel and smaller. Therefore, in order to maintain the voltage drop across the voltage dividing points N51, N52, more current must flow. The difference between this current and the current on the original first resistor string 111 is the value of the compensation current I _COMP . By compensating for the generation of the current I _COMP , the second resistor string 121 can be made to generate a corresponding partial voltage, and the second resistor string 121 can be prevented from affecting the original voltage division of the first resistor string 111.

Similarly, when multiple channel circuits 520-540 use the same voltage dividing point at the same time, the current mode digital analog converter 512 adjusts the voltage at each voltage dividing point according to the current shunt required by the channel circuits 520~540. Current sources I51, I52. For example, when the channel circuits 520 and 530 share the voltage dividing points N51 and N52, the sub current source I51 at the voltage dividing point N51 and the sub current source I52 at the voltage dividing point N52 generate twice the compensation current I _COMP. . Since each of the channel circuits 520-540 may be coupled to the voltage dividing point, each of the sub-power sources I51 and I52 generates a compensation current according to the corresponding voltage dividing point and its required shunt current to compensate the first resistor string 111. The current is shunted to the second resistor string 121 while the current flowing back from the second resistor string 121 to the first resistor string 111 is drained to the ground to avoid affecting the original voltage division of the first resistor string 111. After the description of the above embodiments, those skilled in the art should be able to infer the current values of their sub-current sources I51, I52, which will not be described here.

In addition, it is to be noted that the coupling relationship between the above elements includes a direct or indirect electrical connection as long as the desired electrical signal transfer function can be achieved, and the invention is not limited. The technical means in the above embodiments may be combined or used alone, and the components may be added, removed, adjusted or replaced according to their functions and design requirements, and the invention is not limited. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and will not be described herein.

In summary, the present invention adds a current source that can generate a compensation current to the resistor string, and prevents the second-stage resistor string (ie, the second resistor string) from affecting the voltage division of the first-stage resistor string. At the same time, with the technical means of the present invention, no buffer or isolation circuit is needed between the two resistor strings to separate the two resistor strings.

Although the preferred embodiments of the present invention have been disclosed as above, the present invention is not limited to the above-described embodiments, and any one of ordinary skill in the art can make some modifications without departing from the scope of the present invention. The scope of protection of the present invention should be determined by the scope of the appended claims.

100. . . Digital analog converter

111. . . First resistor string

120~140. . . Channel circuit

121. . . Second resistor string

122. . . First data selector

123. . . Second data selector

124. . . First current source

125. . . Second current source

126. . . buffer

127. . . Decoding unit

210. . . Universal current source

211, 212. . . Operational Amplifier

221. . . Reference resistor string

400. . . Digital analog converter

420~440. . . Channel circuit

510. . . Current source circuit

511. . . Controller

512. . . Current mode digital analog converter

520~540. . . Channel circuit

I51, I52. . . Sub current source

R1. . . First resistance

R2. . . Second resistance

PIN1. . . First output

PIN2. . . Second output

VRH, VRL. . . Reference voltage

OUT1. . . The output voltage

I _COMP . . . Compensation current

I _REF . . . Reference current

VH, VL. . . Reference voltage

P1~P3, P21, P22. . . PMOS transistor

N1~N3, N21, N22. . . NMOS transistor

VB1, VB2, VB31, VB32, VB33, VB34. . . bias

ND1~ND65. . . Partial pressure point

D21~D23, DX21~DX23. . . decoder

S24, SX24. . . Switching unit

SW1~SW4. . . switch

B2, b1, b0. . . Bit

GND. . . Ground terminal

I. . . Current

M1~M20. . . Transistor

In+, in-. . . End point

INT. . . input signal

N51, N52. . . Partial pressure point

1 is a circuit diagram of a digital analog converter according to a first embodiment of the present invention.

2A is a schematic diagram of a current source circuit according to a first embodiment of the present invention.

2B is a circuit diagram of a first data selector of the first embodiment of the present invention.

2C is a schematic diagram showing the internal circuit of the decoder and the switching unit according to the first embodiment of the present invention.

3 is a circuit diagram of a tandem configuration class AB amplifier according to a first embodiment of the present invention.

4 is a circuit diagram of a digital analog converter according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a digital analog converter according to a third embodiment of the present invention.

100. . . Digital analog converter

111. . . First resistor string

120~140. . . Channel circuit

121. . . Second resistor string

122. . . First data selector

123. . . Second data selector

124. . . First current source

125. . . Second current source

126. . . buffer

R1. . . First resistance

R2. . . Second resistance

PIN1. . . First output

PIN2. . . Second output

VRH, VRL. . . Reference voltage

OUT1. . . The output voltage

I _COMP . . . Compensation current

VH, VL. . . Reference voltage

Claims (20)

A digital analog converter having a first resistor string having a plurality of first resistors connected in series to generate a plurality of first voltage dividers, the digital analog converter comprising: at least one channel circuit comprising: The first data selector is coupled to the first resistor string for selecting at least one of the first partial voltages to generate a voltage interval; and a second resistor string having a plurality of second resistors connected in series, The second resistor string is coupled to the first data selector for dividing the voltage interval into a plurality of second voltage dividers; a second data selector coupled to the second resistor string for selecting And outputting one of the second partial voltages; and a current source circuit coupled to the second resistor string, generating a compensation current through the second resistor string according to the voltage interval to reduce flow from the first resistor string a shunt current of the second resistor string; wherein the first data selector generates the voltage interval according to a digital signal of an M bit, wherein the digital signal is divided into a most significant byte and a least significant bit, wherein The highest The effective byte is (M-1) bit, where M is a positive integer and is greater than or equal to 3. The first data selector includes: a decoding unit having three decoders suitable for (M-1) bits And respectively coupled to all voltage dividing points of the first resistor string, and selecting three adjacent partial voltages of the first partial voltages according to the most significant byte group to correspond to the digital signal; and a switching unit And coupled to the outputs of the decoders, selecting two of the three divided voltages according to the least significant bits to generate This voltage range. The digital analog circuit of claim 1, wherein the current source circuit comprises: a first current source coupled to the first end of the second resistor string for mapping a reference current to generate the Compensating current to the second resistor string; and a second current source coupled to the second end of the second resistor string for mapping the reference current to drain the compensation current from the second resistor string to a ground . The digital analog converter of claim 2, further comprising: a universal current source coupled to the first resistor string or the two reference voltages corresponding to the first resistor string to generate the reference current, Wherein the reference current is related to a resistance value of the second resistor string. The digital analog converter of claim 3, wherein the universal current source comprises: a first PMOS transistor having a source coupled to a voltage source; a second PMOS transistor having a source coupling a gate connected to the first PMOS transistor, the gate of which is coupled to a bias voltage; a first NMOS transistor having a drain coupled to the drain of the second PMOS transistor and the first PMOS a gate of the crystal, the source of which is coupled to the first end of a reference resistor string; and a first operational amplifier having a non-inverting input coupled to the first resistor string and an inverting input coupled to the a source of the first NMOS transistor having an output coupled to the gate of the first NMOS transistor; a third PMOS transistor having a source coupled to the second end of the reference resistor string; a second operational amplifier having an inverting input coupled to the reference resistor string The second end has a non-inverting input coupled to the first resistor string, an output coupled to the gate of the third PMOS transistor, and a second NMOS transistor having a drain coupled to the second a drain of the three PMOS transistor, the gate of which is coupled to a bias voltage, and a third NMOS transistor, the drain of which is coupled to the source of the second NMOS transistor, and the source of which is coupled to the ground The gate is coupled to the drain of the second NMOS transistor; wherein the first current source is coupled to the gate of the first PMOS transistor and the gate of the second PMOS transistor to map the reference The second current source is coupled to the gate of the second NMOS transistor and the gate of the third NMOS transistor to map the reference current. The digital analog converter of claim 1, wherein the first data selector has a first output end and a second output end respectively coupled to the two ends of the second resistor string for providing Two of the selected first partial pressures are divided to both ends of the second resistance string. The digital analog converter of claim 1, wherein the first data selector is a 6-bit data selector, and the second data selector is a 4-bit data selector; the first resistor The string includes at least 64 first resistors in series, the second resistor string including at least 16 second resistors in series. The digital analog converter of claim 1, wherein the compensation current is determined by dividing a voltage difference corresponding to the voltage interval by a quotient of the resistance value of the second resistor string. The digital analog converter of claim 1, wherein the channel circuit further comprises a buffer coupled to the output of the second data selector, wherein the buffer is a cascade configuration class AB amplifier . A digital analog converter as described in claim 1 of the patent application, wherein The decoder includes a first decoder, a second decoder, and a third decoder, wherein the odd voltage points in the first resistor string are respectively coupled to the first decoder and the third decoder The even voltage dividing points in the first resistor string are respectively coupled to the second decoder. The digital analog converter of claim 9, wherein the switching unit comprises: a first switch coupled to the output end of the third decoder and a first output of the first data selector a second switch coupled to the output of the first decoder and a second output of the first data selector; a third switch coupled to the output of the second decoder and the first a first output of the data selector; and a fourth switch coupled to the output of the second decoder and the second output of the first data selector; wherein, the least significant bit When it is 1, the first switch is turned on and the fourth switch is turned on. When the least significant bit is 0, the second switch is turned on. A data selector, which is suitable for a digital analog converter, the digital analog converter has a first resistor string, the first resistor string has a plurality of first resistors connected in series to generate a plurality of first partial voltages, wherein the data The selector is coupled to the first resistor string for selecting at least one of the first divided voltages to generate a voltage interval, and the data selector generates the voltage interval according to a digital signal of an M-bit, wherein The digital signal is divided into a most significant byte and a least significant bit, wherein the most significant byte is a (M-1) bit, wherein M is a positive integer and greater than or equal to 3. The data selector comprises: a decoding unit having three decoders for (M-1) bits, respectively All the voltage dividing points of the first resistor string are coupled, and three adjacent voltage dividers of the first voltage dividers are selected according to the most significant byte group to correspond to the digital signal; and a switching unit is coupled Connected to the outputs of the decoders, two of the three divided voltages are selected according to the least significant bit to generate the voltage interval. The data selector of claim 11, wherein the decoders comprise a first decoder, a second decoder and a third decoder, wherein the odd voltage points in the first resistor string The first and second decoders are respectively coupled to the first decoder and the third decoder, and the even voltage points in the first resistor string are respectively coupled to the second decoder. The data selector of claim 12, wherein the switching unit comprises: a first switch coupled to an output end of the third decoder and a first output end of the first data selector; a second switch coupled to the output of the first decoder and a second output of the first data selector; a third switch coupled to the output of the second decoder and the first The first output of the data selector; and a fourth switch coupled to the output of the second decoder and the second output of the first data selector; wherein, when the least significant bit is At 1 o'clock, the first switch is turned on and the fourth switch is turned on. When the least significant bit is 0, the second switch is turned on. A digital analog converter includes: a first resistor string having a plurality of first resistors connected in series, the first resistor string having a plurality of voltage dividing points to generate a plurality of first voltage dividers; a current source circuit having a plurality of sub-current sources coupled to each of the voltage dividing points of the first resistor string; and at least one channel circuit comprising: a first data selector coupled to the first resistor string The second resistor string has a plurality of second resistors connected in series, and the second resistor string is coupled to the first data selection. And the second data selector is coupled to the second resistor string for selecting and outputting one of the second partial voltages; wherein The first data selector generates the voltage interval according to an M-bit digital signal, wherein the digital signal is divided into a most significant byte and a least significant bit, wherein the most significant byte is (M -1) a bit, wherein M is a positive integer and greater than or equal to 3, the first data selector comprises: a decoding unit having three decoders suitable for (M-1) bits, respectively coupled to the first a voltage divider point of a resistor string and selected according to the most significant byte group Selecting three adjacent partial voltages of the first partial voltages to correspond to the digital signal; and a switching unit coupled to the outputs of the decoders, and selecting the three partial voltages according to the least significant bits The two divided voltages generate the voltage interval; wherein the current source circuit adjusts the current value of each of the sub current sources according to the voltage interval to compensate for the shunt current flowing from the first resistor string to the second resistor string. The digital analog converter of claim 14, wherein the current source circuit comprises: a controller generates a control signal according to an input signal, the input signal corresponding to two voltage dividing points of the voltage dividing points, wherein the first data selector selects the first partial voltages according to the output signal Two voltage divisions to generate the voltage interval; and a current mode digital analog converter coupled to the controller and the sub current sources, and adjusting the sub current source corresponding to the selected voltage dividing point according to the control signal Compensating for a shunt current flowing from the first resistor string to the second resistor string. The digital analog converter of claim 14, wherein the decoder comprises a first decoder, a second decoder and a third decoder, wherein the odd voltage divider in the first resistor string The points are respectively coupled to the first decoder and the third decoder, and the even voltage dividing points in the first resistor string are respectively coupled to the second decoder. The digital analog converter of claim 16, wherein the switching unit comprises: a first switch coupled to the output end of the third decoder and a first output of the first data selector a second switch coupled to the output of the first decoder and a second output of the first data selector; a third switch coupled to the output of the second decoder and the first a first output of the data selector; and a fourth switch coupled to the output of the second decoder and the second output of the first data selector; wherein, the least significant bit When it is 1, the first switch is turned on and the fourth switch is turned on. When the least significant bit is 0, the second switch is turned on. A digital analog converter having a first resistor string, the first The resistor string has a plurality of first resistors connected in series to generate a plurality of first voltage dividers. The digital analog converter includes: at least one channel circuit, including: a first data selector coupled to the first resistor string, Selecting a partial voltage of the first partial voltages; a second resistor string having a plurality of second resistors connected in series to generate a plurality of second partial voltages, wherein the first data selector has an output end coupled At any point in the second resistor string, only the selected divided voltage is supplied to a voltage dividing point on the second resistor string; a second data selector is coupled to the second resistor string, Selecting and outputting one of the second partial voltages; and a current source circuit coupled to the second resistor string, generating a compensation current through the second resistor string according to the voltage interval to reduce the first resistor Generating a shunt current to the second resistor string; wherein the first data selector generates the voltage division according to a digital signal of an M bit, wherein the digital signal is divided into a most significant byte and a least significant bit Yuan, where the most significant bit The group is (M-1) bits, wherein M is a positive integer and is greater than or equal to 3. The first data selector comprises: a decoding unit having three decoders suitable for (M-1) bits, respectively coupled Connecting to all voltage dividing points of the first resistor string, and selecting three adjacent partial voltages of the first voltage dividers according to the most significant byte group to correspond to the digital signal; and a switching unit coupled At the outputs of the decoders, one of the three divided voltages is selected according to the least significant bit to generate the divided voltage. The digital analog converter of claim 18, wherein the decoders comprise a first decoder, a second decoder, and a third decoding. The odd-numbered voltage-divided points in the first resistor string are respectively coupled to the first decoder and the third decoder, and the even-numbered voltage-divided points in the first resistor string are respectively coupled to the second decoding Device. The digital analog converter of claim 19, wherein the switching unit comprises: a first switch coupled to the output end of the third decoder and a first output of the first data selector a second switch coupled to the output of the first decoder and a second output of the first data selector; a third switch coupled to the output of the second decoder and the first a first output of the data selector; and a fourth switch coupled to the output of the second decoder and the second output of the first data selector; wherein, the least significant bit When it is 1, the first switch is turned on and the fourth switch is turned on. When the least significant bit is 0, the second switch is turned on.