TWI435426B - Semiconductor package-on-package device - Google Patents

Description

Semiconductor three-dimensional package structure

The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure.

In today's semiconductor packaging technology, in order to meet the requirements of multifunctional and high-power power, a package structure product in which semiconductor packages are stacked on each other is derived, that is, stacked package on package (POP), or It is called a 3D package. POP is packaged and tested by two separate package components and then surface-bonded to form a high-density integrated device that does not occupy the surface area. It can reduce the integration of various integrated circuit processes and the defects of a single package. Rate risk, which in turn increases product yield. Therefore, POP packaging is an emerging, packaged technology and lowest cost system packaging solution, especially suitable for integrating complex and multiple logic components and memory.

1 is a schematic cross-sectional view of a conventional semiconductor three-dimensional package structure before and after combination, and FIG. 2 is a schematic cross-sectional view of the conventional semiconductor three-dimensional package structure after combination. The semiconductor three-dimensional package structure 100 includes a lower layer bottom package 110 and an upper layer upper package 120, both of which are soldered together via solder balls 123 using surface mount technology (SMT). The upper surface 111A of the first substrate 111 of the bottom package 110 is provided with a first wafer 112 and a plurality of transfer pads 114. The transfer pads 114 provide a bonding arrangement of the solder balls 123. A first encapsulant 115 is formed on the upper surface 111A of the first substrate 111 and covers the first wafer 112. The lower surface 111B of the first substrate 111 is formed with a plurality of external terminals 113 for bonding the external surface to a printed circuit board 10. The upper package 120 is bonded to the bottom package 110. The upper surface 121A of the second substrate 121 of the upper package 120 is provided with at least one second wafer 122. A second sealing body 125 is formed on the upper surface 121A of the second substrate 121 to cover the second wafer. 122. The solder balls 123 are formed on the lower surface 121B of the second substrate 121. The solder balls 123 are aligned and bonded to the underlying pads 114 during reflowing to stack and electrically connect the upper package 120 to the bottom package 110. The upper package 120 is bonded to the transfer pads 114 of the bottom package 110 via the solder balls 123 at a suitable reflow temperature. The bottom package 110 is surface-bonded to the printed circuit board 10 via the external terminals 113.

However, as shown in Fig. 2, in various heating processes such as thermal cycle test and actual calculation, stress phenomenon occurs in the package stack due to the difference in coefficient of thermal expansion (CTE) between different materials, which is particularly likely to cause The warpage phenomenon of the first substrate 111 causes the soldering or dummy soldering of the external terminals 113 (such as the empty soldering portion 113A of FIG. 2) or the solder joints of the solder balls 123 to be broken (eg, The solder joint break 123A) of FIG. 2 has poor bonding, and the reliability of the semiconductor three-dimensional package is lowered.

In view of the above, the main object of the present invention is to provide a semiconductor three-dimensional package structure, which can improve the bonding of the embedded solder balls and effectively reduce the substrate warpage of the bottom package, thereby solving the joint solder joint break of the conventional POP stack. There is a problem that the electrical connection between the upper and lower packages fails.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor three-dimensional package structure, comprising: a bottom package, an upper package and an anisotropic conductive adhesive layer. The bottom package includes a first substrate, at least one first chip disposed on the first substrate, a plurality of external terminals disposed under the first substrate, and a plurality of transfer pads, wherein the transfer pads are The periphery of the upper surface of the first substrate is disposed. The upper package is bonded to the bottom package, the upper package includes a second substrate, at least one second wafer disposed on the second substrate, and a plurality of solder balls, wherein the solder balls are disposed Around the lower surface of the second substrate. The anisotropic conductive adhesive layer is disposed between the bottom package and the upper package and has a central opening for bonding the periphery of the upper surface of the first substrate and the lower surface of the second substrate . Wherein, the anisotropic conductive adhesive layer has a plurality of conductive particles, wherein the solder balls are embedded in the anisotropic conductive adhesive layer and cover the conductive particles to be bonded to the transfer pads. .

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor three-dimensional package structure, the coated conductive particles may be substantially concentrated on the solder balls toward the lower half of the transfer pads.

In the foregoing semiconductor three-dimensional package structure, the solder balls may have an elongated arc shape after reflow.

In the foregoing semiconductor three-dimensional package structure, the thickness of the anisotropic conductive adhesive layer may be slightly larger than the height of the solder balls before reflow.

In the aforementioned semiconductor three-dimensional package construction, each solder ball system may include a pillar core covered with solder.

In the foregoing semiconductor three-dimensional package structure, the bottom package may include a first encapsulant formed on the first substrate to seal the first wafer, and the upper package includes a second encapsulant And formed on the second substrate to seal the second wafer.

In the foregoing semiconductor three-dimensional package structure, the first encapsulation system may be smaller than the central opening of the anisotropic conductive adhesive layer to partially cover the upper surface of the first substrate to expose the upper surface of the first substrate. And the second encapsulation system completely covers the upper surface of the second substrate.

In the foregoing semiconductor three-dimensional package structure, the first wafer system may be a controller wafer, and the second wafer system may be a memory wafer.

In the foregoing semiconductor three-dimensional package structure, the anisotropic conductive adhesive layer may have a single layer structure.

In the foregoing semiconductor three-dimensional package structure, the anisotropic conductive adhesive layer may have a multi-layer structure and have a lower layer structure and an upper layer structure, wherein the lower layer structure is adjacent to the first substrate and has more layers than the upper layer structure. Conductive particles.

It can be seen from the above technical solutions that the semiconductor three-dimensional package structure of the present invention has the following advantages and effects:

1. The intervening conductive adhesive layer can be disposed between the upper and lower packages and has a central opening to adhere the periphery of the upper surface of the lower substrate and the lower surface of the upper substrate as one of the technical means. The bonding of the embedded solder balls is improved and the substrate warpage of the bottom package is effectively reduced, and the problem that the conventional solder joint breaks and the electrical connection between the upper and lower packages fails is solved.

Second, the conductive particles coated with the solder ball and then bonded to the transfer pad as one of the technical means can strengthen the bonding strength between the solder ball and the transfer pad.

Third, the solder ball can be covered by the anisotropic conductive adhesive layer as one of the technical means, and the solder ball as the wafer contact can be sealed and protected from external pollution.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to a first embodiment of the present invention, a semiconductor three-dimensional package structure is illustrated in a cross-sectional view of FIG. 3 before combination and a cross-sectional view of FIG. 4 after combination. The semiconductor package structure 200 mainly includes a bottom package 210, an upper package 220, and an anisotropic conductive adhesive layer 230.

The bottom package 210 includes a first substrate 211, at least one first wafer 212 disposed on the first substrate 211, a plurality of terminals 213 disposed on the lower surface 211B of the first substrate 211, and a plurality of switches The pads 214 are disposed on the periphery of the upper surface 211A of the first substrate 211. The external terminals 213 may include solder balls, solder pastes, contact pads or contact pins. In this embodiment, the external terminals 213 include solder balls, and may be disposed on the plurality of first external pads 211C, such that the bottom package 210 is a ball grid array package structure. The external terminals 213 can be surface bonded to a printed circuit board 20.

The upper package 220 is bonded to the bottom package 210. The upper package 220 includes a second substrate 221, at least one second wafer 222 disposed on the second substrate 221, and a plurality of solder balls (solders). Ball 223, wherein the solder balls 223 are disposed on the periphery of the lower surface 221B of the second substrate 221. The solder balls 223 may be tin-lead alloy or lead-free solder balls, for example, a lead-free solder of tin 96.5%-silver 3%-copper 0.5%. When the solder balls 223 reach a reflow temperature of about 217 degrees Celsius or higher, and the highest reflow temperature is about 245 degrees Celsius, the wettability of the solder can be generated. The solder balls 223 can be formed by ball implantation, or solder paste can be first formed on the plurality of second external pads 221C of the lower surface 221B by printing, plating or etching, and then soldered back. In a spherical shape. After the anisotropic conductive adhesive layer 230 is formed, the solder balls 223 may be melt-bonded to the transfer pads 214 of the first substrate 211 by electrical reflowing to form an electrical connection. Mechanical bonding (as shown in Figure 4). Therefore, the upper package 220 passes through the anisotropic conductive adhesive layer 230 and is surface-bonded to the bottom package 210.

Specifically, the bottom package 210 can include a first encapsulant 215, the first encapsulant 215 can be formed on the first substrate 211 to seal the first wafer 212, and the upper package 220 The second encapsulant 225 can be formed on the second substrate 221 to seal the second wafer 222.

In the detail, the substrates 211 and 221 may be a multi-layer printed wiring board such as FR-4, FR-5 or BT resin, or a poly-layer printed wiring board. A flexible circuit board made of guanamine. The wafers 212 and 222 can be adhered to the upper surfaces 211A and 221A of the substrates 211 and 221 by using a double-sided tape, a liquid epoxy adhesive or a B-stage (semi-cured) colloid. A plurality of first bonding pads 216 may be connected to the plurality of first pads 212A of the first wafer 212 and the plurality of first fingers 211D of the first substrate 211. Then, the first bonding wires 216 and the first wafer 212 are sealed by the first sealing body 215 to prevent moisture from intruding to complete the bottom package 210. Similarly, the plurality of second pads 222A of the second wafer 222 and the plurality of second fingers 221D of the second substrate 221 may be connected by a plurality of second bonding wires 226, and then sealed by the second sealing body 225. The second bonding wires 226 and the second wafer 222 complete the upper package 220. In a more detailed manner, the first pads 212A and the second pads 222A may be arranged in a single (multiple) row around the active surface of the first wafer 212 and the second wafer 222 as a connection body. The first pads 212A and the second pads 222A are generally aluminum or copper pads. Further, the first chip 212 can be a controller chip, and the second chip 222 can be a memory chip, which are respectively formed in different packages to achieve integration of the system package.

In this embodiment, the second chip 222 included in the upper package 220 may be plural, and the plurality of second fingers 221D of the second substrate 221 are disposed on the periphery of the second substrate 221, and may not be provided. The pad is transferred so that the periphery of the second substrate 221 has a larger space for more second fingers 221D to be connected to supply more of the second wafer 222. Alternatively, an adapter pad may be disposed around the upper surface 221A of the upper package 220 for stacking more upper package. The bottom package 210 and the upper package 220 may be identical packages in surface joint size to perform stereoscopic stacking using the same surface bonding apparatus.

As shown in FIGS. 3 and 4 , the anisotropic conductive adhesive layer 230 is disposed between the bottom package 210 and the upper package 220 and has a central opening 231 for bonding the first substrate 211 . The periphery of the upper surface 211A and the periphery of the lower surface 221B of the second substrate 221 increase the bonding strength between the first substrate 211 and the second substrate 221 and strengthen the sealing protection of the solder balls 223. Therefore, in the various heating processes such as the thermal cycle test, the bonding of the embedded solder balls can be improved and the substrate warpage of the bottom package can be effectively reduced, and the breakage of the solder joints can be reduced to cause the electrical connection failure between the upper and lower packages. problem. Compared with the conventional package in which the anisotropic conductive adhesive layer is not used, the solder balls are separated by gaps and the height of the upper package cannot be filled into the colloid, so that the substrate of the lower package is easily deformed, and the solder balls at specific positions are formed. In particular, the solder balls at the corners are completely exposed to thermal stress, and the repeated thermal cycling may cause oxidation, structural damage or metal fatigue of the specific solder balls, resulting in breakage of the solder balls.

Specifically, the anisotropic conductive adhesive layer 230 can be an anisotropic conductive paste (ACP) or an anisotropic conductive film (ACF). The anisotropic conductive adhesive layer 230 is formed by mixing a plurality of conductive particles 232 in an appropriate ratio in the resin. Typically, the conductive particles 232 have an equal particle size and a suitably uniform dispersion density to avoid direct electrical conductivity of the anisotropic conductive adhesive layer 230. The particle size of the conductive particles 232 is much smaller than the spherical diameter of the solder balls 223, at least one-fifth or less, which is favorable for being covered by the solder balls. In addition, the heat-resistant melting points of the conductive particles 232 should be greater than the reflow temperature of the solder balls 223, and the conductive particles 232 can be, for example, silver powder or high-temperature particles coated with gold on the surface. Preferably, the thickness of the anisotropic conductive adhesive layer 230 may be slightly larger than the height of the solder balls 223 before reflow, so as to have a sufficient height to adhere to the periphery of the upper surface 211A of the first substrate 211 and The periphery of the lower surface 221B of the second substrate 221.

When the bottom package 210 and the upper package 220 are stacked and reflowed, the anisotropic conductive adhesive layer 230 is embedded in the solder balls 223 to seal and protect the solder balls 223 as wafer contacts. To avoid external pollution. Moreover, during the reflow process, the conductive particles 232 can help the bonding of the solder balls 223. When the conductive particles 232 of the solder balls 223 are partially enlarged, the volume of the conductive particles 232 becomes larger, and then the pads are bonded to the pads. 214, the bonding between the solder balls 223 and the transfer pads 214 can be increased to electrically connect the bottom package 210 and the upper package 220. Preferably, the solder balls 223 are made to have an elongated arc shape after reflowing, with the help of the coated conductive particles 232, to avoid causing the adjacent solder balls 223 to bridge and short circuit.

The present invention is particularly applicable to a multi-package stacking structure having different sizes of encapsulants. The first encapsulant 215 can be smaller than the central opening 231 of the anisotropic conductive adhesive layer 230 to partially cover the upper surface 211A of the first substrate 211. To expose the periphery of the upper surface 211A of the first substrate 211, and the second encapsulant 225 completely covers the upper surface 221A of the second substrate 221. In other words, the anisotropic conductive adhesive layer 230 is partially formed on the upper surface 211A of the first substrate 211 and formed with the central opening 231. If viewed from a top view, a "back" word can be formed. The position is for setting the first wafer 212 and the first encapsulant 215. By using the interposing of the anisotropic conductive adhesive layer 230 and the conductive particles 232 of the solder ball 223, the substrate warpage of the bottom package 210 of the smaller encapsulant can be suppressed and the upper and lower packages are not affected. Electrical connection.

Referring to the partial enlarged views of FIGS. 4 and 5, in the embodiment, the anisotropic conductive adhesive layer 230 may have a single layer structure. The conductive particles 232 are coated by the solder balls 223, so that the proportion of the conductive particles in the colloidal body of the anisotropic conductive adhesive layer 230 is reduced, and the conductive probability of the conductive particles between the conductive particles 232 being improperly reduced can be reduced. .

Therefore, when a thermal cycle test or the like is performed to heat the substrate, the adhesion of the anisotropic conductive adhesive layer 230 to the upper and lower substrates can make the difference in warpage between the two substrates 211 and 221 substantially similar. The bonding of the embedded solder balls is improved and the substrate warpage of the bottom package is effectively reduced, and the problem that the solder joints are broken and the electrical connection between the upper and lower packages fails is caused. Preferably, the anisotropic conductive adhesive layer 230 can have a higher Young's modulus, that is, less than a strain amount of the first substrate 211 and the second substrate 221 under a fixed stress after curing. The effect of the intermediate structure support can be exerted.

As shown in a partially enlarged view of FIG. 6, in a variant embodiment, each solder ball 223 can comprise a pillar core 224 that is covered by solder. In detail, the pillar cores 224 may be non-reflow bumps, such as gold bumps, copper bumps, aluminum bumps or polymer conductive bumps, and the pillar cores 224 The shape may be a square shape, a cylindrical shape, a thin column shape, a cone shape, a hemisphere shape or a spherical shape. Preferably, the pillar cores 224 can be columnar conductors, such as copper pillars, which have the characteristics of high temperature resistance and non-deformation, so that the pillar cores 224 can maintain a good interval maintaining effect. Excessive collapse of the solder balls 223 may occur during the reflow process and the coated conductive particles may be limited to the lower half of the solder balls 223.

Further, as shown in FIG. 3, in order to further prevent the warpage of the first substrate 211 from causing the solder joints of the external terminals 213 to be broken or poorly bonded, a difference may be formed on the upper surface of the printed circuit board 20. The square conductive adhesive layer 30. The material of the anisotropic conductive layer 30 can be the same as the anisotropic conductive adhesive layer 230 described above. That is, the first structural reinforcing frame is fixed to the first substrate 211. The anisotropic conductive adhesive layer 30 also has a plurality of conductive particles 31. The anisotropic conductive adhesive layer 30 can have a central opening 32 and only cover the portion where the external terminals 213 are disposed. The portions of the external terminals 213 can omit the use of the anisotropic conductive adhesive layer 30 to save material usage.

In a second embodiment of the present invention, another semiconductor three-dimensional package structure is disclosed, and a schematic cross-sectional view prior to joining in FIG. 7 and a cross-sectional view after joining in FIG. 8 are illustrated. The semiconductor package structure 300 mainly includes a bottom package 210, an upper package 220, and an anisotropic conductive adhesive layer 330. The main components are generally the same as those of the first embodiment, and the components of the same drawing numbers will not be described in detail.

The anisotropic conductive adhesive layer 330 is disposed between the bottom package 210 and the upper package 220 and has a central opening 231 for bonding the periphery of the upper surface 211A of the first substrate 211 with the second The periphery of the lower surface 221B of the substrate 221. In this embodiment, the anisotropic conductive adhesive layer 330 can have a multi-layer structure and has a lower layer structure 331 and an upper layer structure 332, wherein the lower layer structure 331 is adjacent to the first substrate 211 and has more layers than the upper layer. Conductive particles 333 of structure 332. Moreover, the thickness of the lower layer structure 331 can be smaller than the thickness of the upper layer structure 332, so that the conductive particles 333 are concentrated under the anisotropic conductive adhesive layer 330 to increase the number of the solder balls 223. And reducing the probability of the side between the solder balls 223 in the glue layer.

In a specific embodiment, the upper structure 332 can be, for example, an insulating layer without conductive particles. The solder balls 223 can be coated with more conductive particles 333 and then bonded to the transfer pads 214 to enhance the bonding between the solder balls 223 and the transfer pads 214. Bonding, the bottom package 210 and the upper package 220 are electrically connected. Therefore, the thickness of the anisotropic conductive adhesive layer 330 can be selected to be slightly larger than the ball diameter before the solder balls 223 are reflowed, without affecting the electrical connection and ensuring the substrate bonding of the upper and lower packages.

Therefore, the present invention can be used as a technical means by interposing an anisotropic conductive adhesive layer between the upper and lower packages and having a central opening to adhere the periphery of the upper surface of the lower substrate and the lower surface of the upper substrate. During the heating process, the bonding of the embedded solder balls can be improved and the substrate warpage of the bottom package can be effectively reduced, and the problem that the solder joints are broken and the electrical connection between the upper and lower packages fails can be reduced.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

10. . . A printed circuit board

20. . . A printed circuit board

30. . . Anisotropic conductive adhesive layer

31. . . Conductive particle

32. . . Central opening

100. . . Semiconductor three-dimensional package structure

110. . . Bottom package

111. . . First substrate

111A. . . Upper surface

111B. . . lower surface

112. . . First wafer

113. . . External terminal

113A. . . Empty joint of external terminal

114. . . Transfer pad

115. . . First gel

120. . . Upper package

121. . . Second substrate

121A. . . Upper surface

121B. . . lower surface

122. . . Second chip

123. . . Solder ball

123A. . . Solder ball joint break

125. . . Second seal

200. . . Semiconductor three-dimensional package structure

210. . . Bottom package

211. . . First substrate

211A. . . Upper surface

211B. . . lower surface

211C. . . First outer pad

211D. . . First finger

212. . . First wafer

212A. . . First pad 212A

213. . . External terminal

214. . . Transfer pad

215. . . First gel

216. . . First wire bond

220. . . Upper package

221. . . Second substrate

221A. . . Upper surface

221B. . . lower surface

221C. . . Second outer pad

221D. . . Second finger

222. . . Second chip

222A. . . Second pad

223. . . Solder ball

224. . . Column core

225. . . Second seal

226. . . Second wire

230. . . Anisotropic conductive adhesive layer

231. . . Central opening

232. . . Conductive particle

300. . . Semiconductor three-dimensional package structure

330. . . Anisotropic conductive adhesive layer

331. . . Understructure

332. . . Superstructure

333. . . Conductive particle

Figure 1: Schematic cross-sectional view of a conventional semiconductor three-dimensional package construction prior to assembly.

Fig. 2 is a schematic cross-sectional view showing the bending of the substrate after the combination of the conventional semiconductor three-dimensional package structure.

Fig. 3 is a schematic cross-sectional view showing a semiconductor three-dimensional package structure according to a first embodiment of the present invention before being combined.

Fig. 4 is a schematic cross-sectional view showing the semiconductor three-dimensional package structure according to the first embodiment of the present invention after combination.

Fig. 5 is a partially enlarged cross-sectional view showing Fig. 4.

FIG. 6 is a partially enlarged cross-sectional view showing a semiconductor three-dimensional package structure according to a modified embodiment of the first embodiment of the present invention.

Figure 7 is a cross-sectional view showing another semiconductor three-dimensional package structure according to a second embodiment of the present invention before being combined.

Figure 8 is a cross-sectional view showing the semiconductor three-dimensional package structure according to the second embodiment of the present invention after combination.

20. . . A printed circuit board

30. . . Anisotropic conductive adhesive layer

31. . . Conductive particle

32. . . Central opening

200. . . Semiconductor three-dimensional package structure

210. . . Bottom package

211. . . First substrate

211A. . . Upper surface

211B. . . lower surface

211C. . . First outer pad

212. . . First wafer

212A. . . First pad

213. . . External terminal

214. . . Transfer pad

215. . . First gel

220. . . Upper package

221. . . Second substrate

221A. . . Upper surface

221B. . . lower surface

221C. . . Second outer pad

221D. . . Second finger

222. . . Second chip

222A. . . Second pad

223. . . Solder ball

225. . . Second seal

226. . . Second wire

230. . . Anisotropic conductive adhesive layer

231. . . Central opening

232. . . Conductive particle

Claims (10)

A semiconductor three-dimensional package structure comprising: a bottom package comprising a first substrate, at least one first chip disposed on the first substrate, a plurality of external terminals disposed under the first substrate, and a plurality of switches a pad, wherein the pad is disposed on a periphery of an upper surface of the first substrate; an upper package is bonded to the bottom package, the upper package includes a second substrate, and at least one is disposed on the pad a second wafer of the second substrate and a plurality of solder balls, wherein the solder balls are disposed on a periphery of a lower surface of the second substrate; and an anisotropic conductive adhesive layer is disposed on the bottom package A central opening is formed between the upper package to adhere the periphery of the upper surface of the first substrate and the lower surface of the second substrate; wherein the anisotropic conductive adhesive layer has a plurality of conductive particles The solder balls are embedded in the anisotropic conductive adhesive layer and cover part of the conductive particles, and then bonded to the transfer pads, wherein the coated conductive particles are substantially concentrated on the conductive particles. Some solder balls The transfer some of the lower half of the pad. The semiconductor three-dimensional package structure according to claim 1, wherein the solder balls are elongated in shape after reflow. The semiconductor three-dimensional package structure according to claim 1, wherein the thickness of the anisotropic conductive adhesive layer is greater than the height of the solder balls before reflow. The semiconductor three-dimensional package structure of claim 1, wherein each solder ball comprises a pillar core covered with solder. The semiconductor three-dimensional package structure of claim 1, wherein the bottom package further comprises a first encapsulant formed on the first substrate to seal the first wafer, and the upper package The system further includes a second encapsulant formed on the second substrate to seal the second wafer. The semiconductor three-dimensional package structure of claim 5, wherein the first encapsulation system is smaller than the central opening of the anisotropic conductive adhesive layer to partially cover the upper surface of the first substrate to expose the first The periphery of the upper surface of the substrate, and the second encapsulation system completely covers the upper surface of the second substrate. The semiconductor three-dimensional package structure according to claim 6, wherein the first wafer is a controller wafer and the second wafer is a memory wafer. The semiconductor three-dimensional package structure according to any one of claims 1 to 7, wherein the anisotropic conductive adhesive layer has a multi-layer structure and has a lower layer structure and an upper layer structure, wherein the lower layer structure is adjacent to the first A substrate has more conductive particles than the upper layer structure. A semiconductor three-dimensional package structure comprising: a bottom package comprising a first substrate, at least one first chip disposed on the first substrate, a plurality of external terminals disposed under the first substrate, and a plurality of switches Pad, wherein the transfer pads The upper package is disposed on the bottom surface of the first substrate; the upper package is bonded to the bottom package, the upper package includes a second substrate, and at least one second chip disposed on the second substrate And a plurality of solder balls, wherein the solder balls are disposed on a periphery of a lower surface of the second substrate; and an anisotropic conductive adhesive layer is disposed between the bottom package and the upper package and has a a central opening for bonding the periphery of the upper surface of the first substrate and the periphery of the lower surface of the second substrate; wherein the anisotropic conductive adhesive layer has a plurality of conductive particles, wherein the solder balls are embedded The conductive particles are trapped in the anisotropic conductive adhesive layer and are partially bonded to the transfer pads. The bottom package further includes a first encapsulant formed on the first substrate. Upper to seal the first wafer, and the upper package further includes a second encapsulant formed on the second substrate to seal the second wafer, wherein the first encapsulation system is smaller than the dissimilar Central of the conductive adhesive layer Partially covering over the mouth and the first surface of the substrate to expose the peripheral surface on the first substrate, the second sealant system and complete coverage over the second surface of the substrate. The semiconductor three-dimensional package structure according to claim 9, wherein the first wafer is a controller wafer and the second wafer is a memory wafer.