TWI432116B - Method for fabricating embedded wiring structure of wiring board - Google Patents

Description

Method for manufacturing buried circuit structure of circuit board

The present invention relates to a manufacturing process of a wiring board, and more particularly to a method of manufacturing a wiring structure of a wiring board.

In the manufacturing technology of the existing circuit board, the wiring structure of the wiring board is usually formed by lithograph and wet etching. In detail, in the current manufacturing process of the line structure, electroless plating is usually performed first to form a seed layer covering the dielectric layer on the dielectric layer.

Next, using a lithography, a patterned photoresist layer is formed on the seed layer that partially exposes the seed layer. Thereafter, electroplating is performed to form a metal layer on the seed layer. Then, wet etching is performed, that is, an etching liquid is used to remove a part of the seed layer, thereby forming a wiring structure of the wiring board.

The invention provides a method for manufacturing a buried circuit structure of a circuit board for manufacturing a buried circuit structure of a circuit board.

The invention provides a method for manufacturing a buried circuit structure of a circuit board. First, a composite substrate comprising an activated insulating layer is provided, wherein the activated insulating layer comprises an insulating layer and a plurality of catalyst particles distributed in the insulating layer and has an outer plane. Then, a plurality of routing trenches, at least one pad trench and at least one blind via are formed on the outer plane, wherein some of the catalyst particles are activated and exposed in the trenches, the pad trenches and the blind vias, at least one trench The hole is communicated with the pad slot, and the blind hole is located below the pad slot and communicates with the pad slot. At least one connecting groove communicating with the routing grooves and the pad grooves is formed on the outer surface, and some of the catalyst particles are activated and exposed in the connecting grooves. Thereafter, a chemical deposition method is used to form a sub-layer in the trenches, the pad trenches, the connection trenches, and the blind vias, wherein the activated catalyst particles participate in the chemical reaction of the chemical deposition method. After the seed layer is formed, a metal layer is formed on the seed layer by electroplating to form a plurality of traces in the trenches, a pad is formed in the pad trench, and a conductive pillar is formed in the blind via hole. And forming a plating line in the connecting groove. After forming these traces and pads, the plating lines are removed.

In an embodiment of the invention, the chemical deposition method is electroless plating or chemical vapor deposition (CVD).

In an embodiment of the invention, the above method of removing the plating line includes grinding, rubbing, or etching.

In an embodiment of the invention, the method for forming the trenches, the pad trenches, the blind vias and the connection trenches, and activating the catalyst particles comprises laser ablation or plasma on the activated insulating layer. Plasma etching.

In an embodiment of the invention, the depth of the connecting groove relative to the outer plane is smaller than the depth of the wire grooves relative to the outer plane and the depth of the pad groove relative to the outer plane.

In an embodiment of the invention, the conductive pillar is a solid cylinder.

In an embodiment of the invention, the material of the catalyst particles comprises at least one metal coordination compound.

In an embodiment of the invention, the material of the metal complex compound is selected from the group consisting of zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, ruthenium, indium, iron, manganese, chromium, molybdenum, and tungsten. a group of vanadium, niobium and titanium.

In an embodiment of the invention, the catalyst particles are a plurality of metal particles.

In an embodiment of the invention, the material of the insulating layer is selected from the group consisting of an epoxy resin, a modified epoxy resin, a polyester, an acrylate, a fluoropolymer, a polyphenylene oxide, and a polysiloxane. Amine, phenolic resin, polyfluorene, alizarin polymer, bis-maleic acid-triazabenzene resin, cyanic acid polyester, polyethylene, polycarbonate resin, propylene-butadiene-styrene copolymer , polyethylene terephthalate resin, polybutylene terephthalate resin, liquid crystal polymer, polyamide 6, nylon, copolyacetal, polyphenylene sulfide and cyclic olefin copolymer polymer Group.

In an embodiment of the invention, the composite substrate further includes an inner wiring substrate and a wiring layer. The circuit layer is disposed on the inner layer circuit substrate. The activated insulating layer is disposed on the inner layer wiring substrate and covers the wiring layer. The blind holes partially expose the circuit layer.

In an embodiment of the invention, the ratio of the line width of the plating line to the line width of each of the traces is between 1 and 5.

In an embodiment of the invention, the composite substrate is a mother circuit substrate and includes a metal frame line on a plane, and the metal layer is connected to the metal frame line.

In an embodiment of the invention, the method further includes forming a plurality of outer connecting grooves. These external connecting grooves extend from the metal frame line and communicate with the wire trench, the pad groove and the connecting groove. After forming the metal layer, the metal layer fills the outer connecting trenches to form a plurality of outer plating lines in the outer connecting trenches.

In an embodiment of the invention, the ratio of the line width of each of the outer plating lines to the line width of each of the traces is between 5 and 50.

In an embodiment of the invention, the method of forming a metal layer includes energizing a metal frame.

In an embodiment of the invention, the ratio of the line width of the metal frame line to the line width of each of the lines is between 10 and 100.

Based on the above, since the connection trench communicates with the trenches, the pad trenches and the blind vias, after the seed layer is formed by using the exposed and activated catalyst particles, the seed layer located in the connection trench can be positioned on the trace. The seed layer in the trench is connected to the seed layer located in the pad groove and the blind hole. Thus, by electroplating, a trace can be formed in the trench, a pad can be formed in the pad trench, a conductive pillar can be formed in the blind via, and a plating line can be formed in the trench. After the plating line is removed, the buried wiring structure of the board is completed.

The above described features and advantages of the present invention will be more apparent from the following description.

1A to 1J are schematic flow charts showing a method of manufacturing a buried wiring structure of a wiring board according to an embodiment of the present invention. 1A and FIG. 1B, FIG. 1A is a schematic plan view, and FIG. 1B is a cross-sectional view taken along line I-I of FIG. 1A. In the method of fabricating the buried wiring structure of the present embodiment, first, a composite substrate 110 is provided. The composite substrate 110 includes an activating insulating layer 112 having an outer plane S1 and including a plurality of catalyst particles 112a and an insulating layer 112b, wherein the catalyst particles 112a are distributed in the insulating layer 112b.

These catalyst particles 112a may be a plurality of nanoparticles having a metal component, which contains, for example, metal atoms or metal ions. In detail, these catalyst particles 112a may be a plurality of metal particles such as palladium metal particles. In addition, the material of these catalyst particles 112a may also include more than one metal coordination compound, such as a metal oxide, a metal nitride, a metal complex or a metal chelate (metal). Chelation).

The material of the metal complex compound is, for example, selected from the group consisting of zinc, copper, silver, gold, nickel, aluminum, palladium, platinum, cobalt, rhodium, ruthenium, indium, iron, manganese, chromium, molybdenum, tungsten, vanadium, niobium, titanium. Or any combination of these metals, so the catalyst particles 112a may be aluminum nitride, copper oxide, titanium nitride or cobalt molybdenum bimetallic nitride (Co ₂ Mo ₃ N _x ) particles.

In addition, the material of the catalyst particles 112a may include a plurality of metal coordination compounds, that is, the material of the catalyst particles 112a may be selected from metal oxides, metal nitrides, metal complexes, metal chelates, or any combination of these compounds. . For example, the single catalyst particles 112a may include metal oxides and metal complexes, or include metal nitrides, metal complexes, and metal chelates.

The material of the insulating layer 112b is, for example, selected from the group consisting of epoxy resins, modified epoxy resins, polyesters, acrylates, fluoropolymers, polyphenylene oxides, polyimines, phenolic resins, polyfluorenes. , alizarin polymer, bis-maleic acid-triazabenzene resin, cyanic acid polyester, polyethylene, polycarbonate resin, propylene-butadiene-styrene copolymer, polyethylene terephthalate Diester resin, polybutylene terephthalate resin, liquid crystal polymer, polyamine 6, nylon, copolyacetal, polyphenylene sulfide, cyclic olefin copolymer polymer or any combination of these compounds.

In the embodiment, the composite substrate 110 may be a circuit substrate. In detail, the composite substrate 110 may further include a wiring layer 114 and an inner wiring substrate 116. The wiring layer 114 is disposed on the inner layer wiring substrate 116 and electrically connected to the inner wiring substrate 116, and the active insulating layer 112 is disposed on the inner wiring substrate 116 and covers the wiring layer 114. The circuit layer 114 includes a plurality of pads 114a and a plurality of traces 114b, and the pads 114a are electrically connected to the traces 114b.

The inner wiring substrate 116 may include at least one inner wiring layer and at least one electrically conductive connection structure. The internal circuit layer and the conductive connection structure can be the same as the internal circuit structure of the existing circuit board, and thus are not shown in the drawings. The inner circuit layer can electrically connect the circuit layer 114 via the conductive connection structure, and the conductive connection structure can be a conductive blind via structure or a conductive through hole structure.

When the composite substrate 110 includes the inner layer circuit substrate 116, since the composite substrate 110 includes two layers of wiring: the wiring layer 114 and the internal wiring layer, the manufacturing method of the buried wiring structure of the present embodiment can be applied to manufacturing a multilayer wiring board ( Multilayer wiring board). When the composite substrate 110 does not include the inner layer wiring substrate 116, the manufacturing method of the buried wiring structure of the present embodiment can be applied to manufacture a double-side wiring board.

Please refer to FIG. 1C and FIG. 1D , wherein FIG. 1C is a top view, and FIG. 1D is a cross-sectional view taken along line II-II of FIG. 1C . Then, a plurality of trenches T1, a plurality of pad trenches P1, and a plurality of blind vias H1 are formed on the outer plane S1, and some of the catalyst particles 112a are activated and exposed in the trenches T1 and the pad trenches P1. These blind holes are inside H1. In FIG. 1C and FIG. 1D, at least one of the routing trenches T1 is in communication with a pad slot P1, and the blind via hole H1 is located below the pad slot P1 and communicates with the pad slot P1. In addition, these blind holes H1 partially expose the pads 114a.

These trenches T1, the pad trenches P1, and the blind vias H1 are formed, and the method of activating the catalyst particles 112a may be laser ablation or plasma etching of the activating insulating layer 112. In detail, a portion of the activating insulating layer 112 may be removed by using a laser beam or a plasma to form the trench T1, the pad trench P1, and the blind via hole H1. During the laser ablation or plasma ablation of the activating insulating layer 112, the laser beam or plasma can interrupt the catalyst particles 112a exposed in the trench T1, the pad trench P1 and the blind via H1. The chemical bond promotes activation of the catalyst particles 112a.

In addition, in the embodiment shown in FIG. 1C and FIG. 1D, the number of the pad slot P1 and the blind hole H1 may be multiple, but the wiring layout of the terminal board is in other In the embodiment, the number of the pad slot P1 and the blind hole H1 may be only one. Therefore, the number of the pad slot P1 and the blind hole H1 shown in FIG. 1C and FIG. 1D is merely an example and does not limit the present invention.

Please refer to FIG. 1E and FIG. 1F , wherein FIG. 1E is a top view, and FIG. 1F is a cross-sectional view taken along line III-III of FIG. 1E . Next, a plurality of connection grooves C1 are formed on the outer plane S1, wherein the connection grooves C1 can communicate with the wire grooves T1 and the pad grooves P1. That is to say, any of the trenches T1 can communicate with all of the pad trenches P1 and all other trenches T1 via at least one connecting trench C1.

In the above, the method of forming the connection trenches C1 may be laser ablation or plasma etching of the activating insulating layer 112. That is, a portion of the activated insulating layer 112 is removed by using a laser beam or a plasma to form the connecting grooves C1, and the catalyst particles 112a located in the connecting grooves C1 are activated.

When performing laser ablation, the power of the laser beam for forming the connection groove C1 may be smaller than the power of the laser beam for forming the trench T1 and the pad groove P1, and the connection groove C1 is opposed to the active insulating layer. The depth D1 of the outer plane S1 of 112 may be smaller than the depth D2 of the trench T1 with respect to the outer plane S1 and the depth D3 of the pad trench P1 with respect to the outer plane S1, and the depth D1 may be less than 5 micrometers (μm).

Further, the laser light source for forming the connection groove C1 may be the same as the laser light source for forming the wiring groove T1 and the pad groove P1. That is, the wavelengths of the laser beam for forming the connection groove C1 and the laser beam for forming the wiring groove T1 and the pad groove P1 may be the same.

It should be noted that, in FIG. 1E and FIG. 1F, the number of the connection grooves C1 may be plural, but the wiring design of the terminal circuit board, the number of the connection grooves C1 may be only one, so FIG. 1E and FIG. 1F The number of connection grooves C1 is merely illustrative and does not limit the invention.

It should be noted that, in this embodiment, the connection groove C1 is formed after the formation of the trench T1, the pad groove P1, and the blind hole H1, but in other embodiments, the connection groove C1 may also be Before the formation of the trench T1, the pad trench P1, and the blind via H1, the connection trench C1, the trench T1, the pad trench P1, and the blind via hole H1 shown in FIG. 1C to FIG. 1F are formed. The order of formation is merely illustrative and not limiting of the invention.

1G and FIG. 1H, wherein FIG. 1G is a top view, and FIG. 1H is a cross-sectional view taken along line IV-IV of FIG. 1G. After forming the connection trench C1, the trench T1, the pad trench P1, and the blind via H1, a chemical deposition method is used in the trench T1, the pad trenches P1, the connection trenches C1, and the blind vias H1. Forming a sub-layer 120, wherein the activated catalyst particles 112a, that is, the catalyst particles 112a exposed in the trench T1, the pad groove P1, the connection groove C1 and the blind hole H1, participate in the chemical deposition method. Chemical reaction.

In detail, in the process of performing the above chemical deposition method, the activated catalyst particles 112a located in the trench T1, the pad trench P1, the blind via H1 and the connection trench C1 can directly form the seed layer 120. The reactants generate a chemical reaction to deposit a conductive material in the trenches T1, the pad trenches P1, the blind vias H1, and the trenches C1 to form the seed layer 120. Therefore, the seed layer 120 is basically formed only in the trench T1, the pad trench P1, the blind via hole H1, and the connection trench C1.

The above chemical deposition method may be electroless plating or chemical vapor deposition. For example, when electroless plating is performed to form the seed layer 120, the activating insulating layer 112 may be immersed in an electroless plating solution containing a plurality of metal ions. When the activating insulating layer 112 is in contact with the electroless plating solution, these metal ions may chemically react with the activating insulating layer 112, such as a redox reaction, thereby forming a trench T1, a pad slot P1, and a blind hole H1. A metal material is deposited in the connection trench C1 to form a seed layer 120.

When chemical vapor deposition is performed to form the seed layer 120, the activating insulating layer 112 is placed first in the chamber. Thereafter, a reaction gas is introduced into the reaction chamber. At this time, the activation catalyst particles 112a exposed in the trench T1, the pad groove P1, the blind hole H1, and the connection groove C1 are in contact with the reaction gas, and chemically react with the reaction gas, such as a redox reaction. Thus, a metal material deposited in the trench T1, the pad trench P1, the blind via H1, and the connection trench C1 is formed, thereby forming the seed layer 120.

After the seed layer 120 is formed, a metal layer 130 is formed on the seed layer 120 by electroplating. The metal layer 130 can fill the trenches T1, the pad trenches P1, the blind vias H1, and the connection trenches C1, and a plurality of traces 140 are formed in the trenches T1, respectively, and are formed in the pad trenches P1. A plurality of pads 150 are formed in the plurality of conductive pillars 160, and a plurality of plating lines 170 are formed.

The conductive post 160 connects the pad 150 to the pad 114a of the circuit layer 114 to electrically connect the circuit layer 114 to the pad 150 and the trace 140. One of the traces 140 connects one of the pads 150, and the plating lines 170 connect the traces 140 to the pads 150. In addition, the conductive pillars 160 may be solid pillars to facilitate formation of a stack-via structure based on the conductive pillars 160 during the subsequent manufacturing process of the wiring board.

Since any of the trenches T1 can communicate with all of the pad trenches P1 and all of the trenches T1 via at least one of the connection trenches C1, the seed layer 120 located in the trenches C1 can be positioned in the trenches The seed layer 120 in T1 is connected to the seed layer 120 located in the pad grooves P1 and the blind holes H1. In this way, during the electroplating process, the external current can be substantially transmitted through the seed layer 120 in all the trenches T1, all the connection trenches C1, all the pad trenches P1, and all the blind vias H1, and thus on the seed layer 120. A metal layer 130 is formed.

Further, in the above plating process, the metal layer 130 is formed only on the seed layer 120. That is, the metal layer 130 is formed substantially only in the trench T1, the pad trench P1, the blind via hole H1, and the connection trench C1, and is not formed on the outer plane S1. It can be seen that the present embodiment can reduce the consumption of the plating solution to reduce the manufacturing cost compared to the prior art.

It should be noted that, in this embodiment, the line width W1 of each of the traces 140 may be 50 +/- 5 micrometers (um), and the line width W2 of each of the plating lines 170 may be 100 +/- 10 Micron. Further, in other embodiments, the ratio of the line width W2 to the line width W1 may be between 1 and 5.

Please refer to FIG. 1I and FIG. 1J, wherein FIG. 1I is a top view, and FIG. 1J is a cross-sectional view taken along line V-V of FIG. After forming the traces 140 and the pads 150, the plating lines 170 are removed (see FIGS. 1G and 1H), wherein the method of removing the plating lines 170 can include grinding, brushing, or etching. When the plating line 170 is removed by etching, the connection groove C1 can be left and filled with a material such as a solder mask or a prepreg in a subsequent manufacturing process. To this end, a buried wiring structure including a plurality of wiring lines 140, a plurality of pads 150, and a plurality of conductive pillars 160 has been completed, and the wiring board 100 having the buried wiring structure has been substantially completed.

In particular, the manufacturing method of the buried wiring structure of the circuit board according to another embodiment of the present invention may employ a wiring mother-substrate. Referring to FIG. 2A, a composite substrate 310 is illustrated, and the composite substrate 310 may be a mother circuit substrate, such as a working panel (also referred to as a panel) or a substrate strip.

The composite substrate 310 shown in FIG. 2A is a work board, so the composite substrate 310 includes a plurality of circuit units 312. These line units 312 are substantially all circuit boards, and each line unit 312 can be identical to the composite substrate 110. Although the composite substrate 310 in FIG. 2A is a work sheet, the type of the composite substrate 310 illustrated in FIG. 2A is merely illustrative and not limiting.

In the flow of the manufacturing method of the buried circuit structure of the embodiment, the manufacturing steps disclosed in the above embodiments are also performed on the circuit unit 312, for example, the routing trench T1, the pad slot P1, the blind hole H1 and the connection are formed. The groove C1, the seed layer 120 and the like are formed, and these steps will not be repeatedly described below.

The composite substrate 310 has a flat surface 314 and includes a metal frame line 316 with the metal frame line 316 positioned on the plane 314. The metal frame wire 316 may be formed of a metal foil such as a copper foil or an aluminum foil. For example, the metal wire 316 may be formed by lithography and etching of a copper foil of a copper foil substrate (CCL).

During the electroplating process, the metal wire 316 is used to receive an external current from an external power source and to transfer an external current to the line cells 312 to form a metal layer 130 (see FIG. 1H). In particular, the electroplating apparatus can generally have a plurality of metal fixtures that are electrically connected to an external power source. When electroplating is performed, a metal fixture (not shown) clamps the composite substrate 310 and contacts the metal wire 316. As such, the external power source can input an external current to the metal frame line 316 so that an external current can be transferred to the line units 312, thereby forming the metal layer 130.

Please refer to FIG. 2A and FIG. 2B, wherein FIG. 2B is a partial enlarged view of FIG. 2A. In order to enable the metal wire 316 to transmit an external current to the line units 312, the present embodiment may form a plurality of external connection grooves C2. The external connection trenches C2 extend from the metal frame lines 316 and communicate with the trenches T1, the pad trenches P1 and the connection trenches C1 in the respective line units 312. The method of forming these external connection trenches C2 is the same as forming the trenches. T1, pad groove P1 and method of connecting groove C1.

Thereafter, in the process of performing electroplating to form the metal layer 130, since the external connection trenches C2 extend from the metal frame lines 316 and communicate with the trenches T1, the pad trenches P1 and the connection trenches C1 in the respective line units 312, Thus, the method of forming the metal layer 130 may be to electrify the metal frame line 316 for electroplating. In this manner, the external current can be sequentially transmitted to the trench T1, the pad trench P1, and the connection trench C1 via the metal frame line 316 and the external connection trenches C2, thereby forming the metal layer 130 connecting the metal frame lines 316.

Further, the composite substrate 310 may have the following layout specifications. In detail, in the present embodiment, the line width W3 of each of the outer plating lines 192 may be 500 +/- 50 microns, and the line width W4 of the metal frame lines 316 may be 15 +/- 1.5 centimeters (mm). In addition, in other embodiments, the ratio of the line width W3 to the line width W1 of each of the lines 140 may be between 5 and 50, and the ratio of the line width W4 to the line width W1 may be between 10 and 100. .

After the metal layer 130 is formed, the metal layer 130 fills the external connection trenches C2 to form a plurality of external plating lines 192 in the external connection trenches C2. These external plating lines 192 can then be removed. The method in which the external plating line 192 is removed may be the same as the method of removing the plating line 170. Further, in another embodiment, the method in which the outer plating line 192 is removed may be performed by cutting the work sheet into a plurality of substrate strips while removing the outer plating lines 192. After the plating line 170 and the external plating line 192 are removed, the line units 312 are substantially fabricated into a plurality of wiring boards 100 (see FIG. 1J).

In summary, the present invention utilizes these catalytic particles which are activated and exposed in the trenches, blind vias, connecting trenches and pad trenches, and are combined with the above-described chemical deposition method and electroplating to form the above-mentioned traces and pads. Conductive column. Compared with the prior art, the present invention can manufacture a buried wiring structure without forming a patterned photoresist layer, thereby omitting the step of performing lithography.

While the present invention has been described above in the foregoing embodiments, it is not intended to limit the invention, and the equivalents of the modifications and retouchings are still in the present invention without departing from the spirit and scope of the invention. Within the scope of patent protection.

100. . . circuit board

110, 310. . . Composite substrate

112. . . Activated insulation

112a. . . Catalyst particles

112b. . . Insulation

114. . . Circuit layer

114a, 150. . . Pad

114b, 140. . . Traces

116. . . Inner layer circuit substrate

120. . . Seed layer

130. . . Metal layer

160. . . Conductive column

170. . . Plating line

192. . . External plating line

312. . . Line unit

314. . . flat

316. . . Metal frame line

C1. . . Connection groove

C2. . . External connection groove

D1, D2, D3. . . depth

H1. . . Blind hole

P1. . . Pad slot

S1. . . Outer plane

T1. . . Trough

W1, W2, W3, W4. . . Line width

1A to 1J are schematic flow charts showing a method of manufacturing a buried wiring structure of a wiring board according to an embodiment of the present invention.

2A is a top plan view showing a composite substrate in a flow of a method of manufacturing a buried wiring structure of a circuit board according to another embodiment of the present invention.

Fig. 2B is a partially enlarged schematic view of Fig. 2A.

140. . . Traces

150. . . Pad

170. . . Plating line

C1. . . Connection groove

P1. . . Pad slot

T1. . . Trough

W1, W2. . . Line width

Claims (17)

A method of fabricating a buried wiring structure for a circuit board, comprising: providing a composite substrate including an activated insulating layer, wherein the activated insulating layer comprises an insulating layer and a plurality of catalyst particles distributed in the insulating layer, and Having an outer plane; forming a plurality of wire trenches, at least one pad groove and at least one blind hole on the outer plane, wherein some of the catalyst particles are activated and exposed in the wire trenches, the pad grooves and the blind In the hole, at least one of the routing trenches is in communication with the pad slot, and the blind hole is located below the pad slot and communicates with the pad slot; at least one of the routing trenches is formed on the outer plane a connection groove communicating with the pad slot, and some of the catalyst particles are activated and exposed in the connection groove; and a chemical deposition method is used in the wire trench, the pad groove, the connection groove and the blind hole Forming a sub-layer, wherein the activated catalyst particles participate in a chemical reaction of the chemical deposition method; after forming the seed layer, a metal layer is formed on the seed layer by electroplating to form the trenches Multiple traces are formed inside, respectively A groove formed pad, the conductive pillar is formed a blind hole, and forming a plating line in the connecting groove; and after forming the plurality of lines and the pad, removing the plating line. The method for manufacturing a buried wiring structure of a wiring board according to claim 1, wherein the chemical deposition method is electroless plating or chemical vapor deposition. The method of manufacturing a buried wiring structure of a wiring board according to the first aspect of the invention, wherein the method of removing the plating wire comprises grinding, brushing or etching. The manufacturing method of the buried circuit structure of the circuit board according to the first aspect of the invention, wherein the wire trench, the pad groove, the blind hole and the connecting groove are formed, and the catalyst particles are activated. The method includes laser ablation or plasma etching of the activated insulating layer. The manufacturing method of the buried circuit structure of the circuit board according to the first aspect of the invention, wherein the depth of the connecting groove relative to the outer plane is smaller than the depth of the wire trenches relative to the outer plane and the pad The depth of the slot relative to the outer plane. The method for manufacturing a buried wiring structure of a circuit board according to claim 1, wherein the conductive pillar is a solid cylinder. The method of manufacturing a buried wiring structure of a wiring board according to claim 1, wherein the material of the catalyst particles comprises at least one metal coordination compound. The manufacturing method of the buried wiring structure of the circuit board of claim 1, wherein the material of the metal complex compound is selected from the group consisting of zinc, copper, silver, gold, nickel, palladium, platinum, cobalt, rhodium, ruthenium. a group of indium, iron, manganese, chromium, molybdenum, tungsten, vanadium, niobium, and titanium. The method for manufacturing a buried wiring structure of a circuit board according to claim 1, wherein the catalyst particles are a plurality of metal particles. The method for manufacturing a buried circuit structure of a circuit board according to claim 1, wherein the material of the insulating layer is selected from the group consisting of epoxy resin, modified epoxy resin, polyester, acrylate, Fluorine polymer, polyphenylene oxide, polyimine, phenolic resin, polyfluorene, alizarin polymer, bis-maleic acid-triazabenzene resin, cyanic acid polyester, polyethylene, poly Carbonate resin, propylene-butadiene-styrene copolymer, polyethylene terephthalate resin, polybutylene terephthalate resin, liquid crystal polymer, polyamide 6, nylon, copolymerized polyoxymethylene A group consisting of polyphenylene sulfide and a cyclic olefin copolymer polymer. The manufacturing method of the buried circuit structure of the circuit board according to the first aspect of the invention, wherein the composite substrate further comprises: an inner layer circuit substrate; and a circuit layer disposed on the inner layer circuit substrate, wherein The activated insulating layer is disposed on the inner layer circuit substrate and covers the circuit layer, and the blind hole partially exposes the circuit layer. The method of manufacturing a buried wiring structure of a circuit board according to claim 1, wherein a ratio of a line width of the plating line to a line width of each of the traces is between 1 and 5. The method for manufacturing a buried circuit structure of a circuit board according to claim 1, wherein the composite substrate is a mother circuit substrate and includes a metal frame line on the plane, and the metal layer is connected. The metal frame line. The method for manufacturing a buried circuit structure of a circuit board according to claim 13, wherein before forming the active layer, forming a plurality of external connecting trenches, the external connecting trenches extending from the metal frame line And communicating with the trench, the pad trench, and the connecting trench. After forming the metal layer, the metal layer fills the external connecting trenches to form a plurality of external plating lines in the external connecting trenches. . The method of manufacturing a buried wiring structure of a circuit board according to claim 14, wherein a ratio of a line width of each of the external plating lines to a line width of each of the traces is between 5 and 50. The method of manufacturing a buried wiring structure of a wiring board according to claim 13, wherein the method of forming the metal layer comprises energizing the metal frame. The method for manufacturing a buried wiring structure of a circuit board according to claim 13, wherein a ratio of a line width of the metal frame line to a line width of each of the wires is between 10 and 100.