TWI431626B - Data storage device and method for combining block pairs of a flash memory - Google Patents

Description

Data storage device and method for integrating block of flash memory

The present invention relates to memory, and more particularly to flash memory.

Figure 1 is a timing diagram of the host transmitting a write command to a data storage device. It is assumed that the data storage device includes a flash memory for storing data. When a host wants to write data to a data storage device, the first write command (0x80) is first transmitted to the data storage device via the input/output data bus. Then, the host sequentially transmits the column address and the row address to the data storage device to indicate the address to which the data is to be stored. The host then transmits the data to be written to the flash memory to the data storage device and transmits a second write command (0x10) to the data storage device. When the second write command is transmitted, the data storage device pulls down the potential of a ready/busy wire to prevent the host from continuing to send subsequent commands or data. In general, the controller of the data storage device facilitates the writing of the data by the step-down period T _prog according to the write command. Depending on the specification data transfer between the host and the data storage device, the processing time T _prog this paragraph is not longer than 250ms. After the data has been written, the data storage device will pull up the potential of the standby/busy wire. The host then transmits a read status command to ask the data storage device if the data write was successful.

Flash memory typically includes a plurality of blocks, and each block includes a plurality of pages for storing data. Usually, a page can only be written once. To update the data of the page, the data stored in all pages of the entire block must be erased together to write the data to the page again. Therefore, when the data storage device is to execute the write command, if the data corresponding to the page corresponding to the write address specified by the host has been stored, the data storage device must write the newly received update data to a blank block, and then establish The correspondence between the blank block and the original block corresponding to the write address. This correspondence is called a block pair. The original block is called the mother block of the block pairing, and the block storing the updated data is called the block paired sub-block (child Block).

In general, since maintaining a block pairing requires an additional record of many pairing relationships, the data storage device must control the number of block pairs so that only a fixed number of block pairs are stored in the flash memory. In the general case, the data storage device can write the received data into the flash memory within the processing period T _prog of 250 ms. However, when a write command to perform host transfer requires a new block pairing, in order to keep the number of block pairs in the flash memory fixed, it is necessary to flash the memory before executing the write command transmitted by the host. The original data stored in the parent block included in the partial block pair is integrated into the single block in the updated data stored in the sub-block, so that the original block pair number is reduced first, and then the host transfer can be performed. New block pairing with the write command.

Moreover, since each block contains many pages to store data, it takes a lot of time to integrate the data of the parent block and the sub-blocks of the block pairing. Especially when the flash memory is a multi-level-cell (MLC) flash memory or a three-level-cell (TLC) flash memory, each area of the flash memory The amount of data stored in the block is huge, and the data of the parent block and the sub-block paired by the integrated block takes more time, and often cannot be completed in a short processing period of 250 ms, and the data storage device and the host cannot be reached. Specification of data transfer specifications. Therefore, there is a need for a method of writing data to flash memory to solve the above problems.

In view of the above, it is an object of the present invention to provide a method for integrating block pairing of flash memory to solve the problems of the prior art. First, a target block pair is selected for integration from a plurality of block pairs of the flash memory. Then, the data stored in the parent block of the target block pair is divided into a plurality of data sections. Then, one of the blank blocks of the flash memory is selected as an integrated block for storing the integrated data of the target block pair. Next, multiple write commands are received from a host. Then, in the plurality of processing periods corresponding to the write commands, the update data stored in the sub-blocks of the data segment and the target block are respectively integrated and written into the integrated block.

The invention provides a data storage device coupled to a host. In one embodiment, the data storage device includes a flash memory and a controller. The flash memory includes a data temporary storage block and a plurality of block pairs. The controller selects a target block pair from the block pair of the flash memory for integration, and divides the data stored in the parent block of the target block into a plurality of data segments, and selects the fast a blank block of the flash memory as an integrated block storing the integrated data of the target block pair, receiving a plurality of write commands from the host, and respectively performing a plurality of processing periods corresponding to the write commands The data sections are updated with the updated data stored in the sub-blocks of the target block and written into the integrated block.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

Figure 2 is a block diagram of a data storage device 204 in accordance with the present invention. The data storage device 204 is coupled to a host 202 and accesses data according to the instructions of the host 202. In one embodiment, the data storage device 204 includes a controller 212, a flash memory 214, and a random access memory 216. The flash memory 214 includes a plurality of blocks for storing data, and the blocks include a data temporary storage block 222. Flash memory 214 also includes multiple sets of block pairs 224. Each block pair includes a mother block and a child block, the parent block stores the original data of a logical block address, and the sub-block stores the logical block bit. Update information of the address. For example, the parent block 231 is paired with the corresponding sub-block 241 for a group of blocks, and the parent block 23k is paired with the corresponding sub-block 24k for another group of blocks. The random access memory 216 stores the address storage table 220. In one embodiment, the data storage device 204 is a memory card.

Since the correspondence between the original data of the parent block of the record block and the update data of each page of the sub-block needs to occupy a large amount of data storage space, in order to effectively use the data storage space of the random access memory 216, the controller 212 limits the number of block pairs in flash memory 214 to a threshold value of N. When the number of block pairs K in the flash memory 214 is about to exceed the threshold value N, the controller 212 selects a group of target block pairs from the plurality of sets of block pairs 224 of the flash memory 214, and then targets the target. The original data stored in the parent block of the block pair is integrated with the updated data stored in the sub-block and stored in an integrated block, and then the data of the parent block and the sub-block paired with the original target block are wiped. except. Thus, the number K of block pairs of the flash memory 214 can be maintained at a limit value N.

When a write command is executed, the controller 212 adds a group of block pairs to the flash memory 214, and when the number of block pairs N in the flash memory 214 has reached the limit value K, in order to avoid the area The number of block pairs K exceeds the threshold value N, and the controller 212 must first select a target block pair for integration to reduce the number of block pairs K to execute the write command and increase the number of block pairs to maintain the number of block pairs. K does not exceed the limit value N. However, it takes a long time to integrate the parent block and the sub-block of a target block into one integrated block. Usually, the integration time will exceed 250 ms of the processing time T _prog shown in FIG. 1 , for example, May be 1000ms. At this time, the controller 212 first stores the currently received write address into the address storage table 220 of the random access memory 216, and stores the currently received write data into the flash memory 214. The data is temporarily stored in block 222. Then, the controller 212 divides the data stored in the parent block of the target block into a plurality of data segments, and uses the data storage device 204 to receive a plurality of 250 ms processing times corresponding to the plurality of subsequent write commands from the host 202 respectively. One of the data sections is integrated with the updated data stored in the sub-blocks, wherein the integration time of each data section does not exceed 250 ms as specified by the specification. Thus, the controller 212 can integrate the parent block paired with the child block to maintain the number of block pairs, and can meet the specification requirements for executing the write command between the host 202 and the data storage device 204.

Figure 3 is a flow diagram of a method 300 of integrating block pairing in accordance with the present invention. First, the controller 212 selects a target block pair for integration from the plurality of block pairs 224 of the flash memory 214. It is assumed that the target blocks selected by the controller are paired into blocks 231 and 241. Next, the controller 212 divides the data stored in the parent block of the target block pair into a plurality of data segments. In one embodiment, the number of data segments must be greater than the quotient value obtained by integrating the processing time required to integrate a block by the processing time T _prog of a write command. For example, if the time required to integrate a block pairing is 700 ms, and the processing time T _prog with a write command is 250 ms, the number of data segments is 3 (≧700/250). Therefore, the controller 212 divides the data stored in the parent block pair 231 of the target block into three data segments.

Next, the controller 212 selects a blank block from the flash memory 214 as an integrated block for storing the integrated data of the target block pair (step 306). Controller 212 then receives a write command, writes an address, and writes data from host 202 (step 308). Next, the controller 212 determines whether to perform the write command to create a new block pair (step 310). If the write command is executed without adding a block pair, the controller 212 directly writes the write data to the block corresponding to the write address (step 314). On the other hand, if a new block pairing is required to execute the write command, the controller 212 stores the write address in the address storage table 220, and stores the write data in one of the flash memory 214. Data temporary storage block 222 (step 312). For example, if the page of the block corresponding to the write address has stored data, and the block does not have a sub-block for storing the update data, the block must be added to execute the write command. The corresponding sub-block is used for storing the written data, resulting in a new set of block pairing. However, the number of block pairs cannot be increased until the integration of one block has been completed. Therefore, the write address must be stored in the address storage table 220 in step 312, and the block pairing is integrated and then based on the bit. The write address stored in the address storage table 220 writes the write data to the flash memory 214.

Next, the controller 212 selects a data segment to be consolidated from the plurality of data segments of the parent block of the target block pair (step 316). Then, the controller 212 integrates the updated data stored in the sub-block paired with the target block into the integrated data segment in the processing period corresponding to the write command, and integrates the integrated data region. The segment is written to the integration block (step 318). Next, the controller 212 checks if all of the data sectors of the parent block paired target block have been integrated and written to the integrated block (step 320). If not, the controller 212 continues to receive subsequent write commands from the host 202 (step 308), and continues to use the processing period corresponding to the subsequent write command to continue to other data segments and targets of the parent block paired with the target block. The updated data of the sub-block storage of the block pairing is integrated and written into the integrated block (step 318) until all the data sections of the parent block of the target block pair have been integrated and written into the integrated block ( Step 320). Finally, since the data stored in the parent block and the sub-block of the target block pair has been integrated into the integrated block, the controller 212 erases the data stored in the parent block and the sub-block of the target block pair (steps) 320), thereby reducing the number of block pairs of the flash memory 214 by one.

4 is a schematic diagram of multiple block pairings of integrated flash memory 214 corresponding to method 300 of FIG. It is assumed that the flash memory 214 has a total of four block pairs such as block pairing 30, block pairing 31, block pairing 60, and block pairing 82, and the controller 212 selects the block pairing 30 as the target block pairing for integration. . It is assumed that the controller 212 divides the data of the parent block of the target block pair 30 into three data sections for data integration, respectively. The controller 212 first receives the first write command from the host 202, and integrates the first data segment of the parent block of the block pair 30 with the update data of the sub-block within 250 ms of the processing time of the first write command. The first integrated data section 4A is obtained, and the first integrated data section 4A is written into the integrated block of the block pair 30. Then, the controller 212 receives the second write command from the host 202, and performs the update data of the second data segment and the sub-block of the parent block of the block pair 30 within 250 ms of the processing time of the second write command. The integration is to obtain the second integrated material section 4B, and the second integrated data section 4B is written into the integrated block of the block pairing 30. Then, the controller 212 receives the third write command from the host 202, and performs the third data segment of the parent block of the block pair 30 and the update data of the sub-block within 250 ms of the processing time of the third write command. Integration is performed to obtain the third integrated data section 4C, and the third integrated data section 4C is written into the integrated block of the block pairing 30, thereby completing data integration of the block pairing 30. Then, the controller 212 can clear the data of the parent block and the sub-block of the block pair 30 to reduce the number of block pairs of the flash memory 214 by one.

Similarly, assume that controller 212 then selects block pair 31 as the target block pair for integration. Similarly, it is assumed that the controller 212 divides the data of the parent block of the target block pair 31 into three data sections to perform data integration, respectively. The controller 212 first receives the fourth write command from the host 202, and integrates the first data segment of the parent block of the block pair 31 with the update data of the sub-block within 250 ms of the processing time of the fourth write command. The first integrated data section 4D is obtained, and the first integrated data section 4D is written into the integrated block of the block pair 31. Next, the controller 212 receives the fifth write command from the host 202, and performs the update data of the second data segment and the sub-block of the parent block of the block pair 31 within 250 ms of the processing time of the fifth write command. The integration is to obtain the second integrated data section 4E, and the second integrated data section 4E is written into the integrated block of the block pair 31. Next, the controller 212 receives the sixth write command from the host 202, and performs the third data segment of the parent block of the block pair 31 and the updated data of the sub-block within 250 ms of the processing time of the sixth write command. The integration is performed to obtain the third integrated data section 4F, and the third integrated data section 4F is written into the integrated block of the block pair 31, thereby completing data integration of the block pairing 31. Then, the controller 212 can clear the data of the parent block and the sub-block of the block pair 31, so that the number of block pairs of the flash memory 214 is further reduced by one.

Figure 5 is an embodiment of an address storage table 500 in accordance with the present invention. After the controller 212 sequentially receives a plurality of write commands from the host 202, the controller 212 stores the write addresses corresponding to the write commands into the address storage table 500. The address storage table 500 includes a plurality of storage units, each of which stores a write address. Each storage unit further has a corresponding storage flag to indicate whether the storage unit has a storage write address. In one embodiment, when the value of the storage flag is 1, it indicates that the corresponding storage unit stores the write address; when the value of the storage flag is 0, it indicates that the corresponding storage unit does not store the write address. The address storage table 500 further includes a storage indicator and a cleaning indicator. The storage indicator points to the storage unit of the address storage table 500 for storing the next write address, and the cleanup indicator points to the storage unit of the address storage table 500 storing the next write address to be cleared. In an embodiment, the storage indicator automatically searches for the storage unit with the storage flag of 0 in the address storage table 500. When the controller 212 wants to store the write command received from the host into the address storage table 500, the write command is stored in the storage unit pointed to by the storage indicator. In an embodiment, the cleanup indicator automatically searches the address storage table 500 for the storage unit storing the write address corresponding to the block number of the highest frequency. When the controller 212 wants to clear the write address from the address storage table 500, the write address is read by the storage unit pointed to by the storage indicator, and the data temporary storage block 222 is temporarily placed according to the write address. The stored data is written to the flash memory 214.

Figure 6 is a flow diagram of a method 600 of clearing a write address stored in an address storage table in accordance with the present invention. First, the controller 212 determines a plurality of blocks to be written corresponding to the plurality of write addresses stored in the address storage table (step 602). For example, the to-be-written block corresponding to the plurality of write addresses stored in the address storage table 500 includes the blocks 150, 200, 133, and 167. Next, the controller 212 calculates the number of write addresses corresponding to the plurality of blocks to be written in the address storage table (step 604). For example, the controller 212 can calculate that the number of write addresses stored in the address storage table 500 by the blocks 150, 200, 133, and 167 are 4, 2, 3, 1, respectively. Next, the controller 212 selects a target to-be-written block having the largest number of write addresses from the plurality of blocks to be written (step 606). Therefore, the controller 212 selects the block 150 corresponding to the largest number of write address numbers 4 as the target to be written block.

Next, the controller 212 retrieves a blank block from the flash memory 214 as a sub-block of the target to-be-written block (step 608). Then, the controller 212 writes, according to the write address of the address storage table 500 corresponding to the target to-be-written block, the data to be written into the target to-be-written block in the data temporary storage block 222 to the target to be written. A sub-block of the block is written (step 610). Since the write address corresponding to the target to-be-written block 500 in the address storage table 500 has four pens, it is written to the fourth page, the fifth page, the sixth page, and the seventh page of the block 150, respectively. At this time, the controller 212 writes the data extracted from the data temporary storage block 222 into the sub-block of the block 150 to store the updated data of the fourth page, the fifth page, the sixth page, and the seventh page of the block 150. Next, the controller 212 deletes a plurality of write addresses corresponding to the target to-be-written block 500 from the address storage table 500 (step 612). FIG. 7 is a schematic diagram of a plurality of block pairs added to the flash memory 214 after clearing the write address of the address storage table 500 of FIG. 5 corresponding to the method 600 of FIG. Assume that the flash memory 214 is paired with the original block pair 60 and the block pair 82. When the self-address storage table 500 clears the four write addresses corresponding to the block 150, a block pair 150 is added to the flash memory 214, wherein the sub-block of the block pair 150 stores the block 150. Updates on pages 4, 5, 6, and 7.

Next, the controller 212 checks if there is still a write address to be written in the address storage table 500 (step 614). Since the four write addresses corresponding to the block 150 in the address storage table 500 have been cleared, the current address storage table 500 still has write addresses corresponding to the blocks 200, 133, and 167, wherein The number of write addresses corresponding to block 133 is the most. Therefore, the controller 212 continues to select the block 133 corresponding to the maximum number of write address numbers 3 as the target to be written block (step 606), and the write address according to the address storage table 500 will be used by the data temporary storage block. The data fetched in 222 is written to the sub-block of block 133 to store the updated data on pages 34, 35, and 36 of block 133 (step 610). Referring to FIG. 7, when the self-address storage table 500 clears the three write addresses corresponding to the block 133, a block pair 133 is added to the flash memory 214, and the sub-area of the block pair 133 is added. The block stores the updated information on pages 34, 35, and 36 of block 133. The loop of steps 606-612 will continue until the write address in the address storage table 500 is cleared.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

(Fig. 2)

202. . . Host

204. . . Data storage device

212. . . Controller

214. . . Flash memory

216. . . Random access memory

220. . . Address storage table

222. . . Data temporary storage block

224. . . Block pairing

231, 232, ..., 23k, 241, 242, ..., 24k. . . Block

(Fig. 4)

30, 31, 60, 82. . . Block pairing

(Figure 7)

150, 133, 60, 82. . . Block pairing

Figure 1 is a timing diagram of a host transmitting a write command to a data storage device;

Figure 2 is a block diagram of a data storage device in accordance with the present invention;

Figure 3 is a flow chart of a method for integrating block pairing according to the present invention;

Figure 4 is a schematic diagram of multiple block pairing of integrated flash memory corresponding to the method of Figure 3;

Figure 5 is an embodiment of an address storage table in accordance with the present invention;

Figure 6 is a flow chart showing a method of clearing a write address stored in an address storage table in accordance with the present invention;

FIG. 7 is a schematic diagram showing a plurality of block pairs of the flash memory added after the write address of the address storage table of FIG. 5 is cleared corresponding to the method of FIG. 6.

Claims (19)

A method for integrating block pairing of a flash memory, comprising: selecting a target block pair from a plurality of block pairs of the flash memory for integration; storing the target block in a parent block The data is divided into a plurality of data segments; a blank block of the flash memory is selected as an integrated block for storing integrated data of the target block pair; a plurality of write commands are received from a host; The plurality of processing periods corresponding to the input command are respectively integrated with the updated data stored in the sub-block paired with the target block and written into the integrated block. The method for integrating block matching of flash memory according to claim 1, wherein the method further comprises: after the data segment is integrated with the updated data and written into the integrated block, erasing the The data stored in the parent block and the sub-block of the target block pairing. The method for integrating block of flash memory according to claim 1, wherein the integration of the data segments with the updated data and the writing of the integrated block further comprises: selecting from the data segments. And integrating the updated data of the sub-block paired with the target block to generate an integrated data section, and integrating the integrated data section in one of the processing periods The data section is written into the integration block; and if the data sections are not all integrated and written into the integration block, the selection step of re-executing the data section to be integrated and the generation of the integrated data section and Write step. The method for integrating block of flash memory according to claim 1, wherein each of the write commands includes a write address and a write data, and the method further comprises: receiving After the write command, it is checked whether the number of block pairs of the flash memory needs to be newly added when executing the write command; and if the write command is executed, the block pairing of the flash memory needs to be added. The number of write addresses of the write commands is stored in the address storage table, and the write data of the write commands is stored in a data temporary storage block of the flash memory. The method for integrating block matching of flash memory according to claim 4, wherein the method further comprises: if the writing command is executed, the number of block pairs of the flash memory is not required to be added. And writing the write data to the block corresponding to the write address according to the write commands. The method for integrating block of flash memory according to claim 4, wherein the address storage table comprises a plurality of storage units, and each of the storage units can store a write address, and each A storage unit has a corresponding storage flag to indicate whether the storage unit has a storage write address. The method for integrating block of flash memory according to claim 6 , wherein the address storage table further comprises a storage indicator and a cleaning indicator, wherein the storage indicator is available in the address storage table. The storage unit of the next write address is stored, and the cleanup indicator points to a storage unit in the address storage table storing the next write address to be cleared. The method for integrating block of flash memory according to claim 7 , wherein the storage indicator automatically searches the address storage table for the storage that does not store the write address according to the storage flags. unit. The method for integrating block matching of flash memory according to claim 7, wherein the cleaning indicator automatically searches the address storage table for a write bit storing a write block corresponding to the highest frequency. The storage unit of the address. The method for integrating block matching of flash memory according to claim 4, wherein the method further comprises: when the plurality of write addresses stored in the address storage table are to be cleared, determining the write Entering a plurality of to-be-written blocks corresponding to the address; calculating a number of write addresses corresponding to the waiting write block in the address storage table; selecting the largest write from the waiting write block a target number of addresses to be written to the block; obtaining a blank block from the flash memory as a sub-block of the target to be written block; according to the address storage table corresponding to the target to be written area The write address of the block writes the write data stored in the data temporary storage block to the sub-block of the target to-be-written block; and deletes from the address storage table corresponding to the target to-be-written area The write address of the block. A data storage device coupled to a host, comprising: a flash memory, including a data temporary storage block and a plurality of block pairs; and a controller from the flash memory The equal block matching selects a target block pair for integration, and the data stored in the parent block paired with the target block is divided into a plurality of data segments, and one blank block of the flash memory is selected as the storage block. An integrated block of the integrated data of the target block pairing, receiving a plurality of write commands from the host, and respectively respectively the data segments and the target block in the plurality of processing periods corresponding to the write commands The updated data stored in the paired sub-blocks is integrated and written into the integrated block. The data storage device of claim 11, wherein after the data segment is integrated with the updated data and written into the integrated block, the controller further erases the parent block of the target block pair and The data stored in the sub-block. The data storage device of claim 11, wherein each of the write commands includes a write address and a write data, and after receiving the write command, the controller checks to execute the Whether the write command needs to add the number of block pairs of the flash memory, and if the write command needs to add the number of block pairs of the flash memory, the controller writes the number of blocks. The write address of the input command is stored in the address storage table, and the write data of the write command is stored in the data temporary storage block of the flash memory. The data storage device of claim 13, wherein if the writing command is executed, the number of block pairs of the flash memory is not required to be added, the controller according to the write command The write data is written to the block corresponding to the write address. The data storage device of claim 13, wherein the address storage table comprises a plurality of storage units, each of the storage units can store a write address, and each storage unit has a corresponding storage. Flag to indicate whether the storage unit has a storage write address. The data storage device of claim 15, wherein the address storage table further comprises a storage indicator and a cleaning indicator, wherein the storage indicator points to the address storage table for storing the next write address. And storing the unit, and the cleaning indicator points to a storage unit in the address storage table storing the next write address to be cleared. The data storage device of claim 16, wherein the storage indicator automatically searches the address storage table for the storage unit that does not store the write address according to the storage flags. The data storage device of claim 16, wherein the cleaning indicator automatically searches the address storage table for a storage unit storing a write address corresponding to the highest frequency write block. The data storage device of claim 13, wherein when the data storage device wants to clear a plurality of write addresses stored in the address storage table, the controller determines the corresponding address of the write address. Determining a number of write addresses corresponding to the write block in the address storage table, and selecting a target having the largest number of write addresses from the wait write block a block to be written, a blank block is obtained from the flash memory as a sub-block of the target to be written block, and the write address corresponding to the target to be written block in the address storage table is stored according to the address Writing the data stored in the data temporary storage block to the sub-block of the target to-be-written block, and deleting the write address corresponding to the target to-be-written block from the address storage table .