TWI429204B - Compact layout structure for decoder with pre-decoding and source driving circuit using the same - Google Patents

Description

Decoder with pre-decoding function using tight layout structure and Source drive circuit

The present invention relates to a decoder, and more particularly to a decoder having a tight layout.

A wide variety of electronic devices, such as televisions, notebook computers, screens, and communication devices, have display devices. Therefore, in order to reduce the size and cost of electronic devices, it is desirable to make the display device light, thin, and short. In order to meet such a demand, a variety of flat panel displays (FPDs) have been developed as alternatives to conventional cathode ray tube displays.

A liquid crystal display (LCD) is one of the flat displays. After the picture data is transferred to the timing controller of the liquid crystal display and then transferred to the source driver, the source driver then generates a driving voltage according to the picture data to drive the display to display the picture.

For example, the color depth of a liquid crystal display can be expressed as 6-bit (that is, each red, green, and blue data has 6 bits) or 8-bit (that is, each red, green, and blue data has 8 bits). Bits), as the color depth increases, the source driver can have a higher resolution.

However, increasing the resolution of the source driver increases the cost, especially for digital-to-analog converters (DACs) built into the source driver, which can be used to convert digital input data to analog drive voltages. Because the number of transistors included in the digital analog converter will vary with The increase in resolution has increased dramatically, resulting in an increase in the size of the digital analog converter.

FIG. 1 is a circuit diagram of a conventional digital analog converter. As shown in FIG. 1, the digital analog converter 100 includes a full-type decoder 110 that receives 10-bit digital data to select one of the gamma voltages based on the 10-bit digital data. There are 1024 gamma voltages with a potential between VA and VS and 1024 potentials V0~V1023.

The decoder 110 receives 10-bit digital input data, such as bits D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and inverse phase elements D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B, and D9B, and the decoder 110 selects a gamma voltage from the gamma voltages V0, V1, V2, ..., V1022, and V1023 according to the 10-bit digital input data.

The decoder 110 includes 1024 transistor columns 111 corresponding to the gamma voltages V0, V1, V2, ..., V1022, and V1023, respectively. Among the 1024 transistor columns 111, each of the transistor columns 111 includes ten series in series. A transistor together, and each transistor receives a bit or inverse phase element of the digital input data.

For example, when the digital input data is '0000000001', the gamma voltage V1 is output. Since the gate of the corresponding transistor M10 is connected to D0, and the gates of the corresponding transistors M11~19 are connected to the inverted signals D1B to D19B, the selected gamma voltage V1 is output to the liquid crystal display.

However, a full-type decoder occupies a large amount of wafer area. For example, a 10-bit full-type decoder requires 1024 (that is, 2 ¹⁰ ) transistor columns 111, and the number of such transistors is quite large. (10 × 1024 = 10240). What's more, the 12-bit full-type decoder requires 4096 transistor columns with 12 x 4096 = 49152 transistors, which is more than four times larger than a 10-bit full-mode transistor.

The present invention provides a decoder and a source driver using the same for receiving a digital data and outputting an analog voltage to reduce circuit area and power consumption.

An embodiment of the present invention provides a decoder using a pre-decoded layout structure. The decoder includes: a main switch array for receiving digital data and outputting a voltage when the digital data is within a first range. A first pre-decoding switch array is configured to receive digital data, and pre-decode part of the digital data and the output voltage when the digital data is in a second range. And a second pre-decoding switch array for receiving digital data, and pre-decoding part of the digital data and the output voltage when the digital data is in a third range. The combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is substantially a rectangular layout structure.

Furthermore, the number of column switches of the main switch array is N0, the number of column switches of the first pre-decoding switch array is N1, the number of column switches of the second pre-decoding switch array is N2, and N0=N1+N2, Where N0, N1 and N2 are positive integers.

Therefore, the decoder has a miniaturized and rectangular layout structure because The miniaturized and rectangular layout structure reduces the power consumption and chip area of the decoder.

Another embodiment of the present invention provides a digital analog converter of a source driver in a display. The digital analog converter includes a decoder for generating a plurality of gamma voltages, which can be used to represent a plurality of gray scales. The value and the grayscale voltage that produces the analogy. The decoder further includes: a main switch array for receiving digital data and outputting the voltage when the digital data is within a first range. A first pre-decoding switch array is configured to receive digital data, and pre-decode part of the digital data and the output voltage when the digital data is in a second range. And a second pre-decoding switch array for receiving digital data, and pre-decoding part of the digital data and the output voltage when the digital data is in a third range. The combination of the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array is substantially a rectangular layout structure.

Looking further, the number of column switches of the switch array is N0, the number of column switches of the first pre-decoding switch array is N1, the number of column switches of the second pre-decoding switch array is N2, and N0=N1+N2, wherein N0, N1, and N2 are positive integers.

Therefore, the source driver has a miniaturized and rectangular layout structure, and because of the miniaturized and rectangular layout structure, the power consumption of the decoder and the chip area can be reduced.

The above described features and advantages of the present invention will be more apparent from the following description.

The embodiments described below will be described in detail with reference to the drawings of the embodiments. The same or similar reference numerals are used in the drawings to describe the same or similar parts.

2 is a diagram of a decoder using a pre-decode layout structure in accordance with an embodiment of the present invention. The decoder 200 selects one of the gamma voltages from the gamma voltages V0 to V1023 according to the digital input data D0~D9 and D0B~D9B. The decoder 200 includes a primary switch array 210, a first pre-decode switch array 220, and a second pre-decode switch array 230. The main switch array 210 is a full-type decoder for selecting one of the gamma voltages V0~V991; the first pre-decoding switch array 220 is for selecting one of the gamma voltages V992~V1007; The second pre-decoding switch array 230 is configured to select one of the gamma voltages V1008~V1023.

FIG. 3 illustrates a first pre-decoding switch array 220 using a layout structure. The pre-decode switches in the first pre-decoding switch array 220 for pre-decoding are arranged in columns and rows. FIG. 4 illustrates a second pre-decoding switch array 230 using a layout structure. The pre-decode switches in the second pre-decoding switch array 230 for pre-decoding are arranged in columns and rows.

The decoder 200 receives, for example, 10-bit digital data to select one of the gamma voltages, the gamma voltages V0, V1 from the gamma voltages V0, V1, V2, ..., V1022, and V1023 according to the 10-bit digital data. The potentials of V2, ..., V1022 and V1023 are between voltages VS and VA. The digital input data includes the bit values D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and/or the inverse value of each bit value. It is D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B and D9B.

The main switch array 210 includes 992 transistor columns 221 corresponding to the gamma voltages V0, V1, V2, ..., V990, and V991, respectively, to select one of the gamma voltages from the gamma voltage in accordance with the received digital data. Each of the 992 transistor columns 221 includes ten transistors connected in series, and the bit values corresponding to the 10-bit digital input data and their corresponding inverted bits are respectively input to the ten transistors. Gate.

The main switch array 210 can be regarded as a digital analog converter for outputting a gamma voltage according to the digital data 0000000000~1111011111. For example, after the digital data '0000000001' is input to the main switch array 210, the main switch array 210 selects the gamma voltage V1 and outputs it as Vout. Similarly, when the digital data is input to '1111011111' to the main switch array 210, the main switch array 210 selects the gamma voltage V991 and outputs it as Vout.

The first pre-decoding switch array 220 of the decoder 200 includes 16 transistor columns 221, which respectively correspond to the gamma voltage V992 according to the digital input data having the Most Significant Bits (MSB) '111110'. V993, ..., V1006 and V1007. The first pre-decoding switch array 220 selects one of the gamma voltages from the gamma voltages V992, V993, ..., V1006, and V1007 according to the received digital data and the pre-decode signal K1. Each column of the 16 transistor columns 221 includes a first pre-decode transistor Mpre1 and four transistors connected in series. Figure 5 is a diagram for receiving a portion of the digital input data (the highest in the embodiment) A map of the pre-decoder 510 that generates the pre-decode signal K1. The predecoder 510 is, for example, an AND gate. In the present embodiment, the digital data D4B, D5, D6, D7, D8, and D9 are input to the predecoder 510, and the digital data D4B, D5, D6, and D7 are input. When D8 and D9 are all "1" (ie, logic high), the pre-decode signal K1 is set to the state "1". Otherwise, the pre-decode signal K1 is set to state "0" (ie, logic low).

Therefore, through the predecoder 510, the first pre-decoding switch array 220 operates only when the digital data D4B, D5, D6, D7, D8, and D9 are all "1". Referring to FIG. 2 and FIG. 3 simultaneously, each of the 16 transistor columns 221 has five transistors (one first pre-decode transistor Mpre1 and four transistors) connected in series. The gates of the five transistors in the 16 transistor columns 221 respectively receive the bit values of the pre-decode signal K1 and the four digital input data, that is, D0, D1, D2, and D3, or D0B, D1B, and D2B. And D3B.

Therefore, the first pre-decoding switch array 220 can be regarded as a digital analog converter for outputting the gamma voltage according to the digital data 1111100000~1111101111. For example, after the digital data '1111100001' is input to the first pre-decoding switch array 220, the first pre-decoding switch array 220 selects the gamma voltage V1007 and outputs it as Vout.

The second pre-decoding switch array 230 of the decoder 200 includes 16 transistor columns 231 corresponding to the gamma voltage V1008 according to the digital input data having the Most Significant Bits (MSB) '111111'. V1009...V1022 and V1023. Second pre-decoding The off array 230 selects one of the gamma voltages from the gamma voltages V1008, V1009...V1022 and V1023 based on the received digital data and the pre-decode signal K2. Each of the transistor columns 231 includes a second pre-decode transistor Mpre2 and four transistors connected in series, and the gate terminal of the second pre-decode transistor Mpre2 receives the pre-decode signal K2. 6 is a schematic diagram of a predecoder 610 for receiving a portion of the digital input data (the most significant bit in the embodiment) and generating the pre-decode signal K2. The predecoder 610 is, for example, an AND gate. In this embodiment, the digital data D4, D5, D6, D7, D8, and D9 are input to the predecoder 610, when the digital data D4, D5, D6, D7, When both D8 and D9 are in the state "1", the pre-decode signal K2 is set to the state "1", whereas the pre-decode signal K2 is set to the state "0".

Therefore, through the predecoder 610, the second pre-decoding switch array 230 operates only when the digital data D4, D5, D6, D7, D8, and D9 are all "1". Referring to FIG. 2 and FIG. 4 simultaneously, each of the 16 transistor columns 231 has five transistors (one second pre-decode transistor Mpre2 and four transistors) connected in series. The gates of the five transistors in the six transistor columns 231 respectively receive the bit values of the pre-decode signal K2 and the four digit input data, that is, D0, D1, D2, and D3, or D0B, D1B, and D2B. And D3B.

Therefore, the second pre-decoding switch array 230 can be regarded as a digital analog converter for outputting the gamma voltage according to the digital data 1111110000~1111111111. For example, after the digital data '1111110001' is input to the second pre-decoding switch array 230, the second pre-decoding switch array 230 is selected. The gamma voltage V1009 is output as Vout. From another example, after the digital data '1111111111' is input to the second pre-decoding switch array 230, the second pre-decoding switch array 230 selects the gamma voltage V1023 and outputs it as Vout.

Therefore, the primary switch array 210, the first pre-decode switch array 220, and the second pre-decode switch array 230 can be considered as a 10-bit digital analog converter when used in combination. The number of bits of the digital data may vary depending on the designer or other purposes, and the bit number of the digital data is not intended to limit the invention.

Please refer to FIG. 2, FIG. 3 and FIG. 4 at the same time, because the main switch array 210 has a width of 10 transistors in the column direction, and the first pre-decoding switch array 210 and the second pre-decoding switch array decoder 220 are in the column direction. Each has a width of five transistors, so the layout structure of the decoder 200 can be miniaturized and can be rectangular. Therefore, the width of the decoder 200 corresponds to 10 transistors, and the length of the decoder 200 corresponds to the 992+16=1008 transistor column. The decoder 200 has a smaller wafer area than the full type decoder having 1024 transistor columns in FIG.

Moreover, another decoder that uses the pre-decoding function of the layout structure is disclosed in other embodiments of the present invention. FIG. 7A is a diagram showing a layout structure of a decoder having a pre-decoding function according to another embodiment of the present invention. The decoder 700 selects one of the gamma voltages from the gamma voltages V0 to V1023 according to the digital input data D0~D9 and D0B~D9B. The decoder 700 includes a primary switch array 710, a first pre-decode switch array 720, a second pre-decode switch array 730, a third pre-decode switch array 740, and a fourth pre-decode. Switch array 750.

The decoder 700 receives, for example, 10-bit digital data to select one of the gamma voltages, the gamma voltages V0, V1, from the gamma voltages V0, V1, V2, ..., V1022, and V1023 according to the 10-bit digital data. The potentials of V2, ..., V1022 and V1023 are between the voltages VS and VA. The digital input data includes bit values D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and/or inverse values of each bit value, that is, D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B and D9B.

The main switch array 710 is a full-type decoder for selecting one of the gamma voltages from the gamma voltages V0 to V959; the first pre-decoding switch array 720 is for inputting the digital input having the most significant bit "111110" Data, and select one of the gamma voltages from the gamma voltages V992~V1007; the second pre-decoding switch array 730 is used to input the data according to the digits with the most significant bit "111111", and from the gamma voltage V1008~V1023 One of the gamma voltages is selected; the third pre-decoding switch array 740 is configured to select one of the gamma voltages from the gamma voltages V960 to V975 according to the digital input data having the most significant bit "111100"; the fourth pre-decoding The switch array 750 is configured to select one of the gamma voltages from the gamma voltages V976~V991 according to the digital input data having the most significant bit "111101".

The main switch array 710 of the decoder 700 includes 960 transistor columns 711 corresponding to the gamma voltages V0, V1, V2, ..., V958 and V959, respectively, to select one of the gamma voltages depending on the received digital data. Ma voltage. Each of the 960 transistor columns 711 includes ten transistors connected in series, the gates of which receive the bit values and inverse bits corresponding to the 10-bit digital input data, respectively.

The main switch array 710 can be regarded as a digital analog converter for outputting a gamma voltage according to the digital data 0000000000~1111101111. For example, after the digital data '0000000001' is input to the main switch array 710, the main switch array 710 selects the gamma voltage V1 and outputs it as Vout. Similarly, after the digital material '1111001111' is input to the main switch array 710, the main switch array 710 selects the gamma voltage V959 and outputs it as Vout.

The first pre-decoding switch array 720 and the second pre-decoding switch array 730 are identical to the first pre-decoding switch array 220 and the second pre-decoding switch array 230, respectively. Therefore, the digital data 1111100000~1111101111 can be converted into the gamma voltages V992~V1007 via the first pre-decoding switch array 720, and the digital data 1111110000~1111111111 can be converted into the gamma voltages V1008~V1023 via the second pre-decoding switch array 730.

FIG. 7B illustrates a third pre-decoding switch array 740 using a layout structure, and FIG. 7C illustrates a fourth pre-decoding switch array 750 using a layout structure. The third pre-decoding switch array 740 and the fourth pre-decoding switch array 750 are similar to the first pre-decoding switch array 210 and the second pre-decoding switch array 220, respectively, except for the pre-decode signal K3 and the pre-decode signal K4. The third pre-decoding switch array 740 of the decoder 700 includes 16 transistor columns 741 respectively corresponding to the gamma voltages V960-V975, and the fourth pre-decoding switch array 750 of the decoder 700 includes 16 bars corresponding to the gamma voltages, respectively. The transistor column 751 of V976~V991.

7D and 7E are respectively a schematic diagram and a predecoder for receiving a portion of the digital input data (the most significant bit in the embodiment) and the predecoder 742 generating the pre-decode signal K3 and the pre-decode signal K4. Schematic diagram of 752. The pre-decoders 740 and 752 are, for example, AND gates. In the present embodiment, the digital data D4B, D5B, D6, D7, D8, and D9 are input to the predecoder 742, and the digital data D4B, D5B, When D6, D7, D8, and D9 are all in the state "1", the pre-decode signal K3 is set to the state "1", and conversely, the pre-decode signal K3 is set to the state "0". After the digital data D4, D5B, D6, D7, D8, and D9 are input to the predecoder 752, when the digital data D4, D5B, D6, D7, D8, and D9 are all the state "1", the pre-decode signal K4 is set to the state "1", whereas the pre-decode signal K4 is set to the state "0".

Referring again to FIGS. 7A and 7B, each of the 16 transistor columns 741 has five transistors (one third pre-decode transistor Mpre3 and four transistors) connected in series. Similarly, referring again to FIGS. 7A and 7C, each of the 16 transistor columns 751 has five transistors (one third pre-decoded transistor Mpre4 and four transistors) connected in series.

Please refer to FIG. 7A, FIG. 7B and FIG. 7C at the same time, because the main switch array 710 has a width of 10 transistors in the column direction, and the first pre-decoding switch array 720 and the second pre-decoding switch array decoder 730 are in the column direction. Then each has a width of 5 transistors, and the third pre-decoding switch array 740 and the fourth pre-decoding switch array decoder 750 each have 5 in the column direction. The width of the transistor, so the layout structure of the decoder 700 can be miniaturized and can be rectangular. Therefore, the width of the decoder 700 corresponds to 10 transistors, and the length of the decoder 700 corresponds to 960+16+16=992 transistor columns. The decoder 700 has a smaller wafer area than the full type decoder having 1024 transistor columns in FIG.

Furthermore, another decoder having a pre-decoding function using a layout structure is disclosed in other embodiments of the present invention. FIG. 8 is a diagram showing a decoder having a pre-decoding function using a layout structure according to still another embodiment of the present invention. The decoder 800 includes a first primary switch array 810, a second primary switch array 820, a first pre-decode switch array 830, and a second pre-decode switch array 840.

The decoder 800 receives, for example, 10-bit digital data to select one of the gamma voltages, the gamma voltages V0, V1, V2 from the gamma voltages V0, V1, V2, ..., V1022, and V1023 according to the 10-bit digital data. The potentials of ..., V1022 and V1023 are between voltage VS and VA. The digital input data includes bit values D0, D1, D2, D3, D4, D5, D6, D7, D8, and D9, and/or inverse values of each bit value, that is, D0B, D1B, D2B, D3B, D4B, D5B, D6B, D7B, D8B and D9B.

The first main switch array 810 is a full-type decoder for selecting one of the gamma voltages from the gamma voltages V0 to V959; the first main switch array 820 is a full-type decoder for gamma One of the voltages V992~V1023 selects one of the gamma voltages; the first pre-decoding switch array 830 is used to select one of the gamma voltages from the gamma voltages V960~V975; The decode switch array 840 is configured to select one of the gamma voltages from the gamma voltages V976~V991.

Referring to FIG. 8, the first primary switch array 810 is the same or similar to the primary switch array 710. For example, the first main switch array 810 includes 960 transistor columns 811 corresponding to the gamma voltages V0, V1, V2, ..., V958 and V959, respectively, so that the digital data 0000000000~1111101111 can be converted via the first main switch array 810. Chengma voltage V0~V959.

The second primary switch array 820 is also the same or similar to the primary switch array 710, but converts the digital input data to different gamma voltages. The second main switch array 820 of the decoder 800 includes 32 metal oxide silicon (MOS) transistor columns 821 corresponding to the gamma voltages V992, V993, ..., V1022 and V1023, respectively, according to the received digital data. Select one of the gamma voltages from the gamma voltage. Each of the 32 transistor columns 821 includes ten transistors connected in series. The bit value corresponding to the 10-bit digital input data and its corresponding inverted bit are respectively input to the gates of the ten transistors, so the digital data 1111100000~1111111111 can be converted via the second main switch array 820. Chengma voltage V992~V1023.

The first pre-decoding switch array 830 is identical to the second pre-decoding switch array 840 to the third pre-decoding switch array 740 and the fourth pre-decoding switch array 750. Therefore, the digital data 1111000000~1111001111 can be converted into the gamma voltages V960~V975 via the first pre-decoding switch array 830, and the digital data can be processed via the second pre-decoding switch array 840. 1111010000~1111011111 is converted into gamma voltage V976~V991.

Please refer to FIG. 8 because the first main switch array 810 has a width of 10 transistors in the column direction, and the first pre-decoding switch array 830 and the second pre-decoding switch array decoder 840 each have 5 electric powers in the column direction. The width of the crystal, and the second main switch array 820 has a width of 10 transistors in the column direction, so the layout structure of the decoder 800 can be miniaturized and can be rectangular. Thus, the width of decoder 800 corresponds to 10 transistors, and the length of decoder 800 corresponds to 960+16+32=1008 transistor columns. The decoder 800 has a smaller wafer area than the full type decoder having 1024 transistor columns in FIG.

9 is a schematic diagram of a display in accordance with an embodiment of the present invention. The display 900 includes a timing controller 910, a source driver 920, and a liquid crystal display panel 980. The timing controller 910 outputs control signals and digital data to the source driver 920. The source driver 920 includes a temporary storage circuit 940, a displacement temporary storage circuit 950, and a digital analog converter 960 to output a buffer 970.

The temporary storage circuit 940 stores the digital data provided by the timing controller 910. Because the temporary storage circuit 940 and the digital analog converter 960 operate at low voltage and high voltage, respectively, the displacement temporary storage circuit 950 converts the output potential of the temporary storage circuit 940 so that the digital data provided by the temporary storage circuit 940 can be input to the digital position. Analog converter 960.

The digital analog converter 960 generates a gamma voltage and receives the digital data that has been quasi-displaced by the displacement temporary storage circuit 950, and then selects an appropriate gamma voltage according to the digital data to output an analog gray scale voltage. Output buffer 970 amplifies the power of the analog gray scale voltage from digital analog converter 960 Pressing and outputting the amplified analog gray scale voltage to the data line of the liquid crystal display panel 980.

FIG. 10 illustrates a digital analog converter 960 for converting 10-bit digital data in accordance with an embodiment of the present invention. Referring to FIG. 10, the digital analog converter 960 includes a gamma voltage converter 962 and a decoder 961. The gamma voltage converter 962 generates a gamma voltage having a different voltage level, and the gamma voltage is between the voltage levels VA and VS, and the decoder 961 receives the 10-bit digital data to select one of the gamma voltages. The decoder 961 can use the layout structure in FIG. 2, FIG. 7A or FIG.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Digital Analog Converter

110, 200, 700, 800, 961‧‧ ‧ decoder

111, 211, 221, 231, 711, 721, 731, 741, 751, 811, 821, 831, 841 ‧ ‧ transistor column

210, 710‧‧‧ main switch array

220, 720, 830‧‧‧ first pre-decoding switch array

230, 730, 840‧‧‧ second pre-decoding switch array

510, 610‧‧‧ predecoder

740‧‧‧third pre-decoding switch array

750‧‧‧fourth pre-decoding switch array

810‧‧‧The first major switch array

820‧‧‧Second main switch array

900‧‧‧ display

910‧‧‧Sequence Controller

920‧‧‧Source Driver

940‧‧‧ temporary storage circuit

950‧‧‧Displacement temporary storage circuit

960‧‧‧Digital Analog Converter

962‧‧‧珈玛电压转换器

970‧‧‧Output buffer

980‧‧‧LCD panel

M10~M19‧‧‧O crystal

V0~V1023‧‧‧珈玛电压

D0~D9, D0B~D9B‧‧‧ digital data

Mpre1‧‧‧first pre-decoded transistor

Mpre2‧‧‧Second pre-decoded transistor

K1~K4‧‧‧ pre-decode signal

FIG. 1 is a circuit diagram of a conventional digital analog converter.

2 is a diagram of a decoder using a pre-decode layout structure in accordance with an embodiment of the present invention.

FIG. 3 illustrates a first pre-decoding switch array 220 using a layout structure.

FIG. 4 illustrates a second pre-decoding switch array 230 using a layout structure.

FIG. 5 illustrates a predecoder 510 for receiving a portion of digital input data (the most significant bit in the embodiment) and generating a pre-decode signal K1. Schematic diagram.

6 is a schematic diagram of a predecoder 610 for receiving a portion of the digital input data (the most significant bit in the embodiment) and generating the pre-decode signal K2.

FIG. 7A is a diagram showing a layout structure of a decoder having a pre-decoding function according to another embodiment of the present invention.

FIG. 7B illustrates a third pre-decoding switch array 740 that uses a layout structure.

FIG. 7C illustrates a fourth pre-decoding switch array 750 that uses a layout structure.

FIG. 7D is a schematic diagram of a predecoder 742 for receiving a portion of the digital input data (the most significant bit in the embodiment) and the pre-decode signal K3.

FIG. 7E is a schematic diagram of a predecoder 752 for receiving a portion of the digital input data (the most significant bit in the embodiment) and generating the pre-decode signal K4.

FIG. 8 is a diagram showing a decoder having a pre-decoding function using a layout structure according to still another embodiment of the present invention.

9 is a schematic diagram of a display in accordance with an embodiment of the present invention.

FIG. 10 illustrates a digital analog converter 960 for converting 10-bit digital data in accordance with an embodiment of the present invention.

200‧‧‧Decoder

210‧‧‧Main switch array

211, 221, 231‧‧‧ transistor columns

220‧‧‧First pre-decoding switch array

230‧‧‧Second pre-decoding switch array

V0~V1023‧‧‧珈玛电压

D0~D9, D0B~D9B‧‧‧ digital data

Claims (14)

A decoder for receiving a digital data and outputting an analog voltage, the decoder comprising: a main switch array for receiving the digital data and outputting a voltage when the digital data is within a first range, wherein The main switch array is a full-type decoder; a first pre-decoding switch array is configured to receive the digital data, and pre-decode part of the digital data and the output voltage when the digital data is in a second range, wherein Each of the first pre-decoding switch arrays includes a first pre-decoding switch and a plurality of first switches, the first pre-decoding switch being controlled by a first pre-decode signal; and a second pre-decoding switch array, Receiving the digital data, pre-decoding part of the digital data and the output voltage when the digital data is in a third range, wherein each of the second pre-decoding switch arrays comprises a second pre-decoding switch and a plurality of a second switch, wherein the second pre-decoding switch is controlled by a second pre-decode signal; wherein the main switch array, the first pre-decoding switch array, and the The combination of the pre-decoding switch array is substantially a rectangular layout structure, the number of column switches of the main switch array is N0, and the number of the first pre-decoding switches and the first switches in the first pre-decoding switch array is N1, the second pre-decoding switch in the second pre-decoding switch array and the number of the second switches are N2, and N0=N1+N2, where N0, N1, and N2 are positive integers, and the first pre- The decoding switch array and the output end of the second pre-decoding switch array are coupled to each other. A decoder as claimed in claim 1, wherein N1 = N2. The decoder of claim 1, wherein the primary switch array is configured to select a first gamma voltage from the plurality of first gamma voltages based on the digital data. The decoder of claim 1, wherein the first pre-decoding switch array is configured to select a second gamma voltage from the plurality of second gamma voltages according to the digital data. The decoder of claim 4, wherein the first pre-decoding switch array further comprises a first pre-decoder for pre-decoding the most significant bit of the digital data and providing the first pre- Decode the signal. The decoder of claim 1, wherein the second pre-decoding switch array is configured to select a third gamma voltage from the plurality of third gamma voltages according to the digital data. The decoder of claim 6, wherein the second pre-decoding switch array further comprises a second pre-decoder for pre-decoding the most significant bit of the digital data and providing the first pre- Decode the signal. A source driver includes: a decoder for receiving a digital data and outputting an analog voltage, the decoder comprising: a main switch array for receiving the digital data and the digital data in a first range The internal output voltage, wherein the main switch array is a full-type decoder; a first pre-decoding switch array is configured to receive the digital data, and pre-decode the portion when the digital data is in a second range Digital data And an output voltage, wherein each of the first pre-decoding switch arrays includes a first pre-decoding switch and a plurality of first switches, the first pre-decoding switch being controlled by a first pre-decode signal; and a second a pre-decoding switch array for receiving the digital data, pre-decoding a portion of the digital data and an output voltage when the digital data is in a third range, wherein each of the second pre-decoding switch arrays includes a second pre- a decoding switch and a plurality of second switches, the second pre-decoding switch being controlled by a second pre-decode signal; wherein the main switch array, the first pre-decoding switch array, and the second pre-decoding switch array are combined The number of the column switches of the main switch array is N0, the number of the first pre-decoding switches in the first pre-decoding switch array and the number of the first switches is N1, the second pre- The second pre-decoding switch in the decoding switch array and the number of the second switches are N2, and N0=N1+N2, where N0, N1, and N2 are positive integers, and the first pre-decoding switch array Each coupled to the second output terminal predecode switch array. The source driver of claim 8, wherein N1 = N2. The source driver of claim 9, wherein the main switch array is configured to select a first gamma voltage from the plurality of first gamma voltages according to the digital data. The source driver of claim 8, wherein the first pre-decoding switch array is configured to select a second gamma voltage from the plurality of second gamma voltages according to the digital data. The source driver of claim 11, wherein the first pre-decoding switch array further comprises a first pre-decoder for pre-decoding the most significant bit of the digital data and providing the first Pre-decoded signal. The source driver of claim 8, wherein the second pre-decoding switch array is configured to select a third gamma voltage from the plurality of third gamma voltages according to the digital data. The source driver of claim 13, wherein the second pre-decoding switch array further comprises a second pre-decoder for pre-decoding the most significant bit of the digital data and providing the second Pre-decoded signal.