TWI428751B - Control circuit and control method of flash memory - Google Patents

Description

Flash memory control circuit and control method

The invention relates to a control circuit and a control method for a flash memory, and particularly relates to a method for dynamically selecting a preferred page mapping according to a sequential access or random access of a host to a flash memory system. The control circuit and control method of the flash memory.

Please refer to FIG. 1 , which is a schematic diagram of mapping virtual blocks to physical blocks. The conventional flash memory file system (FFS) uses a block mapping method to map the virtual blocks 120 to the physical block 140, that is, the basic unit of the mapping is a block. . The conventional flash memory file system finds the physical block 140 corresponding to the virtual block 120 by using a block mapping table.

The virtual block 120 and the physical block 140 respectively include a virtual page and a physical page, and the mapping manner of the virtual page and the physical page may be the first page mapping mode or the second page mapping mode described below.

First page mapping

Please refer to FIG. 2, which is a schematic diagram showing the first page mapping mode. The virtual block 120 shown in FIG. 1 is represented by the virtual block 120(1) to the virtual block 120(m) in FIG. 2, and the virtual block 120(1) to the virtual block 120(m). Each includes a virtual page 122 (0) to a virtual page 122 (n). and The physical block 140 shown in FIG. 1 is represented by a physical block 140(1) to a physical block 140(m) in FIG. 2, and the physical block 140(1) to the physical block 140(m) Each includes a physical page 142 (0) to a physical page 142 (n).

The first type of page mapping described above is called an In-Order Block. In the first page mapping mode, the first virtual page 122(1) of the first virtual block 120(1) is mapped to the first physical page of the first physical block 140(1). 142 (1), and the second virtual page 122 (2) of the first virtual block 120 (1) is mapped to the second virtual page 142 of the first physical block 140 (1) (2) And so on. Similarly, the first virtual page 122(1) of the second virtual block 120(2) is mapped to the first physical page 122(1) of the second physical block 140(2), and the first The second virtual page 122(2) of the two virtual blocks 120(2) is mapped to the second physical page 142(2) of the second physical block 140(2), and so on.

Since the virtual page system in the virtual block 120(1) to the virtual block 120(m) is sequentially mapped with the physical page in the physical block 140(1) to the physical block 140(m), it is not required An additional page mapping table can find the physical page 122 corresponding to the physical page 142.

Second page mapping

The second page mapping method is called an Out-of-Order Block. In the second page mapping mode, the physical page 122 in each virtual block 120 and the virtual page 142 in the physical block 140 do not have the above-described sequential mapping relationship. Therefore, you need to create an additional page mapping table (Page Mapping Table) can find the physical page 122 corresponding to the virtual page 142.

However, when the host is on the Random Write Sequence, the first page mapping will result in a lower performance. In addition, when the host is in the Sequential Write Sequence, the second page mapping mode will also reduce the performance. Therefore, how to propose a better solution to improve the performance reduction has become an urgent problem to be solved.

The invention relates to a control circuit and a control method for a flash memory, which dynamically selects a better page mapping mode according to a sequential access or random access of a host to a flash memory system (such as a sequential block (In -Order Block) or Out-Of-Order Block to improve performance.

According to the present invention, a control circuit for a flash memory is proposed. The control circuit of the flash memory is used to control data access between the host and the flash memory, and the control circuit includes a host interface, a flash memory controller, a prediction unit, and an In-Order Block. Take the unit and the Out-Of-Order Block access unit.

The host interface is configured to receive a first access command output by the host to access an update block to the flash memory. The prediction unit determines, according to the first access command, that the host system sequentially accesses the flash memory (Sequential Write) Sequence) or random write sequence to selectively output a first access request (Access Request) or a second access request.

The In-Order Block access unit controls the flash memory controller to perform an In-Order Block Write Operation on the flash memory according to the first access request. The Out-Of-Order Block access unit controls the flash memory controller to perform an Out-Of-Order Block Write Operation write operation according to the second access request.

According to the present invention, a method of controlling a flash memory is proposed. The flash memory control method is used for controlling data access between the host and the flash memory, and the control method comprises: (a) receiving a first access command output by the host, and using the first access command for storing Take the update block to the flash memory. (b) determining, according to the write command, the host to the Sequential Write Sequence or the Random Write Sequence to selectively output the first access request (Access Request) or the second Access request. (c) controlling the flash memory controller to perform an In-Order Block write operation on the flash memory according to the first access request. (d) controlling the flash memory controller to perform an out-of-order block write operation in accordance with the second access request.

In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:

Flash memory control circuit

Please refer to FIG. 3, which is a schematic diagram of a control circuit of a flash memory according to a preferred embodiment of the present invention. The control circuit 30 of the flash memory is coupled between the host 20 and the flash memory 40, and is used to control data access between the host 20 and the flash memory 40. The control circuit 30 includes a host interface 310, a prediction unit 320, an In-Order Block access unit 330, an Out-Of-Order Block access unit 340, and a flash memory controller 350. . The prediction unit 320, the sequential block access unit 330, and the non-sequential block access unit 340 may be implemented in a hardware or software manner, or may be implemented by partially hardware matching a part of the software.

The host interface 310 is coupled to the host 20 and is configured to receive an access command S1 output by the host 20 to access the update block to the flash memory 40. The prediction unit 320 is configured to determine, according to the access command S1, that the host 20 is in the Sequential Write Sequence or the Random Write Sequence to selectively output the access request S2 (Access Request). Or access request S3.

When the host 20 sequentially accesses the flash memory 40, the prediction unit 320 outputs the access request S2 to the In-Order Block access unit 330. The sequential block access unit 330 marks the update block as a sequential block according to the access request S2, and controls the flash memory controller 350 to perform a sequential block write operation on the flash memory 40 according to the access request S2. (In-Order Block Write Operation).

Conversely, when the host 20 randomly accesses the flash memory 40, the prediction unit 320 outputs an access request S3 to an Out-Of-Order Block access unit 340. The Out-Of-Order Block access unit 340 indicates that the update block is a non-sequential block according to the access request S3, and creates a page mapping table according to the update block. In addition, the non-sequential block access unit 340 controls the flash memory controller 350 to perform an out-of-order block write operation write operation according to the access request S3.

Please refer to FIG. 4, which is a schematic diagram showing an access command. Further, the prediction unit 320 determines, for example, that the host 310 sequentially or randomly accesses the flash memory 40 according to the access command S1 and a preset criterion (Predefined Criteria), and the preset criteria may be different depending on the requirements. The implementation of the situation.

For example, the host interface 310 receives the access command S4 before receiving the access command S1, and the host interface 310 receives the access command S5 before receiving the access command S4. The access command S1, the access command S4, and the access command S5 include an access type (such as a read or write), a logical block address (LBA), and a sector count value (Sector Count), respectively. And the prediction unit 320 further records the logical block address and the segment count value of each access command.

The preset criterion is, for example, whether the sum of the logical block address and the segment count value of the access command S4 is equal to the logical block bit of the access command S1. site? If the sum of the logical block address and the segment count value of the access command S4 is equal to the logical block address of the access command S1, it indicates that the host 20 is sequentially accessing the flash memory 40.

Or, further calculating whether the sum of the logical block address and the segment count value of the access command S5 is equal to the logical block address of the access command S4? If the sum of the logical block address and the segment count value of the access command S5 is equal to the logical block address of the access command S4 and the sum of the logical block address and the segment count value of the access command S4 is equal to the access The logical block address of the command S1 indicates that the host 20 is sequentially accessing the flash memory 40.

The foregoing preset criterion is not limited thereto, and the preset criterion may also calculate whether the sum of the logical block address and the segment count value of the n-1th access command is equal to the logical block of the nth access command. Address. Where n = 2~N and N is a positive integer. The preset criteria can determine the value of N depending on the demand.

Flash memory control method

Please refer to FIG. 5, which is a flow chart of a method for controlling a flash memory according to a preferred embodiment of the present invention. The flash memory control method is used to control data access between the host 20 and the flash memory 40, and the control method includes the following steps: First, as shown in step 510, the host interface 310 receives the output of the host 20 output. Command S1, access command S1 is used to access an update block to flash memory 40. Next, as shown in step 520, the logical block address and the segment count value of the access command S1 are recorded.

Following the step 530, the host 20 is determined according to the write command S1. The flash memory 40 is sequentially accessed or randomized (Random Write Sequence) to selectively output an access request S2 or an access request S3. If the prediction unit 320 outputs the access request S2, the host 20 is sequentially accessing the flash memory 40. Conversely, if the prediction unit 320 outputs an access request S3, it indicates that the host 20 is randomly accessing the flash memory 40.

When the host 20 sequentially accesses the flash memory 40, as shown in step 540, the sequential block access unit 330 indicates that the update block is a sequential block. Next, as shown in step 550, the sequential block access unit 330 controls the flash memory controller 350 to perform an In-Order Block write operation on the flash memory 40 in accordance with the access request S2.

Conversely, when the host 20 randomly accesses the flash memory 40, as shown in step 560, the non-sequential block access unit 340 indicates that the update block is a non-sequential block. Next, as shown in step 570, the non-sequential block access unit 340 creates a page mapping table based on the updated block. Then, as shown in step 580, the non-sequential block access unit 340 controls the flash memory controller 350 to perform an out-of-order block write operation in accordance with the access request S3.

The control circuit and the control method of the flash memory disclosed in the above embodiments of the present invention dynamically select a better page mapping mode according to the sequential access or random access of the host 20 to the flash memory 40 ( Such as In-Order Block or Out-Of-Order Block, which improves performance.

In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. The invention has access to the technical field Those skilled in the art can make various changes and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20‧‧‧Host

30‧‧‧Flash memory control circuit

40‧‧‧Flash memory

120, 120 (1) ~ 120 (m) ‧ ‧ virtual blocks

122(1)~122(n)‧‧‧Virtual pages

140, 140 (1) ~ 140 (m) ‧ ‧ physical blocks

144(1)~142(n)‧‧‧Virtual pages

310‧‧‧Host interface

320‧‧‧ Forecasting unit

330‧‧‧Sequential block access unit

340‧‧‧ Non-sequential block access unit

350‧‧‧Flash Memory Controller

Figure 1 is a schematic diagram showing the mapping of virtual blocks to physical blocks.

Figure 2 is a schematic diagram showing the first page mapping mode.

FIG. 3 is a schematic diagram of a control circuit of a flash memory according to a preferred embodiment of the present invention.

Figure 4 depicts a schematic diagram of an access command.

FIG. 5 is a flow chart of a method for controlling a flash memory according to a preferred embodiment of the present invention.

Claims (12)

A flash memory control circuit for controlling data access between a host and a flash memory, the control circuit comprising: a host interface for receiving a first access command of the host output Accessing an update block to the flash memory; a flash memory controller; a prediction unit configured to determine, according to the first access command, the host system to sequentially access the flash memory ( a Sequential Write Sequence or a Random Write Sequence, and outputting a first access request (Access Request) when the host sequentially accesses the flash memory, and the flash memory is generated by the host Outputting a second access request during random access; an In-Order Block access unit configured to control the flash memory controller to execute the flash memory according to the first access request An In-Order Block Write Operation; and an Out-Of-Order Block access unit for controlling the flash memory control according to the second access request Execute a non-sequential block (Out-Of-Order Block) Write operation), wherein the prediction unit determines, according to the first access command and a preset criterion (Predefined Criteria), the host system to a flash memory sequential access sequence (Sequential Write Sequence) or random access ( Random Write Sequence); The host interface receives a second access command before receiving the first access command, where the first access command includes a first logical block address (LBA) and a first a sector count value (Sector Count), the second access command includes a second logical block address and a second segment count value, the preset criterion includes calculating the second logical block address and the first Whether the sum of the two sector count values is equal to the first logical block address to determine whether the host is sequential access or random access to the flash memory. The control circuit of the flash memory as described in claim 1, wherein when the host system sequentially accesses the flash memory, the sequential block access unit marks the update block as a sequential block. . The control circuit of the flash memory as described in claim 1, wherein when the host system randomly accesses the flash memory, the non-sequential block access unit marks the update block as a non-sequential area. Piece. The control circuit of the flash memory according to claim 1, wherein when the host system randomly accesses the flash memory, the non-sequential block access unit establishes a page mapping according to the update block. Table Mapping Table. The control circuit of the flash memory of claim 1, wherein the host interface receives a third access command before receiving the second access command, the third access command includes a first a third logical block address and a third segment count value, the preset criterion further comprising calculating whether the sum of the third logical block address and the third segment count value is equal to the second logical block address To determine that the host system is sequentially accessing the flash memory. Or random access. The control circuit of the flash memory as described in claim 1, wherein the first access command comprises a first logical block address (LBA) and a first segment count value ( Sector Count), the preset unit further records the first logical block address and the first segment count value. A method for controlling a flash memory for controlling data access between a host and a flash memory, the control method comprising: (a) receiving a first access command of the host output, the An access command for accessing an update block to the flash memory; (e) receiving a second access command, the second access command being prior to the first access command, the first save The fetch command includes a first logical block address (LBA) and a first sector count value (Sector Count), the second access command includes a second logical block address and a second a segment count value; (b) determining, according to the write command, the host system to the flash memory sequential access sequence (Sequential Write Sequence) or random access (Random Write Sequence), the host flash memory Outputting a first access request (Access Request) during sequential access, and outputting a second access request when the host randomly accesses the flash memory; (c) controlling the first access request according to the first access request The flash memory controller performs an In-Order Block write to the flash memory. Made; and (d) controlling the flash memory controller according to the second access request Performing an out-of-order block write operation; wherein, in the step (b), determining the host pair fast according to the first access command and a preset criterion (Predefined Criteria) a Sequential Write Sequence or a Random Write Sequence; wherein the preset criterion includes calculating whether a sum of the second logical block address and the second segment count value is equal to the The first logical block address is used to determine that the host is sequentially accessing or random accessing the flash memory. The method for controlling the flash memory as described in claim 7 further includes: (e) when the host system sequentially accesses the flash memory, the sequential block access unit marks the update block As a sequential block. The method for controlling the flash memory according to claim 7 further includes: (e) when the host system randomly accesses the flash memory, the non-sequential block access unit marks the update block. Is a non-sequential block. The method for controlling the flash memory according to the seventh aspect of the invention, further comprising: (e) wherein when the host system randomly accesses the flash memory, the non-sequential block access unit is based on the update area The block creates a page mapping table. The method for controlling the flash memory according to the seventh aspect of the invention, further comprising: (g) receiving a third access command, the third access command is Before the second access command, the third access command includes a third logical block address and a third segment count value. The preset criterion further includes calculating the third logical block address and the first Whether the sum of the three-segment count values is equal to the second logical block address is to determine whether the host is sequential access or random access to the flash memory. The method for controlling a flash memory as described in claim 7 further includes: (e) recording one of the first access commands, a first logical block address (LBA), and a first A sector count value (Sector Count).