TWI427756B - Package structure - Google Patents

Description

Package structure

The present invention relates to a package structure, and more particularly to a package structure including a semiconductor connection element (Interposer).

The advent of semiconductor components is an important milestone in the development of science and technology. Among them, the packaging process plays a pivotal role in semiconductor technology. As semiconductor components continue to advance, components become more diverse, and packaging processes become more complex.

Generally, the semiconductor components are electrically connected and disposed on a substrate, and a package structure is completed by covering the sealant. The external signal can be transmitted to the inside of the semiconductor component through the substrate.

In the pursuit of "light, thin, short, small" design, the designer must set two or more semiconductor components on the same substrate and share the same substrate. It is then packaged into a package structure to reduce product size.

However, each semiconductor component has several electrical contacts. If the electrical contacts of two or more semiconductor components are connected to the substrate, the design of the wires will be a rather difficult task.

Moreover, in the case where the design of the electrical contacts of the semiconductor element is more and more complicated, how to reduce the difference in signal transmission time by how many specific electrical contacts of one semiconductor element or two or more semiconductor elements are generated, and how Improving the transmission efficiency of power signals is an important direction of current research and development.

The present invention relates to a package structure that utilizes the design of the wires of a semiconductor connection element such that the substrate of the package structure can simultaneously form a signal communication path with the first semiconductor element and the second semiconductor element.

According to an aspect of the invention, a package structure is proposed. The package structure includes at least one first semiconductor component, at least one second semiconductor component, a semiconductor connection component, and a substrate. The first semiconductor component includes a plurality of first conductive bumps. The second semiconductor component includes a plurality of second conductive bumps. The semiconductor connecting component includes a connecting main board, at least one signal wire and at least one signal conducting post. The signal wires are placed on the connection board. The two ends of the signal wire are electrically connected to one of the first conductive bumps and one of the second conductive bumps. The signal conductive column is electrically connected to. The substrate is electrically connected to the signal conductive column. The first semiconductor element and the second semiconductor element are both memory chips, and the first semiconductor element and the second semiconductor element have the same line structure.

According to another aspect of the invention, a package structure is proposed. The package structure includes a semiconductor component, a semiconductor connection component, and a substrate. The semiconductor component includes at least two signal conductive bumps. The semiconductor connecting component comprises a connecting main board, at least two signal conducting columns and at least two signal wires. The signal conductive column runs through the connection motherboard. The signal wires are placed on the connection board. Each of the two signal wires is electrically connected to one of the signal conductive bumps and one of the signal conductive posts. The lengths of the individual signal wires are substantially equal. The substrate is electrically connected to the signal conductive column.

In order to make the above description of the present invention more comprehensible, the preferred embodiments are described below, and in conjunction with the accompanying drawings, the detailed description is as follows:

The following is a detailed description of the embodiments, which are intended to be illustrative only and not to limit the scope of the invention. In addition, the drawings in the embodiments omit unnecessary elements to clearly show the technical features of the present invention.

First embodiment

Please refer to FIG. 1 , which illustrates a schematic diagram of a package structure 1000 in accordance with a first embodiment of the present invention. The package structure 1000 of the present embodiment includes a first semiconductor component 100, a second semiconductor component 200, and a semiconductor connection component 300 (interposer) (the material of which comprises a thermo plastic or epoxy) and a Substrate 400. The first semiconductor element 100 and the second semiconductor element 200 are, for example, a memory wafer, a processed wafer, or a photosensitive wafer. In the present embodiment, the first semiconductor element 100 and the second semiconductor element 200 are both memory chips, and the first semiconductor element 100 and the second semiconductor element 200 have the same line structure. The material of the substrate 400 is an insulating material such as glass fiber (FR4) or ceramic material. The semiconductor connection device 300 is disposed between the first semiconductor 100 and the substrate 400 and is disposed between the second semiconductor 200 and the substrate 400. The semiconductor connection component 300 is used to electrically connect the substrate 400 to the first semiconductor component 100 and the second semiconductor component 200 at the same time. In order to clarify the detailed components of the package structure 1000 of the present embodiment, the following is a detailed view of the top view and a plurality of cross-sectional views along different cross-sectional lines as follows.

Please refer to FIG. 2 and FIG. 3A to FIG. 3C , FIG. 2 is a plan view of the package structure 1000 of FIG. 1 , and FIG. 3A is a cross-sectional view of the package structure 1000 of FIG. 2 along a section line A-A′. 3B is a cross-sectional view of the package structure 1000 of FIG. 2 along section line BB′, and FIG. 3C is a cross-sectional view of the package structure 1000 of FIG. 2 taken along section line C-C′. As shown in FIG. 2, the first semiconductor device 100 includes a plurality of first conductive bumps 110, a plurality of third conductive bumps 130, and a plurality of power conductive bumps 150. The second semiconductor device 200 includes a plurality of second conductive materials. The bump 220, the plurality of fourth conductive bumps 240, and the plurality of power conductive bumps 250.

In order to clearly illustrate the detailed components of the package structure 1000, Figure 2 presents the internal components in perspective. The first conductive bumps 110 are arranged along a first extension line L1, and the second conductive bumps 220 are arranged along a second extension line L2. The third conductive bumps 130 are extended along a third extension. The lines L3 are arranged, and the fourth conductive bumps 240 are arranged along a fourth extension line L4. The first extension line L1, the second extension line L2, the third extension line L3, and the fourth extension line L4 are substantially parallel to each other.

Moreover, the distance between the first extension line L1 and the third extension line L3 is substantially 350 micrometers (um). The distance between each of the first conductive bumps 110 is substantially 150 micrometers, and the distance between each of the third conductive bumps 130 is substantially 150 micrometers.

The first conductive bumps 110 and the third conductive bumps 130 are arranged correspondingly. That is, the line L13 of the first conductive bump 110 and the corresponding third conductive bump 130 is substantially perpendicular to the first extension line L1 and the third extension line L3. Similarly, the second conductive bumps 220 and the fourth conductive bumps 240 are arranged correspondingly. That is, the line L24 of the second conductive bump 220 and the corresponding fourth conductive bump 240 is substantially perpendicular to the second extension line L1 and the fourth extension line L4.

Taking FIG. 3A as an example, the first conductive bump 110 and the third conductive bump 130 can be viewed simultaneously along the A-A' cross-sectional view of FIG.

In essence, the first semiconductor device 100 and the second semiconductor device 200 of the present embodiment have a similar structure, so that the first conductive bumps 110 and the third conductive bumps 130 are disposed in the same manner as the second conductive bumps 220 and The four conductive bumps 240 are arranged in a similar manner.

That is to say, the distance between the second extension line L2 and the fourth extension line L4 is also substantially 350 micrometers. The distance between each of the second conductive bumps 220 is also substantially 150 micrometers, and the distance between the fourth conductive bumps 240 is also substantially 150 micrometers.

As shown in FIG. 2, in the case of the semiconductor connection component 300, the semiconductor connection component 300 of the present embodiment includes a connection main board 310, a plurality of signal wires 320, a plurality of power supply wires 340, a plurality of signal conductive columns 330, and a plurality of Power supply conductive post 350. The signal wire 320 is disposed on the connection main board 310. The two ends of the partial signal wires 320 are electrically connected to one of the first conductive bumps 110 and one of the second conductive bumps 220, respectively. The two ends of the other part of the signal wire 320 are electrically connected to one of the third conductive bumps 130 and one of the fourth conductive bumps 240.

Please refer to FIG. 2 , FIG. 3A and FIG. 4 simultaneously. FIG. 4 is a schematic diagram of the first conductive bump 110 , the signal conductor 320 , the signal conductive pillar 330 and the second conductive bump 220 of FIG. 2 . As shown in FIG. 3A, the signal conductive post 330 is connected through the main board 310. The substrate 400 is electrically connected to the signal wire 320 by the signal conductive pillars 330. Moreover, the first conductive bumps 110, the signal wires 320, and the signal conductive pillars 330 form a signal transmission path.

Similarly, the second conductive bumps 220, the signal wires 320, and the signal conductive posts 330 may also form another signal transmission path. That is, the signals of the first conductive bumps 110 and the second conductive bumps 220 can be transmitted to the substrate 400 together (or the substrate 400 can transmit signals to the first conductive bumps 110 and the second conductive via the same signal conductive pillars 330). Bump 220).

As shown in FIG. 4, the signal conductive post 330 is electrically connected to a midpoint M of a line segment of the signal conductor 320. The lengths D1, D2 of the two ends of the line segment midpoint M to the signal conductor 320 are substantially equal. Since the lengths D1 and D2 of the two ends of the line segment M to the signal conductor 320 are substantially equal, the lengths of the two signal transmission paths are also equal, so that the difference between the two signal transmissions causes any difference in transmission time (Difference). In arrival time).

As shown in FIG. 2, in the first semiconductor device 100, the first conductive bump 110 has a plurality of third conductive bumps 130 on the left side and no other conductive bumps on the right side; and in the second semiconductor device 200, There are a plurality of fourth conductive bumps 140 on the left side of the two conductive bumps 220, and no other conductive bumps on the right side. In order to enable the first conductive bumps 110 to be electrically connected to the second conductive bumps 220, and to enable the third conductive bumps 130 to be electrically connected to the fourth conductive bumps 240. The first conductive bumps 110 and the second conductive bumps 220 are staggered.

In more detail, the signal wire 320 extending from the first conductive bump 110 extends first to the right, then extends downward, and then extends to the left to the second conductive bump 220 to form an opening U to the left. Type transition structure. The signal conductor 320 extending from the fourth conductive bump 240 extends first to the left, then extends upward, and then extends to the right to form a U-turn structure having an opening to the right.

For convenience of explanation, the text of "up, down, left, and right" is illustrated by the second drawing. However, the text descriptions of "Up, Down, Left, and Right" are not intended to limit the present invention. Those skilled in the art will understand that as long as the angle is changed in Figure 2, the texts of "Up, Down, Left, and Right" are also explained. Change with it.

The U-shaped transition structure extends the distance between the midpoint M and the two end points of the line segment of the signal conductor 320, and a portion of the signal conductive pillars 330 are arranged along a fifth extension line L5, and some of the signal conductive pillars 330 are along the first The distance between the fifth extension line L5 and the sixth extension line L6 is greater than the distance between the first extension line L1 and the third extension line L3, and is greater than the distance between the second extension line L2 and the fourth extension line L4.

In more detail, please refer to FIG. 4 , the signal conductor 320 of the embodiment includes a first sub-signal lead 321 , a second sub-signal lead 322 and a third sub-signal lead 323 . One end of the first sub-signal wire 321 is connected to one of the first conductive bumps 110. One end of the second sub-signal wire 322 is connected to one of the second conductive bumps 220 and parallel to the first sub-signal wire 321 . The two ends of the third sub-signal wire 323 are respectively connected to the other end of the first sub-signal wire 321 and the other end of the second sub-signal wire 322.

In this embodiment, the third sub-signal conductor 323 is substantially perpendicular to the first sub-signal lead 321 and the second sub-signal lead 322. That is to say, the signal wire 320 of the embodiment has a U-shaped folded structure with double right angles. Similarly, the signal wires 320 connecting the third conductive bumps 130 and the fourth conductive bumps 240 have the same structure and will not be repeated here.

As described above, the semiconductor connection device 300 of the present embodiment can form a signal transmission path for the first semiconductor device 100 and the second semiconductor device 200 and the substrate 400 in a single-layer circuit structure without requiring a complicated multilayer circuit structure. Significantly reduce manufacturing and material costs.

In addition, in the case of the power conduction path, referring to FIG. 2, the power lead 340 is connected in series with the power conductive bumps 150 of the first semiconductor component 100 and disposed adjacent to the power conductive bumps 150. As such, as shown in FIG. 3B, the power supply conductive bumps 150, the power supply wires 340, and the power supply conductive posts 350 form a power transmission path. Similarly, as shown in FIG. 3C, the power supply conductive bump 250, the power supply lead 340, and the power supply conductive post 350 also form another power transfer path.

In general, the current of the power signal is large, and the lower the impedance of the wire, the better, to avoid overheating of the wire. Taking the power conductive bumps 150 as an example, since the power conductive bumps 150 are connected in series by one power supply wire 340, the number of power wires 340 can be reduced. Moreover, the power lead 340 is disposed adjacent to the power conductive bumps 150, and the length of the power lead 340 can also be shortened. In this way, the impedance of the power supply lead 340 can be minimized and the transmission efficiency of the power signal can be improved.

Referring to FIG. 1 again, the package structure 1000 of the embodiment further includes a first sealant 500 and a second sealant 600. The first adhesive 500 is disposed between the first semiconductor component 100 and the semiconductor connection component 300, and between the second semiconductor component 200 and the semiconductor connection component 300. The second sealant 600 is disposed between the semiconductor connection element 300 and the substrate 400.

The first conductive bumps 110, the second conductive bumps 220, the third conductive bumps 130 (not shown in FIG. 1), the fourth conductive bumps 240 (not shown in FIG. 1), the signal wires 320, and The power lead 340 is wrapped in the first sealant 500, and the signal conductive post 330 and the power conductive post 350 are wrapped in the second sealant 600. Therefore, the package structure 1000 can be completely protected.

Second embodiment

Referring to FIG. 5, a top view of a package structure 2000 in accordance with a second embodiment of the present invention is shown. The package structure 2000 of the present embodiment is different from the package structure 1000 of the first embodiment in the arrangement of the power supply wires 340a, and the rest of the same points are not repeated.

As shown in FIG. 5, the semiconductor connection component 300a of the present embodiment includes a plurality of power supply wires 340a, and one of the power supply wires 340a is connected to a power supply conductive bump 150 or a power supply conductive bump 250, and is adjacent to the power supply conductive bump. Block 150 or this power conductive bump 250 is provided. The other end of each power lead 340a is connected to each of the self-conducting conductive posts 350. In this way, the length of each power lead 340a can be minimized so that the impedance of the power supply lead 340a can be minimized.

Third embodiment

Please refer to FIG. 6, which illustrates a top view of a package structure 3000 in accordance with a third embodiment of the present invention. The package structure 3000 of the present embodiment is different from the package structure 2000 of the second embodiment in the number of the first semiconductor elements 100 and the number of the second semiconductor elements 200, and the rest of the same points are not repeated.

As shown in FIG. 6, the package structure 3000 includes a plurality of first semiconductor elements 100 and a plurality of second semiconductor elements 200. The number of the first semiconductor elements 100 and the second semiconductor elements 200 is the same. The first semiconductor element 100 and the second semiconductor elements 200 are in one-to-one correspondence.

When the first semiconductor component 100 and the second semiconductor component 200 are similar, the semiconductor connection component 300b can replicate the totem of the plurality of sets of signal wires 320 and the power supply wires 340a by repeated exposure of a reticle, which is quite convenient.

Fourth embodiment

Referring to FIG. 7, a top view of a package structure 4000 in accordance with a fourth embodiment of the present invention is shown. The package structure 4000 of the present embodiment is different from the package structure 1000 of the first embodiment in the number of the semiconductor elements 700 and the arrangement of the signal wires 820 and the power wires 840, and the rest are not repeated.

As shown in FIG. 7, the package structure 4000 of the present embodiment includes a semiconductor element 700, a semiconductor connection element 800, and a substrate 900. In the present embodiment, the package structure 4000 includes only one semiconductor component 700. The semiconductor component 700 includes at least two signal conductive bumps 710 and a power conductive bump 750. The semiconductor connecting component 800 includes a connecting main board 810, at least two signal conducting posts 830, at least two signal wires 820, at least one power lead 840, and at least one power conducting post 850. The signal conductive post 830 is connected to the main board 810. The signal wires 820 are disposed on the connection main board 810. The two ends of the signal wires 820 are electrically connected to one of the signal conductive bumps 710 and one of the signal conductive posts 830. The substrate 900 is electrically connected to the signal conductive pillar 830.

The length of each of the signal wires 820 (for example, the lengths D41 and D42 of FIG. 7) is substantially equal. Therefore, each of the signal conductive bumps 710 reduces any time difference when transmitting the signal.

In addition, one end of the power lead 840 is connected to the power conductive bump 750 and disposed adjacent to the power conductive bump 750. As a result, the impedance of the power supply line 840 can be reduced to the lowest level and the transmission efficiency of the power signal can be improved.

In addition, the semiconductor connecting component used in the above embodiments of the present invention may also be a Paper Lead Frame. In order to clearly explain the structure of the Paper Lead Frame and the manufacturing method thereof, the following is described with reference to an embodiment: FIG. 8 to FIG. 13 are schematic diagrams showing a manufacturing method of a semiconductor connecting element. First, a carrier 19 is provided, which in this embodiment is a copper piece. A patterned first conductive layer 20' is formed on the carrier 19.

Referring to Fig. 9, above the first conductive layer 20', a photoresist layer 25 is placed thereon, and the photoresist layer 25 is patterned to leave a hole 27'.

Referring to Fig. 10, in the hole 27', a second conductive layer 27 is formed. In the present embodiment, it is formed by electroplating, which is substantially flat and does not protrude from the surface of the photoresist layer 25.

Referring to Fig. 11, the photoresist layer 25 is removed to obtain a patterned first conductive layer 20' and a second conductive layer 27.

Referring to FIG. 12, a first insulating layer 28 is formed by filling a mold with a molding material to embed the patterned first conductive layer 20' and the second conductive layer 27 in the first insulating layer 28. . The molding material used for this first insulating layer 28, which is an epoxy resin in this embodiment, has a characteristic of an elastic modulus of more than 1.0 GPa and a CTE value of less than 10 ppm.

Referring to Figure 13, the carrier 19 is removed by etching to obtain a semiconductor connecting component before packaging.

The package structure disclosed in the above embodiments of the present invention is designed to have a plurality of advantages through the design of the semiconductor connection component. The following only some of the advantages are described as follows: first, first conductive bump, signal conductor, signal conductive pillar and The conductive solder balls form a signal transmission path, and the second conductive bumps, the signal wires, the signal conductive columns and the conductive solder balls also form another signal transmission path. Therefore, the substrate system can simultaneously form a signal communication path with the first semiconductor element and the second semiconductor element.

Second, since the signal conductive pillars are connected to the midpoint of the line segment of the signal conductor, the lengths of the two conductive paths are substantially the same. As a result, signal passing reduces the difference in any delivery time.

The third U-turn structure extends the distance between the midpoint M and the two end points of the line segment of the signal conductor, so that some of the signal conductive pillars are arranged along a fifth extension line, and some of the signal conductive pillars extend along a sixth extension. The line arrangement, the distance between the fifth extension line and the sixth extension line is greater than the distance between the first extension line and the third extension line, and greater than the distance between the second extension line and the fourth extension line.

Fourth, the semiconductor connection element can form a signal transmission path for the first semiconductor element and the second semiconductor element and the substrate in a single-layer circuit structure without requiring a complicated multilayer circuit structure. This significantly reduces manufacturing and material costs.

Fifth, if the power supply conductive bumps are connected in series by a power supply wire, and the power supply wires are disposed adjacent to the power supply conductive bumps, the number of power supply wires can be reduced, and the length of the power supply wires can be shortened. In this way, the impedance of the power supply line can be reduced to the lowest level, and the transmission efficiency of the power signal is improved.

The arrangement of the sixth, first sealant and the second sealant can also completely protect the package structure.

Seventh, if one of the power supply wires is connected to a power supply conductive bump and disposed adjacent to the power supply conductive bump, the length of each power supply wire can be minimized, so that the impedance of the power supply wire can be minimized.

Eighth, the semiconductor connecting component is not only suitable for electrical connection of two semiconductor components, but also suitable for electrical connection of multiple sets of semiconductor components. At this time, the semiconductor connecting component can reproduce the totem of the plurality of sets of signal conducting and power supply wires by repeated exposure of a reticle, which is quite convenient.

Ninth, in the above embodiment, although the two semiconductor elements are electrically connected in a group, the semiconductor connection element may also electrically connect the plurality of semiconductor elements into one group, depending on the needs of the designer.

Tenth, through the signal transmission of the semiconductor connecting component, the minimum pitch of the conductive bumps of the semiconductor component is reduced. In the first embodiment, the minimum spacing between the first conductive bump and the third conductive bump may be less than 100 micrometers (Microns), and the minimum spacing between the second conductive bump and the fourth conductive bump may be less than 100 micrometers. .

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

1000, 2000, 3000. . . Package structure

100. . . First semiconductor component

110. . . First conductive bump

130. . . Third conductive bump

150, 250, 750. . . Power conductive bump

200. . . Second semiconductor component

220. . . Second conductive bump

240. . . Fourth conductive bump

300, 300a, 300b, 800. . . Semiconductor connection element

310, 810. . . Connecting the motherboard

320, 820. . . Signal wire

321. . . First sub-signal wire

322. . . Second sub-signal wire

323. . . Third sub-signal wire

330, 830. . . Signal conductive column

340, 340a, 840. . . Power supply wire

350, 850. . . Power supply conductive column

400, 900. . . Substrate

500. . . First glue

600. . . Second sealant

700. . . Semiconductor component

710. . . Conductive bump

19. . . Carrier

20’. . . First conductive layer

25. . . Photoresist layer

27. . . Second conductive layer

27’. . . Hole

28. . . First insulating layer

D1, D2, D41, D42. . . length

L1. . . First extension line

L2. . . Second extension line

L3. . . Third extension line

L4. . . Fourth extension line

L13, L24. . . Connection

M. . . Midpoint of line segment

1 is a schematic view showing a package structure according to a first embodiment of the present invention;

2 is a plan view showing the package structure of FIG. 1;

3A is a cross-sectional view of the package structure of FIG. 2 taken along section line A-A';

3B is a cross-sectional view of the package structure of FIG. 2 taken along section line B-B';

3C is a cross-sectional view of the package structure of FIG. 2 taken along section line C-C';

4 is a schematic view showing the first conductive bump, the signal wire, the signal conductive pillar, and the second conductive bump of FIG. 2;

5 is a plan view showing a package structure according to a second embodiment of the present invention;

6 is a plan view showing a package structure in accordance with a third embodiment of the present invention;

7 is a plan view showing a package structure in accordance with a fourth embodiment of the present invention;

8 to 13 are schematic views showing a method of manufacturing a semiconductor connecting member.

1000. . . Package structure

100. . . First semiconductor component

110. . . First conductive bump

130. . . Third conductive bump

150, 250. . . Power conductive bump

200. . . Second semiconductor component

220. . . Second conductive bump

240. . . Fourth conductive bump

300. . . Semiconductor connection element

310. . . Connecting the motherboard

320. . . Signal wire

330. . . Signal conductive column

340. . . Power supply wire

350. . . Power supply conductive column

L1. . . First extension line

L2. . . Second extension line

L3. . . Third extension line

L4. . . Fourth extension line

L5. . . Fifth extension line

L6. . . Sixth extension line

L13, L24. . . Connection

M. . . Midpoint of line segment

Claims (31)

A package structure comprising: at least one first semiconductor component having a plurality of first conductive bumps; at least one second semiconductor component having a plurality of second conductive bumps; and a semiconductor connection component (Interposer) for receiving the a first semiconductor component and the second semiconductor component, wherein the semiconductor connector component comprises: a connection main board having a first surface and a second surface; and a plurality of conductive layers disposed in the connection board for Electrically connecting the first surface to the second surface, wherein a first conductive layer is disposed on the first surface and includes a plurality of signal wires, and a second conductive layer is disposed on the second surface and includes a plurality of The first semiconductor element and the second semiconductor element are disposed on the first surface, and the at least one signal wire is connected to a first conductive bump and a second conductive bump; and at least one The signal conducting post is electrically connected to the signal wire; wherein the at least one signal wire comprises two ends and a midpoint of a line segment, and each end of the signal wire is respectively connected to a first conductive bump and a second conductive bump, wherein the signal conductive column is connected to a midpoint of the line segment of the signal wire, and the lengths of the two signal transmission paths from the midpoint of the line segment to the two ends of the signal wire are substantially equal; And a substrate for receiving the semiconductor connecting component, wherein the information A conductive pillar is attached to the substrate. The package structure of claim 1, wherein the first semiconductor component and the second semiconductor component are both memory chips. The package structure of claim 1, wherein the first semiconductor element and the second semiconductor element have the same line structure. The package structure of claim 1, wherein the signal wire has a U-shaped turning structure. The package structure of claim 3, wherein the signal wire comprises: a first sub-signal wire, one end of which is connected to one of the first conductive bumps; and a second sub-signal wire, one end of which is Connecting to the one of the second conductive bumps and parallel to the first sub-signal wire; and a third sub-signal wire, the two ends are respectively connected to the other end of the first sub-signal wire and the second sub- The other end of the signal wire. The package structure of claim 5, wherein the third sub-signal wire is substantially perpendicular to the first sub-signal wire and the second sub-signal wire. The package structure of claim 1, wherein the first conductive bumps are arranged on the first semiconductor component along a first extension line, and the second conductive bumps are along a second The extension lines are arranged on the second semiconductor component, and the first extension line and the second extension line are substantially parallel to each other. The package structure of claim 7, wherein the first semiconductor component further comprises a plurality of third conductive bumps, the second semiconductor component further comprising a plurality of fourth conductive bumps, the third conductive bumps The block is arranged on the first semiconductor element along a third extension line, and the fourth conductive bumps are arranged on the second semiconductor element along a fourth extension line, the first extension line, the first The second extension line, the third extension line, and the fourth extension line are substantially parallel to each other. The package structure of claim 8, wherein the semiconductor connection component comprises a plurality of signal conductive pillars, and the signal conductive pillars are arranged on the semiconductor connection component along a fifth extension line and a sixth extension line. The distance between the fifth extension line and the sixth extension line is greater than the distance between the first extension line and the third extension line, and is greater than the distance between the second extension line and the fourth extension line. The package structure of claim 8, wherein a distance between the first extension line and the third extension line is substantially equal to a distance between the second extension line and the fourth extension line. The package structure of claim 8, wherein the conductive bumps on the first semiconductor component and the second semiconductor component have a minimum pitch of less than 150 micrometers (micron, um). The package structure of claim 1, wherein the signal wire and the signal conductive column are formed by electroplating copper (Cu). The package structure according to claim 1, wherein the substrate is a ceramic substrate, a glass fiber substrate (FR4 Substrate) or a printed circuit board (Printed) Circuit board). The package structure of claim 1, wherein the package structure comprises a plurality of first semiconductor elements and a plurality of second semiconductor elements, and the number of the first semiconductor elements and the second semiconductor elements are the same. The package structure of claim 1, wherein the first semiconductor component further comprises a plurality of power supply conductive bumps, the semiconductor connection component further comprising a power supply lead and a power supply conductive post, the power supply lead is connected in series The power supply conductive bumps are disposed adjacent to the power supply conductive bumps. The package structure of claim 1, wherein the first semiconductor component further comprises a power supply conductive bump, the semiconductor connection component further comprising a power supply wire and a power supply conductive post, one end of the power supply wire is connected to the power supply Conductive bumps are disposed adjacent to the power conductive bumps. The package structure according to claim 1, wherein the material of the connecting main board comprises an insulating mold material. The package structure of claim 17, wherein the insulating mold material is a thermo plastic or an epoxy. The package structure of claim 1, further comprising: a first sealant disposed between the first semiconductor component and the semiconductor connection component, and the second semiconductor component connected to the semiconductor Connected between components. The package structure of claim 19, further comprising: a second sealant disposed between the semiconductor connection component and the substrate. The package structure of claim 1, wherein the semiconductor connection element is a single layer circuit structure. A package structure comprising: a semiconductor component having at least two signal conductive bumps; and a semiconductor connection component (Interposer) for receiving the semiconductor component, wherein the semiconductor connection component comprises: a connection motherboard, having a first one The surface and a second surface comprise an insulating molding material; a plurality of conductive layers are disposed in the connecting main board for electrically connecting the first surface to the second surface, wherein a first conductive layer is disposed On the first surface, and including at least two signal wires, a second conductive layer is disposed on the second surface and includes at least two signal conductive pillars; wherein the semiconductor component is disposed on the first surface and connected to the first surface Each of the signal wires includes two ends, and the two ends of the signal wires are respectively connected to a signal conductive bump and a signal conductive column, wherein the at least two signal wires are substantially equal in length; and a substrate is used for receiving The semiconductor connection component, wherein the signal conductive pillars are connected to the substrate. The package structure of claim 22, wherein the minimum spacing of the signal conductive bumps on the semiconductor component is less than 150 micrometers (micron, um). The package structure of claim 22, wherein the signal wires and the signal conductive posts are formed by electroplating copper (Cu). The package structure of claim 22, wherein the substrate is a ceramic substrate, a glass fiber substrate (FR4 Substrate) or a printed circuit board. The package structure of claim 22, wherein the semiconductor component further comprises at least one power supply conductive bump, the semiconductor connection component further comprising at least one power supply lead and at least one power supply conductive post, one end of the power supply lead is connected to the The power supply conductive bump is disposed adjacent to the power conductive bump. The package structure according to claim 22, wherein the material of the connecting main board comprises an insulating mold material. The package structure of claim 27, wherein the insulating mold material is a thermo plastic or an epoxy. The package structure of claim 22, further comprising: a first sealant disposed between the semiconductor component and the semiconductor connection component. The package structure of claim 29, further comprising: a second sealant disposed between the semiconductor connection component and the substrate. The package structure of claim 22, wherein the semiconductor connection component is a single layer circuit structure.