TWI426379B - System and method for detecting system error of a computer - Google Patents

Description

Computer system error detection system and method

The invention relates to a computer system detection system and method, in particular to a computer system error detection system and method.

At present, a central processing unit (CPU) with integrated North Bridge function appears in a high-end computer system (such as a server), and the functions of memory control and connection are moved from the north bridge to the inside of the CPU. If an error occurs in this type of computer system, such as CPU internal error (Inter Error, IERR) and memory multi-bit error (Multi-Bit Error), the CPU will stop working. However, these two types of system errors are caused by the CPU transmitting information to the external device using the same one of the pins, which will cause the external device to obtain the CPU error signal confusion, and will reduce the server self-monitoring ability, making the user unable to Detailed identification of the root cause of the error increases the difficulty of maintenance.

In view of the above, it is necessary to provide a computer system error detection system and method, and use the substrate management controller to automatically detect whether the error occurred in the computer system is an internal error of the CPU or a complex error of the memory.

The computer system error detection system is installed and operated in a baseboard management controller . The computer system includes a CPU and a memory, and the baseboard management controller is connected to the computer system by a GPIO of the CPU. The computer system error detection system includes: a parameter setting module, configured to set an interrupt flag value, and initialize the interrupt flag value to zero; the signal monitoring module is configured to monitor the computer system during the running process. The CPU uses the GPIO signal output by the GPIO, and detects whether the GPIO signal output by the CPU is converted into a low level signal by a high level signal within a delay time; and the interrupt service module is used when the GPIO signal is high. When the flat signal is converted into a low level signal, the startup interrupt service program triggers an interrupt service to increment the interrupt flag value by one, and detects whether the interrupt flag value is greater than or equal to one after the delay time; the error processing module is used to interrupt The flag value is equal to one time to determine that the system error occurred in the computer system is an internal CPU error, and when the value of the interrupt flag is greater than one, it is determined that the system error occurred in the computer system is a complex bit error of the memory.

In the computer system error detection method, the computer system includes a CPU and a memory, and is connected to the baseboard management controller by a GPIO of the CPU. The method includes the steps of: setting an interrupt flag value, and initializing the interrupt flag value to zero; monitoring the GPIO signal output by the CPU through the GPIO埠 during the running of the computer system; determining whether the GPIO signal output by the CPU is a high level signal; when the GPIO signal output by the CPU is a low level signal, the interrupt service routine is triggered to trigger an interrupt service to increase the value of the interrupt flag by one; and the GPIO signal output by the CPU is detected to be low by a delay time. The flat signal is converted into a high level signal; when the GPIO signal is converted from a low level signal to a high level signal, the start interrupt service program triggers an interrupt service to increment the interrupt flag value; after the delay time, it is determined whether the interrupt flag value is greater than Is equal to one; if the interrupt flag value is equal to one, it is determined that the system error occurred in the computer system is within the CPU Part error; if the interrupt flag value is greater than one, it is determined that the system error occurred in the computer system is a complex bit error of the memory.

Compared with the prior art, the computer system error detection system and method of the present invention can automatically detect whether an error occurred in the computer system is an internal error of the CPU or a complex bit error of the memory. It also prompts the user of the type of error that occurs in the computer system, which in turn allows the user to easily handle errors that occur in the computer system.

1‧‧‧Baseboard Management Controller

10‧‧‧Computer System Error Detection System

101‧‧‧ parameter setting module

102‧‧‧Signal Monitoring Module

103‧‧‧Interrupt Service Module

104‧‧‧Error handling module

11‧‧‧Microprocessor

12‧‧‧ storage unit

2‧‧‧ computer system

20‧‧‧CPU

21‧‧‧ memory

22‧‧‧ display

1 is a block diagram of a preferred embodiment of a computer system error detection system of the present invention.

2 is a flow chart of a preferred embodiment of the computer system error detection method of the present invention.

Figure 3 is a schematic diagram of a GPIO signal output by a CPU of a computer system.

1 is an architectural diagram of a preferred embodiment of the computer system error detection system 10 of the present invention. In this embodiment, the computer system error detection system 10 is installed and runs in a Baseboard Management Controller (BMC) 1 and can be used in a system error of the computer system 2, such as a central processing unit of the computer system 2. (Central Processing Unit, CPU) 20 itself generates an internal error (Inter Error, IERR) or the memory 21 of the computer system 2 generates a multi-bit error (Multi-Bit Error), and detects that the system error is internal to the CPU 20. The error is still a complex bit error of the memory 21. The CPU 20 internal error includes, but is not limited to, a data operation error occurring when the CPU 20 processes the data or a logic control error. The plurality of bit errors of the memory 21 include, but are not limited to, data corruption errors in the memory 21 or bit error dislocations when reading or writing data. error.

The substrate management controller 1 is connected to the computer system 2 by a general purpose input output (GPIO) of the CPU 20. The computer system 2 can be a desktop computer, a notebook computer, a server, or a workstation computer. In the embodiment, the substrate management controller 1 includes, but is not limited to, a microprocessor 11 and a storage unit 12. The computer system 2 includes, but is not limited to, a CPU 20, a memory 21, and a display 22.

The computer system error detection system 10 includes a parameter setting module 101, a signal monitoring module 102, an interrupt service module 103, and an error processing module 104. The module referred to in the present invention is a series of computer programs that can be executed by the microprocessor 11 and can perform a fixed function, and is stored in the storage unit 12 of the substrate management controller 1.

The parameter setting module 101 is configured to set an interrupt flag value (for example, the flag is tag), and initialize the interrupt flag value tag to zero, that is, the interrupt flag value tag=0. The interrupt flag value tag is used to indicate the number of times the microprocessor 11 starts the interrupt service program to trigger the interrupt service. When the microprocessor 11 starts the interrupt service, the interrupt flag value tag is incremented, that is, tag=tag +1 operation.

The signal monitoring module 102 is configured to monitor the GPIO signal output by the CPU 20 through the GPIO 即时 during the operation of the computer system 1 and determine whether the GPIO signal is a high level signal. In the present embodiment, when the computer system 1 is operating normally, the GPIO signal output by the CPU 20 is always a high level signal, which is represented by a binary digit "1", as shown in FIG. 3(a). The CPU 20 itself has an internal error when the computer system 1 is running. In error, the GPIO signal output by the CPU 20 is changed from a high level signal "1" to a low level signal, which is represented by a binary digit "0", and then the GPIO signal is always a low level signal "0", referring to FIG. (b) is shown. When the memory 21 of the computer system 1 is in a complex bit error, the GPIO signal output by the CPU 20 fluctuates between the high and low level signals, that is, the high level signal "1" changes to the low level signal "0. ", then change from the low level signal "0" to the high level signal "1", and then the low level signal "0". Refer to Figure 3(c). When a complex bit error occurs in the memory 21, the GPIO signal generally fluctuates up and down after 18 CPU clock cycles, and then remains a low level signal "0".

The signal monitoring module 102 is further configured to determine whether the GPIO signal output by the CPU 20 is converted from a high level signal to a low level signal within a delay time. In this embodiment, the delay time depends on the operating frequency of the CPU 20. If the operating frequency of the CPU 20 is 1000 Hz, the delay time is 3 seconds.

The interrupt service module 103 is configured to start the interrupt service program to trigger an interrupt service to interrupt the flag value when the GPIO signal is converted from the high level signal "1" to the low level signal "0" during the delay time. Tag plus one, that is, tag=tag+1 operation. The interrupt service module 103 is further configured to detect the interrupt flag value tag after the delay time and determine whether the interrupt flag value tag is equal to one.

The error processing module 104 is configured to determine that the system error occurred in the computer system 1 is an internal error of the CPU 20 when the interrupt flag value tag is equal to one, and determine that the system error occurred in the computer 1 is the memory 21 when the interrupt flag value tag is greater than one. The complex bit error, such as memory 21, occurs with 2, 4, 8, ... 2 ⁿ bit errors, where n is a natural number greater than one. The error processing module 104 is further configured to determine whether the computer system 1 has crashed. When the signal monitoring module 102 does not detect the GPIO signal output by the CPU 20, it indicates that the computer system 1 is dead, the error processing module 104 clears the interrupt flag value tag, and closes or restarts the computer system 1 to the system that occurred. Error handling.

In this embodiment, when a system error occurs in the computer system 1, the error processing module 104 displays a system error (for example, an internal error of the CPU 20 or a complex bit error of the memory 21) in the display 22 of the computer 1 to prompt The type of system error that occurs in the user computer system 1 allows the user to conveniently handle errors occurring in the computer system 1.

2 is a flow chart of a preferred embodiment of the computer system error detection system 10 of the present invention. In this embodiment, the method can detect whether the system error is an internal error of the CPU 20 of the computer system 2 or a complex bit error of the memory 21 when the system error occurs in the computer system 2.

In step S20, the parameter setting module 101 sets an interrupt flag value (for example, the flag is tag), and initializes the interrupt flag value tag to zero, that is, the interrupt flag value tag=0.

In step S21, the signal monitoring module 102 detects the GPIO signal output by the CPU 20 through the GPIO埠 during the running of the computer system 1. When the computer system 1 is operating normally, the GPIO signal is always a high level signal "1", as shown in FIG. 3(a). When the computer system 1 is running, the CPU 20 itself generates an internal error, and the GPIO signal changes from a high level signal "1" to a low level signal "0", and then the GPIO signal is always a low level signal "0". Refer to Figure 3(b). When the computer system 1 is running, the memory 21 has a complex bit error, and the GPIO signal is high level. The number "1" changes to a low level signal "0", and then changes from a low level signal "0" to a high level signal "1". Referring to FIG. 3(c), when a complex bit error occurs in the memory 21, the GPIO signal generally fluctuates up and down after 18 CPU clock cycles, and then remains a low level signal "0".

In step S22, the signal monitoring module 102 determines whether the GPIO signal output by the CPU 20 is a high level signal "1". If the GPIO signal is a high level signal "1", then return to step S21; if the GPIO signal is a low level signal "0", then step S23 is performed.

In step S23, the interrupt service module 103 starts the interrupt service program to trigger an interrupt service to increment the interrupt flag value tag, that is, the tag=tag+1 operation.

In step S24, the signal monitoring module 102 determines whether the GPIO signal is converted from the low level signal “0” to the high level signal “1” within a delay time. In this embodiment, the delay time depends on the operating frequency of the CPU 20. If the operating frequency of the CPU 20 is 1000 Hz, the delay time is 3 seconds.

If the GPIO signal is converted from the low level signal "0" to the high level signal "1" during the delay time, the process returns to step S23. If the GPIO signal does not transition from the low level signal "0" to the high level signal "1" during the delay time, in step S25, the interrupt service module 103 determines whether the interrupt flag value tag is equal to one after the delay time. .

If the interrupt flag value tag is equal to one, in step S26, the error processing module 104 determines that the system error occurred in the computer system 1 is an internal error of the CPU 20; if the interrupt flag value tag is greater than one, in step S27, the error processing module 104 determines The system error that occurred in computer 1 is the complex bit error of memory 21.

In step S28, the error processing module 104 determines whether the computer system 1 has crashed. In this embodiment, when the signal monitoring module 102 does not monitor the GPIO signal output by the CPU 20, the error processing module 104 determines that the computer system 1 has crashed. If the computer system 1 does not crash, the flow returns to step S21, and the signal monitoring module 102 continues to monitor the GPIO signal output by the CPU 20. If the computer system 1 crashes, in step S29, the error processing module 104 clears the interrupt flag value tag, and closes or restarts the computer system 1 to process the system error that occurred.

When a computer system 1 has a system error, the error processing module 104 displays a system error (such as an internal error of the CPU 20 or a complex bit error of the memory 21) in the display 22 of the computer 1 to prompt the user of the computer system. 1 The type of system error that occurs, which in turn allows the user to easily handle errors that occur in computer system 1.

The above is only the preferred embodiment of the present invention, and has been used in a wide range of applications. Any other equivalent changes or modifications that are not departing from the spirit of the present invention should be included in the following patent application. Within the scope.

1‧‧‧Baseboard Management Controller

10‧‧‧Computer System Error Detection System

101‧‧‧ parameter setting module

102‧‧‧Signal Monitoring Module

103‧‧‧Interrupt Service Module

104‧‧‧Error handling module

11‧‧‧Microprocessor

12‧‧‧ storage unit

2‧‧‧ computer system

20‧‧‧CPU

21‧‧‧ memory

22‧‧‧ display

Claims (10)

A computer system error detection system is installed and operated in a baseboard management controller. The computer system includes a CPU and a memory. The baseboard management controller is connected to the computer system by a GPIO of the CPU, and the computer system detects the error. The system includes: a parameter setting module, configured to set an interrupt flag value, and initialize the interrupt flag value to zero; the signal monitoring module is configured to monitor the GPIO output by the CPU through the GPIO埠 during the running of the computer system. a signal, and detecting whether the GPIO signal output by the CPU is converted from a high level signal to a low level signal during a delay time; and an interrupt service module for converting the GPIO signal from a high level signal to a low level signal The startup interrupt service program triggers an interrupt service to increment the interrupt flag value by one, and detects whether the interrupt flag value is greater than or equal to one after the delay time; the error processing module is configured to determine that the computer system occurs when the interrupt flag value is equal to one. The system error is a CPU internal error, and when the interrupt flag value is greater than one, it is determined that the system error occurred in the computer system is the memory Bit error. The computer system error detection system of claim 1, wherein the error processing module is further configured to display the system error on a display of the computer when a system error occurs in the computer system. The computer system error detection system of claim 1, wherein the error processing module is further configured to determine whether a computer system has a crash, and when the computer system crashes, the interrupt flag value is cleared. And shut down or restart the computer system to handle the system error. For example, the computer system error detection system described in claim 1, wherein the GPIO signal output by the CPU is always a high level signal when the computer system is in normal operation, and the GPIO signal output by the CPU is high when an internal error occurs in the CPU. The level signal changes to a low level signal and then remains a low level signal. When a complex bit error occurs in the memory, the GPIO signal output by the CPU fluctuates between a high level signal and a low level signal. The computer system error detection system of claim 1, wherein the delay time depends on the operating frequency of the CPU. A computer system error detection method, the computer system comprising a CPU and a memory, and connected to the baseboard management controller by a GPIO of the CPU, the method comprising the steps of: setting an interrupt flag value, and initializing the interrupt flag value Zero; during the operation of the computer system, the GPIO signal output by the CPU through the GPIO is monitored instantaneously; whether the GPIO signal output by the CPU is a high level signal; when the GPIO signal output by the CPU is a low level signal When the interrupt service routine is started, the interrupt service triggers the interrupt flag value by one; and detects whether the GPIO signal output by the CPU is converted from a low level signal to a high level signal during a delay time; when the GPIO signal is low level When the signal is converted into a high level signal, the interrupt service routine is triggered to trigger an interrupt service to increase the value of the interrupt flag by one; after the delay time, it is determined whether the value of the interrupt flag is greater than or equal to one; if the value of the interrupt flag is equal to one, the computer system is determined. The system error that occurred is a CPU internal error; if the interrupt flag value is greater than one, it is determined that the system error occurred in the computer system is memory The complex bit is wrong. The computer system error detection method of claim 6, wherein the method further comprises the step of: displaying the system error on the display of the computer when a system error occurs in the computer system. The computer system error detection method of claim 6, wherein the method further comprises the steps of: determining whether the computer system has a crash; if the computer system does not crash, continuing to monitor the GPIO signal output by the CPU; If the system crashes, the interrupt flag value is cleared and the computer system is shut down or restarted to process the system error. For example, the computer system error detection method described in claim 6 wherein the GPIO signal output by the CPU is always a high level signal when the computer system is in normal operation, and the GPIO signal output by the CPU is high when an internal error occurs in the CPU. The level signal changes to a low level signal and then remains a low level signal. When a complex bit error occurs in the memory, the GPIO signal output by the CPU fluctuates between a high level signal and a low level signal. The computer system error detection method of claim 6, wherein the delay time depends on the operating frequency of the CPU.