TWI425748B - A control circuit for a power converter - Google Patents

Description

Control circuit of power converter

The invention relates to a power converter, in particular to a control circuit of a power converter.

Nowadays, due to the advancement of science and technology, many electronic products have been developed to meet the needs of the people. The functions of these electronic products are becoming more and more powerful, and bring convenience to the people today. Most of today's electronic devices require a power converter that receives an input power source and outputs an adjusted output power source based on the input power source to provide the power required by the electronic device.

Please refer to FIG. 1 , which is a circuit diagram of a power converter of the prior art. As shown, the conventional power converter includes a transformer T ₁ having a primary side winding N _P and a secondary side winding N _S , and one end of the primary side winding N _P is coupled to an input voltage V _IN , once The other end of the side winding N _P is coupled to a switch Q ₁ , the switch Q _{1 is} coupled to the ground through a resistor R _S , and the resistor R _{S is} used to sense a switching current I _{P of the} switch Q ₁ to generate a current signal. V _CS . One end of the secondary winding N _S of the transformer T ₁ is coupled to one end of a rectifier D _O , and a capacitor C _{O is} coupled between the other end of the rectifier D _{O and} the other end of the secondary winding N _S , the capacitor C _O Also coupled to the output of the power converter, the output of the power converter is used to provide an output voltage V _O .

Referring to FIG. 1 , the control circuit of the conventional power converter includes a sawtooth wave generating circuit 10 , and the sawtooth wave generating circuit 10 includes a charging and discharging circuit including a resistor R _T , a capacitor C _T , a switch 115 , and a A discharge current source 117. One end of the resistor R _T is coupled to a reference voltage V _REF , and the capacitor C _{T is} coupled between the ground terminal and the other end of the resistor R _T , and the reference voltage V _{REF is} used to charge the capacitor C _T . One end of the switch 115 is coupled to the capacitor C _T , the other end of the switch 115 is coupled to one end of the discharge current source 117 , and the other end of the discharge current source 117 is coupled to the ground for discharging the capacitor C _T . The sawtooth wave generating circuit 10 charges and discharges the capacitor C _T by the reference voltage V _REF and the discharge current source 117 to generate the sawtooth wave signal V _SAW .

Referring to FIG. 1, the sawtooth wave generating circuit 10 further includes a first comparator 121, a second comparator 123 and a flip-flop, and the flip-flop includes anti-gates 125 and 127. The first comparator 121 compares the sawtooth wave signal V _SAW with a high threshold signal V _H to generate a first comparison signal. The second comparator 123 compares the sawtooth wave signal V _SAW with a low threshold signal V _L and generates a second comparison signal. The first comparison signal and the second comparison signal are respectively transmitted to the opposite gates 125 and 127 of the flip-flop to generate a pulse signal PLS for controlling the switch 115.

Referring to FIG. 1, the control circuit of the conventional power converter includes, in addition to the sawtooth wave generating circuit 10, comparators 21, 22, anti-gates 32, 34 and a flip-flop 36 for controlling the power supply. The switch Q _{1 of the} converter controls the output voltage V _{O of the} power converter, that is, the output power of the power converter. The sawtooth wave signal V _SAW generated by the sawtooth wave generating circuit 10 is used to control the maximum output power of the power converter. The negative input terminal of the comparator 21 is coupled to the capacitor C _T to receive the sawtooth wave signal V _SAW , and the positive input terminal of the comparator 21 inputs a reference voltage It is compared with the sawtooth wave signal V _SAW to output a control signal MDC. The other comparator 22 is configured to compare the feedback signal V _FB and the current signal V _CS for outputting a protection signal V _ST . The inverse gate 32 is coupled to the outputs of the comparators 21, 22 to receive the control signal MDC and the protection signal V _ST . The set terminal S of the flip-flop 36 is coupled to the output of the inverse OR gate 32, and the reset terminal R of the flip-flop 36 receives the control signal MDC. The inverse gate 34 is used to output a switching signal V _PWM according to the output signal of the output terminal Q of the flip-flop 36 and the control signal MDC, and to control the switch Q ₁ .

Please refer to FIG. 2, which is a schematic diagram of a pulse diagram of a circuit diagram of a conventional power converter. As shown in the figure, the maximum on-time of the switching period of the switching signal V _PWM is determined by the control signal MDC. The conventional control circuit uses the sawtooth wave signal V _SAW generated by the sawtooth wave generating circuit 10 and the reference voltage Compared to generate a control signal the MDC, to control the maximum on-time of the switching signal V _PWM, i.e. the control of the switch Q ₁ is turned on the maximum time, thereby controlling the maximum power output of the power converter. However, when one of the parameters of the high threshold signal V _H , the low threshold signal V _L and the reference voltage level drifts, the pulse width of the control signal MDC will drift, so the switching period of the switching signal V _PWM will drift. In addition, since the sawtooth wave generating circuit 10 is susceptible to interference or other factors, accurate sawtooth wave signal V _SAW cannot be generated, and thus the reference voltage After the comparison, the pulse width of the generated control signal MDC cannot be accurately fixed, so that the maximum on-time of the switching signal V _PWM is affected, so that the maximum on-time of the switch Q ₁ cannot be accurately controlled, and the precise control cannot be accurately controlled. The maximum output power of the power converter.

Therefore, the present invention has been directed to a control circuit for a power converter that solves the above problems, which can improve the above disadvantages, and accurately control the maximum output power of the power converter, and can increase stability to solve the above problem.

The main object of the present invention is to provide a control circuit for a power converter, which generates a control signal with a fixed pulse width by a frequency divider, and precisely controls the maximum on-time of the switch of the power converter to achieve a true control power conversion. The purpose of the maximum output power of the device.

The invention relates to a control circuit for a power converter, wherein the control circuit is configured to output a switching signal to control a switch of a power converter, comprising an oscillator and a frequency divider, wherein the oscillator is used to generate a pulse wave Signal, and providing a pulse signal to the frequency divider, the frequency divider removes the pulse signal to generate a control signal having a fixed pulse width, the switching signal has a switching period, and one of the switching periods is controlled by the maximum conduction time. The fixed pulse width of the control signal. The invention can surely control the maximum on-time of the switching signal by the fixed pulse width of the control signal generated by the frequency divider, and can surely control the maximum output power of the power converter.

For a better understanding and understanding of the technical features of the present invention and the efficacies achieved, please refer to the preferred embodiment and the detailed description, as follows: Please refer to Figure 3, which is A circuit diagram of a power converter in accordance with a preferred embodiment of the present invention. As shown, the power converter according to the present invention comprises a transformer T _1, T ₁ of the transformer to transfer energy from the primary side to the secondary side, one to provide an adjusted output voltage V _O. The primary side and the secondary side of the transformer T ₁ respectively have a primary side winding N _P and a secondary side winding N _S , one end of the primary side winding N _P is coupled to an input voltage V _IN , and the primary side winding N _P is another one end is coupled to a switch Q _1, the switch Q ₁ in series a sensing element, the sensing element in the present embodiment is a resistor R _S, switch Q one end of _a coupling end of the resistor R _S, the other end of the resistor R _S of Coupled to the ground, the resistor R _{S is} used to sense a switching current I _{P of the} switch Q ₁ to generate a current signal V _CS . The above-mentioned switch Q _{1 is} used to control the transformer T ₁ , and a preferred embodiment thereof may be a transistor. One end of the secondary winding N _S of the transformer T ₁ is coupled to one end of a rectifier D _O , and the other end of the rectifier D _{O and} the other end of the secondary winding N _S are coupled to a capacitor C _O , and the capacitor C _{O is} also The output of the power converter is coupled to the output of the power converter to provide an output voltage V _O .

Referring to FIG. 3, the control circuit of the power converter of the present invention includes an oscillator 40 and a frequency divider 50 for generating a control signal MDC for generating a switching signal V _PWM for controlling the power converter. The switch Q ₁ controls the output voltage V _O of the power converter, that is, controls the output power of the power converter. The oscillator 40 is configured to generate a pulse signal PLS, and the frequency divider 50 is coupled to the oscillator 40. The frequency divider signal PLS generates a control signal MDC having a fixed pulse width for generating the switching signal V _PWM . controlling the switching of the switch Q _1, i.e. the control switch is turned on and off of Q _1. The frequency division signal PLS generated by the oscillator 40 is de-frequencyed by the frequency divider 50, so that the control signal MDC having a fixed pulse width can be generated to control the switching of the switching signal V _PWM by the fixed pulse width. a maximum on time period, and surely control switch Q ₁ of the maximum on time, i.e., does the control maximum output power of the power converter. One embodiment of the present invention, in the embodiment, one of the control pilot signal is equal to one of the control-time MDC MDC deadline signal, thus to accurately control the maximum on the switching signal V _PWM on-time is equal to the switching period of the switching signal V _PWM resolution of a cutoff time, i.e., one control switch Q ₁ is equal to the maximum on time of the switch Q ₁ is turned off one time.

Referring to FIG. 3, the control circuit of the power converter of the present invention further includes a protection circuit including a comparator 60 for receiving a feedback signal V _FB and a current signal V _CS for comparing the feedback signal V. _FB and current signal V _CS to output a protection signal V _ST . That the above-described embodiment of the feedback signal VFB, which may be an opto-coupler or by a return to one of _a feedback circuit is coupled to an auxiliary winding of the transformer T (not shown) to detect the power converter output signal VO When the feedback signal VFB is known, since the voltage of the auxiliary winding is related to the output voltage VO of the power converter, the feedback signal VFB is associated with the output voltage VO.

In response to the above, the control circuit of the present invention generates the switching signal V _PWM according to the control signal MDC by a switching circuit. The switching circuit includes a first logic gate 72, a flip-flop 74 and a second logic gate 76. The first logic gate 72 and the second logic gate 76 are inverted or gated in this embodiment. The two input terminals of the inverse gate 72 are respectively coupled to the output end of the comparator 60 and the output terminal of the frequency divider 50 to receive the protection signal V _ST and the control signal MDC to generate a setting signal V _SET . The set terminal S of the flip-flop 74 is coupled to the output of the inverse gate 72 to receive the set signal V _SET , and the reset terminal R of the flip-flop 74 is coupled to the output of the frequency divider 50 to receive the control signal MDC. . The two input terminals of the inverse gate 76 are coupled to the output terminal Q of the flip-flop 74 and the output terminal of the frequency divider 50, and output a switching signal V according to one of the output signals of the flip-flop 74 and the control signal MDC. _PWM . The switching signal V _PWM is used to control the switch Q _{1 of the} power converter to control the output voltage V _{O of the} power converter, that is, to control the output power of the power converter.

Please refer to FIG. 4, which is a circuit diagram of an oscillator and a frequency divider according to a preferred embodiment of the present invention. As shown in the figure, in this embodiment, the frequency divider is a divide-by-four circuit in this embodiment (but not limited thereto, it may also be a divide-by-two circuit), and is composed of two stages of two divided circuits. The control signal MDC is generated according to the pulse signal PLS, and the period of the control signal MDC is an even multiple of the pulse signal PLS. The oscillator 40 includes a charge and discharge circuit and a pulse signal generating circuit. The charge and discharge circuit includes a resistor R _T , a capacitor C _T , a discharge switch 415 and a discharge current source 417 for generating a sawtooth signal V. _SAW . The pulse signal generating circuit comprises a first comparator 421, a second comparator 423 and a flip-flop, the flip-flop includes a reverse gate 425, 427, and the pulse signal generating circuit is used for the sawtooth signal V. _{The SAW} generates a pulse signal PLS. One end of the resistor R _T of the charge and discharge circuit is coupled to a reference voltage V _REF , and the capacitor C _{T is} coupled between the ground terminal and the other end of the resistor R _T , and the reference voltage V _{REF is} used to charge the capacitor C _T . The discharge switch 415 is coupled between the capacitor C _T and one end of the discharge current source 417, and the other end of the discharge current source 417 is coupled to the ground for discharging the capacitor C _T . The charge and discharge circuit charges and discharges the capacitor C _T by the reference voltage V _REF and the discharge current source 417 to generate the sawtooth wave signal V _SAW .

Referring to FIG. 4, the positive input terminal and the negative input terminal of the first comparator 421 of the pulse wave signal generating circuit respectively receive a high threshold signal V _H and a sawtooth wave signal V _SAW to compare the sawtooth wave signal V _SAW with a high threshold. Signal V _H and a first comparison signal is generated at the output. The positive input terminal and the negative input terminal of the second comparator 423 receive the sawtooth wave signal V _SAW and a low threshold signal V _{L respectively} to compare the sawtooth wave signal V _SAW with the low critical signal V _L and generate a second at the output end. Compare signals. The first comparison signal and the second comparison signal are transmitted to the flip-flop to generate the pulse signal PLS. The output ends of the first comparator 421 and the second comparator 423 are respectively coupled to the first input terminals of the first anti-gate 425 and the second anti-gate 427, that is, the first anti-gate 425 and the second anti-gate The first input end of the 427 receives the first comparison signal and the second comparison signal respectively, and the output end of the second anti-gate 427 is coupled to the second input end of the first anti-gate 425, and the output of the first anti-gate 425 The terminal is coupled to the second input of the second anti-gate 427 and generates a pulse signal PLS for controlling the discharge switch 415.

Referring to Fig. 4, the frequency divider 50 includes an inverter 51 and flip-flops 53, 55. The input of the inverter 51 receives the pulse signal PLS to generate an inverted pulse signal/PLS. The flip-flops 53 and 55 are connected in series to generate a control signal MDC having a fixed pulse width in accordance with the pulse signal PLS. The clock input terminal ck of the flip-flop 53 is coupled to the output terminal of the inverter 51 to receive the inverted pulse signal/PLS, and the input terminal D of the flip-flop 53 is coupled to the inverted output terminal of the flip-flop 53. QN, the output terminal Q of the flip-flop 53 is coupled to the clock input terminal ck of the flip-flop 55, and the input terminal D of the flip-flop 55 is coupled to the inverting output terminal QN of the flip-flop 55, and the flip-flop 55 The output terminal Q outputs a control signal MDC. In addition, in a preferred embodiment of the present invention, the oscillator and the frequency divider 50 can be integrated into a control chip, wherein the resistor R _T and the capacitor C _{T of the} oscillator 40 are not disposed in the control chip. Set outside the control chip.

Please refer to FIG. 5, which is a schematic diagram of a pulse diagram of a circuit diagram of a power converter according to a preferred embodiment of the present invention. As shown in the figure, the control signal MDC generated by the frequency divider 50 (see FIG. 3) has a fixed pulse width. In this embodiment, the on-time of the control signal MDC is equal to the cut-off time. The maximum on-time of the switching period of the switching signal V _PWM can be precisely controlled, that is, the maximum on-time of the control switch Q ₁ (please refer to FIG. 3 together), so that the maximum output power of the power converter can be surely controlled. In addition, when the comparator 60 of the protection circuit (please refer to FIG. 3) compares the current signal V _{CS with the} feedback signal V _FB , a low level protection signal V _ST is generated to turn off the switching signal V _PWM .

In summary, the control circuit of the power converter of the present invention is used to generate a switching signal to control the switching of the power converter and control the output power of the power converter. The control circuit includes an oscillator and a frequency divider, and the oscillator is configured to generate a pulse signal and transmit the pulse signal to the frequency divider, and the frequency divider removes the pulse signal to generate a control signal with a fixed pulse width to surely control the switching period of the switching signal. Maximum on-time to precisely control the maximum on-time of the switch. When the temperature or process variation, although the frequency drift, but the pulse cycle after the frequency is absolutely stable, and thus can control the maximum output power of the power converter.

Therefore, the present invention is a novelty, progressive and available for industrial use. It should be in accordance with the requirements of patent applications for patent law in China. It is undoubtedly to file an invention patent application according to law, and the Prayer Council will grant patents as soon as possible.

However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims of the present invention are equally changed. Modifications are intended to be included in the scope of the patent application of the present invention.

10‧‧‧Sawtooth generation circuit

115‧‧‧ switch

117‧‧‧Discharge current source

121‧‧‧First comparator

123‧‧‧Second comparator

125‧‧‧Anti-gate

127‧‧‧Anti-gate

21‧‧‧ Comparator

22‧‧‧ Comparator

32‧‧‧Anti-gate

34‧‧‧Anti-gate

36‧‧‧Factor

40‧‧‧ oscillator

415‧‧‧discharge switch

417‧‧‧Discharge current source

421‧‧‧First comparator

423‧‧‧Second comparator

425‧‧‧Anti-gate

427‧‧‧Anti-gate

50‧‧‧Delephone

51‧‧‧Inverter

53‧‧‧Factor

55‧‧‧Factor

60‧‧‧ comparator

72‧‧‧Anti-gate

74‧‧‧Factor

76‧‧‧Anti-gate

Ck‧‧‧clock input

C _O ‧‧‧ capacitor

C _T ‧‧‧ capacitor

D _O ‧‧‧Rectifier

I _P ‧‧‧Switching current

MDC‧‧‧ control signal

N _P ‧‧‧ primary winding

N _S ‧‧‧secondary winding

PLS‧‧‧ pulse signal

/PLS‧‧‧Reverse pulse signal

Q ₁ ‧‧‧Switch

R _S ‧‧‧resistance

R _T ‧‧‧resistance

T ₁ ‧‧‧Transformer

V _CS ‧‧‧current signal

V _FB ‧‧‧Response signal

V _O ‧‧‧Output voltage

V _PWM ‧‧‧Switching signal

V _REF ‧‧‧reference voltage

V _SAW ‧‧‧Sawtooth Signal

V _ST ‧‧‧protection signal

V _SET ‧‧‧ setting signal

V _H ‧‧‧High threshold signal

V _IN ‧‧‧ input voltage

V _L ‧‧‧ low threshold signal

1 is a circuit diagram of a conventional power converter; FIG. 2 is a schematic diagram of a pulse diagram of a circuit diagram of a conventional power converter; and FIG. 3 is a circuit diagram of a power converter according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 5 is a circuit diagram of a circuit diagram of a power converter according to a preferred embodiment of the present invention; and FIG. 5 is a schematic diagram of a pulse diagram of a circuit diagram of a power converter according to a preferred embodiment of the present invention.

40‧‧‧ oscillator

50‧‧‧Delephone

60‧‧‧ comparator

72‧‧‧Anti-gate

74‧‧‧Factor

76‧‧‧Anti-gate

C _O ‧‧‧ capacitor

D _O ‧‧‧Rectifier

I _P ‧‧‧Switching current

MDC‧‧‧ control signal

N _P ‧‧‧ primary winding

N _S ‧‧‧secondary winding

PLS‧‧‧ pulse signal

Q ₁ ‧‧‧Switch

R _S ‧‧‧resistance

T ₁ ‧‧‧Transformer

V _CS ‧‧‧current signal

V _FB ‧‧‧Response signal

V _IN ‧‧‧ input voltage

V _O ‧‧‧Output voltage

V _PWM ‧‧‧Switching signal

V _ST ‧‧‧protection signal

V _SET ‧‧‧ setting signal

Claims (9)

A control circuit for a power converter, the control circuit outputs a switching signal for controlling a switch of a power converter, comprising: an oscillator for generating a pulse signal; and a frequency divider for dividing the pulse signal Generating a control signal having a fixed pulse width; a switching circuit comprising: a first logic gate generating a setting signal according to the control signal; and a flip-flop generating a signal according to the setting signal and the control signal Outputting a signal; and a second logic gate, generating the switching signal according to the output signal and the control signal to control the switch; wherein the switching signal has a switching period, and one of the switching periods is controlled by a maximum on time The fixed pulse width of the control signal. The control circuit of the power converter of claim 1, wherein the one of the control signals has an on-time equal to one of the control signals. The control circuit of the power converter of claim 1, wherein the maximum on time of the switching signal is equal to one of the switching periods of the switching signal. . The control circuit of the power converter of claim 1, further comprising: a protection circuit for generating a protection signal according to a feedback signal and a current signal, wherein the first logic gate is based on the control signal and the protection The signal generates the setting signal to control the switching signal. The control circuit of the power converter of claim 4, wherein the protection circuit comprises: a comparator that receives the feedback signal and the current signal to generate the protection signal. The control circuit of the power converter of claim 1, wherein the oscillator comprises: a charge and discharge circuit to generate a sawtooth wave signal: A pulse wave signal generating circuit generates the pulse wave signal according to the sawtooth wave signal. The control circuit of the power converter of claim 6, wherein the pulse signal generating circuit comprises: a first comparator receiving a high threshold signal and the sawtooth wave signal to generate a first comparison signal; a second comparator receives a low threshold signal and the sawtooth wave signal to generate a second comparison signal; and a flip flop receives the first comparison signal and the second comparison signal to generate the pulse signal. The control circuit of the power converter of claim 1, wherein the frequency divider comprises: at least one circuit divided by two, connected in series with each other, generating the control signal according to the pulse signal, and the period of the control signal It is an even multiple of the pulse signal. The control circuit of the power converter of claim 1, wherein the oscillator is integrated with the frequency divider as a control chip.