TWI424310B - Cpu power supply circuit and operating method thereof - Google Patents

Description

Central processing unit power supply circuit and operation method thereof

The present invention relates to a power supply circuit, and more particularly to a central processing unit power supply circuit and method of operation thereof.

A typical personal computer, such as a notebook (NB) computer, often uses a multilayer ceramic capacitor (Multi-Layer Ceramic Capacitor, MLCC) in the capacitance (for example, input capacitance) of a central processing unit (CPU) power supply circuit. ) to reduce costs and reduce component area. However, when the operating frequency of the central processing unit power supply circuit falls within the audio range that can be perceived by the human ear, components such as multilayer ceramic capacitors emit audible noise due to the piezoelectric effect. A traditional approach to solving audio noise problems is to use capacitors that are less piezoelectric, such as Polymerized Organic Semiconductor Capacitors (POSCAP) or other electrolytic capacitors, to reduce audio noise caused by changes in CPU load. However, POSCAP has disadvantages such as high cost and large component area.

The invention provides a central processing unit power supply circuit and an operation method thereof, which can effectively suppress audio noise actively.

Embodiments of the present invention provide a central processing unit power supply circuit that is coupled between a power supply and a central processing unit. The power supply circuit includes a voltage conversion circuit, a sampling unit, a setting unit, and a comparator. The voltage conversion circuit includes an input capacitor and an inductor, the input capacitor is connected to the power supply, and the output of the inductor is connected to the central processing unit.

The sampling unit is connected to the input end of the inductor to sample an input signal at the input end of the inductor. The sampling unit converts the input signal to provide a sampled voltage. The setting unit is connected to one of the operation mode control terminals of the voltage conversion circuit. The comparator is connected to the sampling unit and the setting unit. The comparator compares the sampled voltage with a reference voltage. When the sampling voltage is less than the reference voltage, the comparator controls the setting unit such that the voltage conversion circuit enters a continuous conduction mode (CCM).

In an embodiment of the invention, the voltage conversion circuit further includes a regulator, a first power switch, a second power switch, and an output capacitor. The regulator has the above operational mode control terminal. The first power switch is respectively connected to the power supply, the regulator, the input end of the inductor and the sampling unit. The second power switch is connected in series with the first power switch, and is respectively connected to the regulator, the input end of the inductor and the sampling unit. The output capacitor is connected to the output of the inductor and to the central processing unit.

In an embodiment of the invention, the voltage conversion circuit is a multilayer ceramic capacitor, and the input capacitor is respectively connected to the power supply and the first power switch.

In an embodiment of the invention, the regulator has a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM). When the central processing unit is in a low load state, the regulator is in a discontinuous conduction mode, and the sampling voltage is less than the reference voltage. When the regulator enters the continuous conduction mode by the discontinuous conduction mode according to the operation of the setting unit.

In an embodiment of the invention, the sampling unit has a time delay effect.

In one embodiment of the invention, the input signal is a pulse width modulated signal.

In an embodiment of the invention, the sampling unit is configured to convert the input signal into an analog signal.

In one embodiment of the invention, the magnitude of the sampled voltage is proportional to the frequency of the input signal.

Embodiments of the present invention provide a method of operating a power supply circuit for controlling a voltage conversion circuit connected between a power supply and a central processing unit. The voltage conversion circuit includes an inductor, and an output terminal thereof is connected to the central processing unit. The operation method of the power supply circuit includes: sampling an input signal of an input end of the inductor; converting the input signal to a sampling voltage; comparing the sampling voltage with a reference voltage; and if the sampling voltage is less than the reference voltage, causing the voltage conversion circuit to enter a continuous conduction mode (CCM) ).

In one embodiment of the invention, the input signal is a pulse width modulated signal.

In an embodiment of the invention, wherein the step of converting the input signal to the sampling voltage, the magnitude of the sampling voltage is proportional to the frequency of the input signal.

Based on the above, the embodiment of the present invention detects whether the operating frequency of the voltage conversion circuit falls within an audio range that can be perceived by the human ear through the sampling unit and the comparator. When the voltage conversion circuit operates in the non-audio range, the comparator and the setting unit do not change the operation mode of the voltage conversion circuit regardless of the operation mode in which the voltage conversion circuit is currently operating. When the comparator detects that the voltage conversion circuit operates in the audio range, the comparator controls the operation of the setting unit to temporarily force the setting unit to change the operation mode of the voltage conversion circuit to the continuous conduction mode until the operating frequency of the voltage conversion circuit leaves the audio range. . Therefore, the central processing unit power supply circuit disclosed in the embodiment of the present invention can effectively suppress the audio noise actively. In addition, since the sampling unit is a signal that samples the input end of the inductor, it is possible to avoid the driving operation of the interference voltage conversion circuit.

The above described features and advantages of the present invention will be more apparent from the following description.

FIG. 1 is a schematic diagram showing functional blocks of a central processing unit power supply circuit 100 according to an embodiment of the invention. The central processing unit power supply circuit 100 is connected to the power supply 102 and the central processing unit 103. In this embodiment, the power supply 102 can be a power adapter. The power supply 102 can convert the mains 101 (AC voltage source) to the input voltage Vin and then provide the input voltage Vin to the computer system.

In this embodiment, the power supply 102 further includes a conversion circuit for converting into a plurality of sets of DC voltages, which can convert a higher voltage Vin (usually 19V) into a voltage required by each device, for example: 3.3 V and 5V. Therefore, in this embodiment, the conversion circuit is a DC-DC power type conversion. In other embodiments, the input voltage Vin may also be supplied by the battery module, which is not limited by the present invention.

In the computer system, the power supply circuit 100 converts the input voltage Vin to the voltage level required by the central processing unit 103, and then outputs the output voltage Vout to the central processing unit 103 to supply power to the central processing unit 103. In the present embodiment, the power supply circuit 100 includes a voltage conversion circuit 110, a sampling unit 120, a comparator 130, and a setting unit 140.

The voltage conversion circuit 110 is connected to the power supply 102 and the central processing unit 103 to convert the input voltage Vin into an output voltage Vout. The voltage conversion circuit 110 is operable in a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM). When the central processing unit 103 is in a low load state, the voltage conversion circuit 110 is in the discontinuous conduction mode (DCM), and the sampling voltage Vsp is less than the reference voltage Vref, the voltage conversion circuit 110 is in a discontinuous conduction mode according to the operation of the setting unit 140 ( DCM) Forced into continuous conduction mode (CCM).

In the embodiment, the voltage conversion circuit 110 further includes an inductor L, a regulator 111, a first power switch MU, a second power switch MD, an input capacitor Cin, and an output capacitor Cout.

The regulator 111 has an operation mode control terminal CCM#, and the regulator 111 has a discontinuous conduction mode (DCM) and a continuous conduction mode (CCM), which can control the voltage conversion circuit 110 according to the signal of the operation mode control terminal CCM#. Continuous conduction mode or continuous conduction mode. Generally, the signal connection of the operation mode control terminal CCM# receives a control signal from a chipset (such as a south bridge chip or a platform controller hub (PCH), not shown) or the central processing unit 103 to perform DCM and CCM switching. For example, in the present embodiment, the central processing unit 103 transmits the operation mode setting signal Vopm to the regulator 111 via the wafer set, or the central processing unit 103 directly transmits the operation mode setting signal Vopm to the regulator 111. In this embodiment, the operation mode control terminal CCM# is also connected to the setting unit 140, and a detailed description thereof will be described later.

The regulator 111 is connected to the first power switch MU, the second power switch MD, and the setting unit 140, respectively. The first power switch MU is connected to the power supply 102, the regulator 111, the input of the inductor L, the sampling unit 120, and the input capacitor Cin. The second power switch MD is connected in series with the first power switch MU, and the second power switch MD is connected to the regulator 111, the input end of the inductor L and the sampling unit 120, respectively. The input capacitor Cin is connected to the first power switch MU and the power supply 102, respectively. The input ends of the inductors L are respectively connected to the first power switch MU, the second power switch MD and the sampling unit 120. The output of the inductor L is connected to the central processing unit 103 to supply the output voltage Vout. The output capacitor Cout is connected to the output of the inductor L and the central processing unit 103.

In this embodiment, the input capacitor Cin is a multilayer ceramic capacitor (MLCC), and the output capacitor Cout is a polymer organic semiconductor solid electrolytic capacitor (POSCAP).

The sampling unit 120 is connected to the input end of the inductor L, the first power switch MU, and the second power switch MD to sample the input signal of the input end of the inductor L. The sampling unit 120 converts the input signal VL at the input of the inductor L to provide the sampling voltage Vsp to the comparator 130. The comparator 130 is connected to the sampling unit 120 and the setting unit 140, respectively. The setting unit 140 is connected to the operation mode control terminal CCM# of the comparator 130 and the regulator 111, respectively.

The setting unit 140 is connected to the operation mode control terminal CCM# of the voltage conversion circuit 110, that is, the operation mode control terminal CCM# of the regulator 111. This operation mode control terminal CCM# can control the operation mode of the voltage conversion circuit 110. For example, when the operation mode control terminal CCM# is at the first logic level, the operation mode of the voltage conversion circuit 110 is a discontinuous conduction mode (DCM). When the operation mode control terminal CCM# is at the second logic level, the operation mode of the voltage conversion circuit 110 is the continuous conduction mode (CCM).

For another example, when the operation mode control terminal is at the first logic level, the operation mode of the voltage conversion circuit 110 is a pulse frequency modulation (PFM) mode, and when the operation mode control terminal is the second logic level, The operation mode of the voltage conversion circuit 110 is a pulse width modulation (PWM) mode. For example, when the operation mode control terminal is at the first logic level, the operation mode of the voltage conversion circuit 110 is “auto mode” (for example, dynamically selecting the operation mode in the PFM mode or the PWM mode according to the load), and when When the operation mode control terminal is at a high logic level, the operation mode of the voltage conversion circuit 110 is limited to the PWM mode.

The sampling unit 120 samples the input signal VL at the input of the inductor L to provide a sampling voltage Vsp. In the present embodiment, the input signal VL is a pulse width modulation (PWM) signal of a digital type. The sampling unit 120 can convert the input digital type signal into an analog signal. In the present embodiment, the RC delay circuit (resistive capacitance delay circuit) may be included in the sampling unit 120 to have a time delay effect to prevent the sampling signal from switching the operation mode of the voltage conversion circuit 110 too frequently.

The level of the sampling voltage Vsp is a pulse frequency corresponding to the signal VL, that is, corresponding to the operating frequency of the voltage conversion circuit 110, that is, the magnitude of the sampling voltage Vsp is proportional to the frequency of the input signal VL.

When the voltage conversion circuit operates in discontinuous conduction mode (DCM), the operating frequency is proportional to the magnitude of the load current. The constant load current is always lowered from high, and the operating frequency is always lowered from high, so the sampling voltage Vsp is also lowered from high.

Therefore, in the discontinuous conduction mode (DCM), the power conversion circuit 110 causes the operating frequency to enter the audio range (20 Hz to 20 KHz) due to the change of the load, and the sampling voltage Vsp falls correspondingly into a certain voltage range (below). Similarly, the first voltage range is referred to; similarly, when the voltage conversion circuit 110 operates in a non-audio range (eg, several hundred KHz), the sampling voltage Vsp will correspondingly fall into another voltage range (hereinafter referred to as a second voltage range). Therefore, a reference voltage level can be selected between the aforementioned first voltage range and the second voltage range, and the reference voltage Vref can be set accordingly with reference to the voltage level.

In other embodiments, the sampling unit 120 can be implemented with a counter and a digital analog converter. The counter is connected to the input of the inductor L to count the number of pulses of the signal VL in unit time, and then outputs the result to the digital analog converter. The digital analog converter converts the count result output by the counter into an analog sampling voltage Vsp, and then outputs the sampling voltage Vsp to the comparator 130.

The comparator 130 receives the sampling voltage Vsp and the control setting unit 140. When the sampling voltage Vsp is less than the reference voltage Vref, the comparator 130 controls the operation of the setting unit 140 to force the voltage conversion circuit 110 to enter the continuous conduction mode (CCM).

In general, if the input capacitance Cin is a multilayer ceramic capacitor (MLCC), there is a noise problem in operating the voltage conversion circuit 110 in the discontinuous conduction mode (DCM), but the power conversion efficiency is high. If the voltage conversion circuit 110 is operated in the continuous conduction mode (CCM), there is no noise problem, but the power conversion efficiency is low.

Therefore, when the comparator 130 detects that the voltage conversion circuit 110 is operating in the non-audio range, the comparator 130 controls the operation of the setting unit 140 so that the operation mode of the voltage conversion circuit 110 is as DCM as possible. When the comparator 130 detects that the voltage conversion circuit 110 is operating in the audio range, the comparator 130 controls the operation of the setting unit 140 to cause the setting unit 140 to change the operation mode of the voltage conversion circuit 110 to CCM until the operating frequency of the voltage conversion circuit 110 leaves. Audio range.

Therefore, the present embodiment can operate the voltage conversion circuit 110 in the DCM while using a lower cost multilayer ceramic capacitor (MLCC) as the input capacitance Cin. That is to say, the present embodiment can reduce the audio noise without sacrificing the power conversion efficiency. Since the voltage conversion circuit 110 can not use POSCAP and electrolytic capacitors, this embodiment can enjoy the cost and space benefits brought by the MLCC.

In another embodiment, when the comparator 130 detects that the voltage conversion circuit 110 is operating in the non-audio range, the comparator 130 controls the operation of the setting unit 140 such that the operation mode of the voltage conversion circuit 110 is "automatic mode". This automatic mode causes the voltage conversion circuit 110 to automatically select to operate in a pulse frequency modulation (PFM) mode or a pulse width modulation (PWM) mode depending on the load. In general, the operating frequency of the PWM mode is much higher than the audio range that the human ear can feel. Therefore, when the comparator 130 detects that the voltage conversion circuit 110 is operating in the audio range, the comparator 130 controls the operation of the setting unit 140 to cause the setting unit 140 to change the operation mode of the voltage conversion circuit 110 to the PWM mode until the voltage conversion circuit 110 The operating frequency leaves the audio range.

The regulator 111 has at least a first mode of operation and a second mode of operation. The setting unit 140 can change the logic level of the mode control terminal CCM# of the regulator 111 according to the sampling voltage Vsp, thereby changing the operation mode of the regulator 111 to the first operation mode or the second operation mode. In some embodiments, the aforementioned first mode of operation may be a pulse width modulation mode and the second mode of operation may be a pulse frequency modulation mode. In other embodiments, the aforementioned first mode of operation may be a continuous conduction mode and the second mode of operation may be a discontinuous conduction mode.

In some embodiments, the operation mode control terminal of the voltage conversion circuit 110 (the mode control terminal CCM# of the regulator 111) is also connected to the central processing unit 103 via the setting unit 140 to receive the operation mode setting signal Vopm. In other embodiments, the operation mode control end of the voltage conversion circuit 110 (the mode control terminal CCM# of the regulator 111) is also connected to the chip set via the setting unit 140 (for example, a south bridge wafer or a platform control unit (PCH), not shown The central processing unit 103 can transmit the operation mode setting signal Vopm to the voltage conversion circuit 110 via the wafer set. When the voltage conversion circuit 110 operates in the non-audio range, the voltage conversion circuit 110 can dynamically determine the operation mode according to the operation mode setting signal Vopm outputted by the central processing unit 103 or the chipset. When the voltage conversion circuit 110 operates in the audio range, the setting unit 140 forces the operation mode of the voltage conversion circuit 110 to be changed to CCM (or PWM mode) until the operating frequency of the voltage conversion circuit 110 leaves the audio range.

2 is a circuit diagram showing the central processing unit power supply circuit 100 of FIG. 1 in accordance with an embodiment of the present invention. The sampling unit 120 includes a first resistor R1 and a sampling capacitor Csp. The first end of the first resistor R1 is connected to the input end of the inductor L, and the second end of the first resistor R1 is connected to the comparator 130 to provide the sampling voltage Vsp. The first end of the sampling capacitor Csp is connected to the second end of the first resistor R1, and the second end of the sampling capacitor Csp is grounded.

In the embodiment shown in FIG. 2, comparator 130 includes an operational amplifier OP. A first input (eg, an inverting input) of the operational amplifier OP is coupled to the output of the sampling unit 120 (the second end of the first resistor R1) to receive the sampled voltage Vsp. A second input (eg, a non-inverting input) of the operational amplifier OP is coupled to the reference voltage Vref. The output terminal of the operational amplifier OP is connected to the setting unit 140.

In the embodiment shown in FIG. 2, the setting unit 140 includes a second resistor R2 and a mode switch SW. The first end of the second resistor R2 is connected to the first voltage, and the second end of the second resistor R2 is connected to the operation mode control end of the voltage conversion circuit 110 (the mode control terminal CCM# of the regulator 111). The first end of the mode switch SW is connected to the second end of the second resistor R2. The second end of the mode switch SW is connected to the second voltage. The control terminal of the mode switch SW is connected to the output terminal of the comparator 130 (the output terminal of the operational amplifier OP). In the embodiment shown in FIG. 2, the first voltage and the second voltage are respectively a system voltage VCC and a ground voltage. In other embodiments, the first voltage can be a ground voltage and the second voltage can be a system voltage VCC. In the embodiment shown in FIG. 2, the front stage component (e.g., central processing unit 103 or chipset) can supply the operating mode setting signal Vopm in an open drain manner.

3 is a timing diagram showing the timing of the circuit of FIG. 2 in accordance with an embodiment of the present invention. Referring to FIG. 2 and FIG. 3, the voltage conversion circuit 110 can dynamically determine the operation mode according to the operation mode setting signal Vopm outputted by the central processing unit 103 or the chipset. When the central processing unit 103 is heavily loaded, the voltage conversion circuit 110 operates in a PWM mode, at which time the operating frequency of the voltage conversion circuit 110 is fixed at a certain frequency (higher than the audio range).

When the central processing unit 103 is lightly loaded, the voltage conversion circuit 110 operates in the PFM mode, that is, dynamically adjusts the operating frequency with the load state. Therefore, in the PFM mode, the operating frequency of the voltage conversion circuit 110 may operate in the audio range with the load state. When the voltage conversion circuit 110 operates in the non-audio range, the sampling voltage Vsp is higher than the reference voltage Vref, so that the control voltage VC output from the operational amplifier OP is at a logic low level, so the mode switch SW is in an off state. When the voltage conversion circuit 110 operates in the audio range, the sampling voltage Vsp may be lower than or equal to the reference voltage Vref such that the control voltage VC output by the operational amplifier OP is at a logic high level, so the mode switch SW is in an on state. At this time, the setting unit 140 pulls down the potential of the operation mode control terminal (the mode control terminal CCM# of the regulator 111) of the voltage conversion circuit 110 to a logic low level to forcibly change the operation mode of the voltage conversion circuit 110 to the PWM mode. . Therefore, the central processing unit power supply circuit 100 disclosed in the embodiment of the present invention can effectively suppress audio noise actively.

For another example, when the central processing unit 103 is in a low load state, the regulator 111 is in the discontinuous conduction mode (DCM), and the sampling voltage Vsp is less than the reference voltage Vref, the regulator 111 is discontinuously turned on according to the operation of the setting unit 140. The mode (DCM) enters continuous conduction mode (CCM). Therefore, the power supply circuit 100 disclosed in the embodiment of the present invention can effectively suppress the audio noise actively.

4 is a circuit diagram showing the central processing unit power supply circuit 100 of FIG. 1 in accordance with another embodiment of the present invention. For details of FIG. 4, reference may be made to the related description of FIGS. 1 and 2. 4 is different from the place of FIG. 2 in the embodiment of the setting unit 140 of FIG. It is assumed here that the pre-stage element (for example, the central processing unit 103 or the chip set) supplies the operation mode setting signal Vopm in a push-pull manner. In order to prevent the operation of the setting unit 140 from colliding with the operation mode setting signal Vopm supplied from the pre-stage element, the first end of the second resistor R2 receives the operation mode setting signal Vopm as shown in FIG. When the voltage conversion circuit 110 operates in the audio range, the control voltage VC output from the operational amplifier OP is at a logic high level and the mode switch SW is in an on state, so the setting unit 140 will control the operation mode of the voltage conversion circuit 110 (adjustment) The potential of the mode control terminal CCM#) of the device 111 is pulled down to a logic low level to force the operating mode of the voltage conversion circuit 110 to be changed to CCM (or PWM mode) until the operating frequency of the voltage conversion circuit 110 leaves the audio range.

The above embodiment can be used to add a hysteresis effect to the comparator 130, or to add an RC delay effect to the setting unit 140 to adjust the sensitivity of the action while taking into account the energy saving benefits of the DCM and the human ear. For example, FIG. 5 is a circuit diagram illustrating a central processing unit power supply circuit 100 of FIG. 1 in accordance with yet another embodiment of the present invention. For details of FIG. 5, reference may be made to the related description of FIGS. 1, 2, and 4. Figure 5 differs from that of Figure 4 in the embodiment of the setting unit 140 of Figure 5. The setting unit 140 shown in FIG. 5 includes a second resistor R2, a mode switch SW, a third resistor R3, a diode D1, and a delay capacitor Cd. The first end of the second resistor R2 receives the operation mode setting signal Vopm, and the second end of the second resistor R2 is connected to the operation mode control terminal of the voltage conversion circuit 110 (the mode control terminal CCM# of the regulator 111). The first end of the mode switch SW is connected to the second end of the second resistor R2, and the second end of the mode switch SW is connected to the second voltage (for example, the ground voltage. The first end of the third resistor R3 is connected to the output end of the comparator 130 for receiving The second end of the third resistor R3 is connected to the control end of the mode switch. The anode of the diode D1 is connected to the first end of the third resistor R3, and the cathode of the diode D1 is connected to the second end of the third resistor R3. The delay capacitor Cd is connected to the second end of the third resistor R3. The third resistor R3, the diode D1 and the delay capacitor Cd are added to the setting unit 140, so that the mode switch SW is turned on quickly, and the delay is cut off. Turn off, so that the voltage conversion circuit 110 does not switch back and forth between the PWM mode and the PFM mode.

FIG. 6 is a flow chart showing the operation method of the power supply circuit 100 according to an embodiment of the invention. This method of operation can control the voltage conversion circuit 110 connected between the power supply 102 and the central processing unit 103. First, the sampling unit 120 proceeds to step S610 to sample the input signal VL of the voltage conversion circuit 110 connected to the input terminal of the inductance L of the central processing unit 103. Next, the sampling unit 120 proceeds to step S620 to convert the input signal VL to the sampling voltage Vsp. Then, the comparator 130 proceeds to step S630 to compare the sampling voltage Vsp with the reference voltage Vref. If the sampling voltage Vsp is smaller than the reference voltage Vref, the comparator 130 controls the voltage conversion circuit 110 through the setting unit 140 so that the voltage conversion circuit 110 enters the continuous conduction mode (step S640). If the sampling voltage Vsp is greater than or equal to the reference voltage Vref, the comparator 130 controls the voltage conversion circuit 110 through the setting unit 140 such that the voltage conversion circuit 110 enters the discontinuous conduction mode (step S650).

In summary, the central processing unit power supply circuit 100 disclosed in the embodiment of the present invention is in the main circuit of the voltage conversion circuit 110, and the switching signal VL of the inductor L on the input side is extracted and converted into the analog signal Vsp. The comparator 130 detects whether the voltage conversion circuit 110 is operating in the audio range, and then introduces the corresponding control signal VC into the operation mode control terminal of the voltage conversion circuit 110, so that the voltage conversion circuit 110 leaves the audio operation range, and the audio noise can be suppressed. . The above embodiment utilizes the operating frequency of the voltage conversion circuit 110 as a feature for identifying whether or not there is noise, and once confirmed, actively changes the operation mode of the voltage conversion circuit 110.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Power supply circuit

101. . . Mains

102. . . Power Supplier

103. . . Central processing unit

110. . . Voltage conversion circuit

111. . . Regulator

120. . . Sampling unit

130. . . Comparators

140. . . Setting unit

Cd. . . Delay capacitor

Cin. . . Input capacitance

Cout. . . Output capacitor

Csp. . . Sampling capacitor

D1. . . Dipole

L. . . inductance

MU. . . First power switch

MD. . . Second power switch

OP. . . Operational Amplifier

R1. . . First resistance

R2. . . Second resistance

R3. . . Third resistance

S610~S650. . . step

SW. . . Mode switch

VC. . . Control voltage

Vin. . . Input voltage

VL. . . Signal at the input of the inductor

Vopm. . . Operating mode setting signal

Vout. . . The output voltage

Vref. . . Reference voltage

Vsp. . . Sampling voltage

1 is a schematic diagram showing functional blocks of a central processing unit (CPU) power supply circuit according to an embodiment of the invention.

2 is a schematic diagram showing the power supply circuit of the central processing unit of FIG. 1 according to an embodiment of the invention.

3 is a timing diagram showing the timing of the circuit of FIG. 2 in accordance with an embodiment of the present invention.

4 is a schematic diagram showing the power supply circuit of the central processing unit of FIG. 1 according to another embodiment of the present invention.

FIG. 5 is a schematic diagram showing the power supply circuit of the central processing unit of FIG. 1 according to still another embodiment of the present invention.

FIG. 6 is a flow chart showing an operation method of a power supply circuit according to an embodiment of the invention.

100. . . Power supply circuit

101. . . Mains

102. . . Power Supplier

103. . . Central processing unit

110. . . Voltage conversion circuit

111. . . Regulator

120. . . Sampling unit

130. . . Comparators

140. . . Setting unit

Cin. . . Input capacitance

Cout. . . Output capacitor

L. . . inductance

MU. . . First power switch

MD. . . Second power switch

R2. . . Second resistance

SW. . . Mode switch

VC. . . Control voltage

Vin. . . Input voltage

VL. . . Signal at the input of the inductor

Vopm. . . Operating mode setting signal

Vout. . . The output voltage

Vsp. . . Sampling voltage

Claims (11)

A central processing unit power supply circuit is connected to a power supply and a central processing unit, comprising: a voltage conversion circuit comprising an input capacitor and an inductor, the input capacitor being connected to the power supply, an output of the inductor Connecting the central processing unit; a sampling unit, connecting an input end of the inductor to sample an input signal of the input end of the inductor, and converting the input signal to provide a sampling voltage; and a setting unit connecting the voltage conversion One of the circuit operates the mode control terminal; and a comparator that connects the sampling unit to the setting unit, the comparator compares the sampling voltage with a reference voltage, and when the sampling voltage is less than the reference voltage, the comparator controls the setting The unit causes the voltage conversion circuit to enter a continuous conduction mode. The power supply circuit of claim 1, wherein the voltage conversion circuit further comprises: a regulator having the operation mode control end; a first power switch connected to the power supply, the regulator, The input end of the inductor and the sampling unit; a second power switch connected in series with the first power switch, and respectively connected to the regulator, the input end of the inductor and the sampling unit; and an output capacitor, connected The output of the inductor is coupled to the central processing unit. The power supply circuit of claim 2, wherein the input capacitor is a multilayer ceramic capacitor, and the input capacitor is respectively connected to the power supply and the first power switch. The power supply circuit of claim 2, wherein the regulator has a discontinuous conduction mode and the continuous conduction mode, and when the central processing unit is in a low load state, the regulator is in the discontinuous conduction mode, And when the sampling voltage is less than the reference voltage, the regulator enters the continuous conduction mode by the discontinuous conduction mode according to the operation of the setting unit. The power supply circuit of claim 1, wherein the sampling unit has a time delay effect. The power supply circuit of claim 1, wherein the input signal is a pulse width modulation signal. The power supply circuit of claim 1, wherein the sampling unit is configured to convert the input signal into an analog signal. The power supply circuit of claim 1, wherein the magnitude of the sampling voltage is proportional to a frequency of the input signal. A method for operating a power supply circuit for controlling a voltage conversion circuit connected between a power supply and a central processing unit, the voltage conversion circuit including an inductor, and one output of the inductor is connected to the central processing unit The operating method includes: sampling an input signal at one input end of the inductor; converting the input signal to a sampling voltage; comparing the sampling voltage with a reference voltage; and if the sampling voltage is less than the reference voltage, causing the voltage conversion circuit Enter a continuous conduction mode. The method of operation of claim 9, wherein the input signal is a pulse width modulation signal. The operating method of claim 9, wherein in the step of converting the input signal to the sampling voltage, the magnitude of the sampling voltage is proportional to the frequency of the input signal.