TWI423449B - Oxide semiconductor thin film transistor and manufacturing method thereof - Google Patents

Description

Oxide semiconductor thin film transistor and manufacturing method thereof

The present invention relates to an oxide semiconductor thin film transistor and a method of fabricating the same, and more particularly to an oxide semiconductor thin film transistor having low contact resistance and high electron mobility between an oxide semiconductor layer and a source/drain electrode. And its manufacturing method.

A thin film transistor (TFT) is a semiconductor component widely used in display technology, for example, in a liquid crystal display panel (LCD), an organic light emitting diode display panel (OLED). ) and electronic paper (E-paper) and other display products. The switching of voltage or current is provided by the thin film transistor, so that the pixels in each display exhibit bright, dark and gray scale display effects. The electron mobility of the thin film transistor is an important index characteristic when the thin film transistor is used in a display. The electron mobility directly affects the switching speed of the thin film transistor, which in turn has a great influence on the display quality of the display.

For example, the specifications of the previous conventional TV video signals and the frequency of replacement are VGA (640 x 480 pixels) and 60 Hz, while the current specifications of digital TVs have improved to full HD (1920 x 1080 paintings). And 120Hz, followed by 4K2K (3840 x 2160 pixels) and 240Hz specifications, which is higher resolution and shorter picture update frequency to continuously improve the picture quality of the display. However, as the resolution of the screen and the frequency of replacement are increased, the response rate to each single pixel requirement in the display will become more stringent. Therefore, when the electron mobility of the thin film transistor used in each pixel cannot be as fast as the response rate is required, the display screen is abnormal.

Currently, thin film transistors used in the display industry can be distinguished according to the semiconductor layer materials used, including amorphous silicon TFTs (a-Si TFTs), polysilicon TFTs, and oxide semiconductors. Thin film transistor (oxide semiconductor TFT). Among them, amorphous germanium thin film transistors are still the mainstream in the display industry due to their mature process technology and high yield. However, the amorphous germanium thin film transistor is affected by the properties of the amorphous germanium semiconductor material, so that the electron mobility cannot be improved greatly and effectively by the adjustment of the process or component design (currently the electron mobility of the amorphous germanium thin film transistor) It is generally within 1 cm ² /Vs), so it cannot meet the needs of higher-profile displays that are currently visible in the future. Polycrystalline germanium thin film transistors benefit from the properties of polycrystalline germanium materials, and have a significant improvement in electron mobility (the electron mobility of polycrystalline germanium thin film transistors is generally optimal up to 100 cm ² /Vs). However, due to the complicated process of the polycrystalline germanium film transistor (relatively costly improvement) and the crystallization process in the large-size panel application, the problem of poor uniformity of crystallinity exists, so the polycrystalline germanium thin film transistor is still applied to the small-sized panel. Mainly. The oxide semiconductor thin film transistor is a newly emerging oxide semiconductor material which has been widely used in recent years. Such a material is generally an amorphous structure, and is not applied to the problem of poor uniformity on a large-sized panel, and can be utilized. Film formation in a variety of ways, such as sputtering, spin-on, and inkjet printing. Therefore, the process is even more flexible than the amorphous germanium film transistor. The electron mobility of the oxide semiconductor thin film transistor is generally 10 times higher than that of the amorphous germanium thin film transistor (the electron mobility of the oxide semiconductor thin film transistor is generally between 10 cm ² /Vs and 50 cm ² /Vs). ), to the extent that the demand for future high-profile displays is currently available.

However, in the structure of the oxide semiconductor thin film transistor, if the contact impedance between the source electrode/drain electrode and the oxide semiconductor layer is too large, the performance of the thin film transistor is lowered and the high electron mobility cannot be effectively exerted. characteristic. Therefore, it is necessary to reduce the contact resistance between the oxide semiconductor layer and the source/drain electrodes so that the oxide semiconductor thin film transistor exhibits characteristics of high electron mobility.

One of the main objects of the present invention is to provide an oxide semiconductor thin film transistor and a method of fabricating the same, which can reduce the contact resistance between the oxide semiconductor layer and the source/drain electrodes to improve electron mobility.

A preferred embodiment of the present invention provides an oxide semiconductor thin film transistor. The oxide semiconductor thin film transistor includes a substrate, a gate electrode, a source electrode and a drain electrode, a gate dielectric layer, a patterned oxide semiconductor layer, and a patterned hydrogen-containing material layer. The gate electrode, the source electrode and the drain electrode are disposed on the substrate, and the source electrode and the drain electrode respectively have an upper surface and a side surface. The gate dielectric layer is disposed between the gate electrode and the source electrode/drain electrode. The patterned oxide semiconductor layer is disposed on the substrate, wherein the patterned oxide semiconductor layer has a channel region and a non-channel region, the non-channel region at least partially covering the upper surface and the side surface of the source electrode and at least partially covering the drain The upper surface and the side surface of the electrode, and the channel region is located above the substrate between the source electrode and the drain electrode. The patterned hydrogen-containing material layer is disposed on the patterned oxide semiconductor layer, wherein the patterned hydrogen-containing material layer covers at least a portion of the non-channel region of the patterned oxide semiconductor layer, and is covered by the patterned hydrogen-containing material layer The resistivity of the patterned oxide semiconductor layer is less than the resistivity of the patterned oxide semiconductor layer not covered by the patterned hydrogen-containing material layer.

Another preferred embodiment of the present invention provides a method of fabricating an oxide semiconductor thin film transistor, comprising the following steps. First, a substrate is provided. Next, a gate electrode is formed on the substrate. Then, a gate dielectric layer is formed on the substrate and the gate electrode. Subsequently, a source electrode and a drain electrode are formed on the gate dielectric layer, wherein the source electrode and the drain electrode respectively have an upper surface and a side surface. Next, a patterned oxide semiconductor layer is formed on the source electrode, the drain electrode and the gate dielectric layer, wherein the patterned oxide semiconductor layer has a channel region and a non-channel region, and the non-channel region is at least partially covered One of the source electrode has an upper surface and a side surface and at least partially covers an upper surface and a side surface of the drain electrode, and the channel region is located on the gate dielectric layer between the source electrode and the drain electrode. Furthermore, a patterned hydrogen-containing material layer is formed on the patterned oxide semiconductor layer, wherein the patterned hydrogen-containing material layer covers at least a portion of the non-channel region of the patterned oxide semiconductor layer. Then, an annealing process is performed to drive the hydrogen of the patterned hydrogen-containing material layer into the patterned oxide semiconductor layer such that the resistivity of the patterned oxide semiconductor layer covered by the patterned hydrogen-containing material layer Reducing and less than the resistivity of the patterned oxide semiconductor layer not covered by the patterned hydrogen-containing material layer.

The invention utilizes a partially patterned hydrogen-containing material layer on the patterned oxide semiconductor layer, and an annealing process is used to reduce the resistivity of the patterned oxide semiconductor layer covered by the patterned hydrogen-containing material layer, thereby achieving a reduction The contact resistance between the oxide semiconductor layer and the source/drain electrodes improves the electron mobility thereof.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figure 1. FIG. 1 is a schematic view showing an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention. As shown in Fig. 1, the oxide semiconductor thin film transistor 20 is a bottom gate-gate film (Bottom-Gate TFT) structure. The oxide semiconductor thin film transistor 20 includes a substrate 10, a gate electrode 11, a source electrode 13A and a drain electrode 13B, a gate dielectric layer 12, a patterned oxide semiconductor layer 14, and a pattern. The hydrogen containing material layer 15 is formed. As shown in FIG. 1, the gate electrode 11 is disposed on the substrate 10, the gate dielectric layer 12 is disposed on the substrate 10 and the gate electrode 11, and the source electrode 13A and the drain electrode 13B are disposed on the gate. Above the dielectric layer 12, the source electrode 13A has an upper surface 13A1 and a side surface 13A2, and the drain electrode 13B has an upper surface 13B1 and a side surface 13B2. The patterned oxide semiconductor layer 14 is disposed on the source electrode 13A, the drain electrode 13B, and the gate dielectric layer 12, wherein the patterned oxide semiconductor layer 14 has a channel region 14C and a non-channel region 14D, The channel region 14D at least partially covers the upper surface 13A1 and the side surface 13A2 of the source electrode 13A and at least partially covers the upper surface 13B1 and the side surface 13B2 of the drain electrode 13B, and the channel region 14C is located at the source electrode 13A and the drain electrode 13B. Between the gate dielectric layer 12 is between. The patterned hydrogen-containing material layer 15 is disposed on the patterned oxide semiconductor layer 14, and the patterned hydrogen-containing material layer 15 covers at least a portion of the non-channel region 14D of the patterned oxide semiconductor layer 14. For example, in the present embodiment, the patterned hydrogen-containing material layer 15 covers the non-channel region 14D of the patterned oxide semiconductor layer 14 in a comprehensive manner, but is not limited thereto. In other embodiments of the present invention, it is visible. The design needs to selectively cause the patterned hydrogen-containing material layer 15 to only partially cover the non-channel region 14D of the patterned oxide semiconductor layer 14, or to extend the patterned hydrogen-containing material layer 15 to cover the source electrode 13A. With the drain electrode 13B. Further, in the present invention, a portion of the patterned oxide semiconductor layer 14 covered by the patterned hydrogen-containing material layer 15 is defined as a blanket region 14A without patterning oxidation covered by the patterned hydrogen-containing material layer 15. A portion of the semiconductor layer 14 is defined as an uncovered region 14B. The resistivity of the footprint 14A is less than the resistivity of the uncovered region 14B. In this embodiment, the material of the patterned oxide semiconductor layer 14 includes indium gallium zinc oxide (InGaZnOx, IGZO) or zinc oxide (ZnOx), but not limited thereto, and may be other types of oxide semiconductors. material. In addition, the preferred thickness of the patterned oxide semiconductor layer 14 is generally between 10 nm and 60 nm, but is not limited thereto. The material of the patterned hydrogen-containing material layer 15 may include cerium hydroxide-containing cerium, cerium hydroxide-containing, cerium oxyhydroxide or other suitable material, and its main function is to provide a hydrogen component to the patterned oxide semiconductor to be covered. The layer 14 lowers the resistivity of the covered patterned oxide semiconductor layer 14 and further reduces the contact resistance between the patterned oxide semiconductor layer 14 and the source electrode 13A/drain electrode 13B. It should be noted that in the present embodiment, the patterned hydrogen-containing material layer 15 may cover a portion of the channel region 14C of the patterned oxide semiconductor layer 14 and expose a portion of the channel region of the patterned oxide semiconductor layer 14. 14C to ensure effective reduction of the contact resistance between the patterned oxide semiconductor layer 14 and the source electrode 13A/drain electrode 13B. In other embodiments of the present invention, the patterned hydrogen-containing material layer 15 may also selectively cover the channel region 14C of the patterned oxide semiconductor layer 14 according to design requirements.

Please refer to Figure 2. FIG. 2 is a schematic view showing an oxide semiconductor thin film transistor 21 according to another preferred embodiment of the present invention. In this embodiment, the respective elements and material characteristics of the oxide semiconductor thin film transistor 21 are the same as those of the above-described oxide semiconductor thin film transistor 20. For simplification of description, the respective elements are denoted by the same reference numerals. As shown in Fig. 2, the oxide semiconductor thin film transistor 21 is a top-gate TFT structure. The source electrode 13A and the drain electrode 13B are disposed on the substrate 10, wherein the source electrode 13A has an upper surface 13A1 and a side surface 13A2, and the drain electrode 13B has an upper surface 13B1 and a side surface 13B2. The patterned oxide semiconductor layer 14 is disposed on the source electrode 13A, the drain electrode 13B, and the substrate 10. The patterned oxide semiconductor layer 14 has a channel region 14C and a non-channel region 14D, and the non-channel region 14D is at least Partially covering the upper surface 13A1 and the side surface 13A2 of the source electrode 13A and at least partially covering the upper surface 13B1 and the side surface 13B2 of the drain electrode 13B, and the channel region 14C is located between the source electrode 13A and the drain electrode 13B. Above 10. The patterned hydrogen-containing material layer 15 is disposed on the patterned oxide semiconductor layer 14, wherein the patterned hydrogen-containing material layer 15 covers at least a portion of the non-channel region 14D of the patterned oxide semiconductor layer 14. For example, in the present embodiment, the patterned hydrogen-containing material layer 15 covers the non-channel region 14D of the patterned oxide semiconductor layer 14 in a comprehensive manner, but the invention is not limited thereto. The portion of the patterned oxide semiconductor layer 14 covered by the patterned hydrogen-containing material layer 15 is defined as a footprint 14A, and a portion of the patterned oxide semiconductor layer 14 that is not covered by the patterned hydrogen-containing material layer 15 is defined. It is defined as an uncovered area 14B, and the resistivity of the covered area 14A is smaller than the resistivity of the uncovered area 14B. As shown in FIG. 2, the gate dielectric layer 12 covers the substrate 10, the source electrode 13A, the drain electrode 13B, the patterned oxide semiconductor layer 14, and the patterned hydrogen-containing material layer 15, and the gate The electrode 11 is disposed on the gate dielectric layer 12. The material characteristics of the respective elements in this embodiment are the same as those of the oxide semiconductor thin film transistor in the previous preferred embodiment, and will not be described herein.

Please refer to Figures 3A to 3F. 3A to 3F are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention. First, as shown in Fig. 3A, a substrate 10 is provided. Next, a gate electrode 11 is formed on the substrate 10. In the present embodiment, the substrate 10 includes a rigid substrate such as a glass substrate or a flexible substrate, but is not limited thereto. Then, as shown in FIG. 3B, a gate dielectric layer 12 is formed on the substrate 10 and the gate electrode 11. The material of the gate dielectric layer 12 includes barium hydrogen hydride, barium hydroxide, and hydrogen-containing nitrogen. Cerium oxide or other suitable material. Next, as shown in FIG. 3C, a source electrode 13A and a drain electrode 13B are formed on the gate dielectric layer 12, wherein the source electrode 13A has an upper surface 13A1 and a side surface 13A2, and a drain electrode 13B. There is an upper surface 13B1 and a side surface 13B2. Next, as shown in FIG. 3D, a patterned oxide semiconductor layer 14 is formed on the source electrode 13A, the drain electrode 13B, and the gate dielectric layer 12. The patterned oxide semiconductor layer 14 has a channel region 14C. And a non-channel region 14D, wherein the non-channel region 14D at least partially covers an upper surface 13A1 and a side surface 13A2 of the source electrode 13A and at least partially covers an upper surface 13B1 and a side surface 13B2 of the drain electrode 13B, and the channel The region 14C is located above the gate dielectric layer 12 between the source electrode 13A and the drain electrode 13B. Then, as shown in FIG. 3E, a patterned hydrogen-containing material layer 15 is formed on the patterned oxide semiconductor layer 14, wherein the patterned hydrogen-containing material layer 15 covers at least a portion of the non-channel of the patterned oxide semiconductor layer 14. Zone 14D. For example, in the present embodiment, the patterned hydrogen-containing material layer 15 covers the non-channel region 14D of the patterned oxide semiconductor layer 14 in a comprehensive manner, but the invention is not limited thereto. Finally, as shown in FIG. 3F, an annealing process 16 is performed. Wherein the portion of the patterned oxide semiconductor layer 14 covered by the patterned hydrogen-containing material layer 15 is defined as a footprint 14A, a portion of the patterned oxide semiconductor layer 14 not covered by the patterned hydrogen-containing material layer 15. It is defined as uncovered area 14B. The annealing process 16 is used to drive the hydrogen of the patterned hydrogen-containing material layer 15 downward into the footprint 14A such that the resistivity of the footprint 14A is less than the resistivity of the uncovered region 14B, as shown in FIG. The oxide semiconductor thin film transistor 20. In the present embodiment, the annealing process 16 includes an Excimer Laser Annealing (ELA) process or a high temperature annealing process, but is not limited thereto. In addition, in the present embodiment, the material of the patterned oxide semiconductor layer 14 includes indium gallium zinc oxide or zinc oxide, but not limited thereto may be other types of oxide semiconductor materials. The preferred thickness of the patterned oxide semiconductor layer 14 is generally between 10 nm and 60 nm. The material for patterning the hydrogen-containing material layer 15 includes barium hydrogen hydride containing, barium hydroxide or barium hydrogen hydride. It should be noted that in the present embodiment, the patterned hydrogen-containing material layer 15 may cover a portion of the channel region 14C of the patterned oxide semiconductor layer 14 and expose a portion of the channel region of the patterned oxide semiconductor layer 14. 14C to ensure effective reduction of the contact resistance between the patterned oxide semiconductor layer 14 and the source electrode 13A/drain electrode 13B.

Please refer to Figure 4 and refer to Figure 3F together. FIG. 4 is a schematic view showing the relationship between the energy level of the excimer laser annealing process and the thickness of the patterned oxide semiconductor layer 14 according to a preferred embodiment of the present invention. The effect on the patterned oxide semiconductor layer 14 described in FIG. 4 mainly refers to the excimer laser annealing process for the uncovered region 14B when performing the excimer laser annealing process as shown in FIG. 3F. The impact. As shown in FIG. 4, the abscissa indicates the thickness of the patterned oxide semiconductor layer 14, and the ordinate indicates the amount of energy of the excimer laser annealing process. The curve in Fig. 4 represents the critical energy value of the uncoated region 14B at different thicknesses, and the excimer laser annealing process causes the patterned oxide semiconductor layer 14 to change from an amorphous phase to a crystalline phase. In other words, according to Fig. 4, the thickness value of a patterned oxide semiconductor layer 14 is selected on the abscissa, and vertically intersects the curve at a point, and the ordinate value of the point is patterned oxidation for this purpose. At the thickness of the semiconductor layer 14, the amorphous phase is converted to the critical energy value of the crystalline phase. When the energy value applied by the excimer laser annealing process is greater than the critical energy value, the patterned oxide semiconductor layer 14 which originally exhibits an amorphous phase is converted into a crystalline phase. In the present invention, the excimer laser annealing process is required to provide a considerable amount of energy to drive the hydrogen of the patterned hydrogen-containing material layer 15 downward into the footprint 14A so that the resistivity of the footprint 14A is less than that of the uncovered layer. The resistivity of zone 14B. However, in the excimer laser annealing process, it is also necessary to simultaneously consider that the energy of the excimer laser annealing process should not be too large to convert the uncovered region 14B from an amorphous phase to a crystalline phase, thereby affecting the oxide semiconductor thin film. The semiconductor properties of the crystal. Therefore, in this embodiment, the preferred energy range of the excimer laser annealing process is substantially between 50 mJ/cm ² and 600 mJ/cm ² , and the preferred energy range is the control patterned oxide semiconductor layer 14 . The preferred thickness value is generally between 10 nm and 60 nm.

Please refer to Figures 5A and 5B. 5A to 5B are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to another preferred embodiment of the present invention. First, as shown in Fig. 5A, a substrate 10 is provided. Next, a source electrode 13A and a drain electrode 13B are formed on the substrate 10. The source electrode 13A has an upper surface 13A1 and a side surface 13A2. The drain electrode 13B has an upper surface 13B1 and a side surface 13B2. In this embodiment, the substrate 10 includes a rigid substrate such as a glass substrate or a flexible substrate, but is not limited thereto. Then, a patterned oxide semiconductor layer 14 is formed on the source electrode 13A, the drain electrode 13B and the substrate 10. The patterned oxide semiconductor layer 14 has a channel region 14C and a non-channel region 14D, wherein the non-channel region 14D At least partially covering an upper surface 13A1 and a side surface 13A2 of the source electrode 13A and at least partially covering an upper surface 13B1 and a side surface 13B2 of the drain electrode 13B, and the channel region 14C is located at the source electrode 13A and the drain electrode On the substrate 10 between 13B. Then, a patterned hydrogen-containing material layer 15 is formed on the patterned oxide semiconductor layer 14, wherein the patterned hydrogen-containing material layer 15 covers at least a portion of the non-channel region 14D of the patterned oxide semiconductor layer 14. For example, in the present embodiment, the patterned hydrogen-containing material layer 15 covers the non-channel region 14D of the patterned oxide semiconductor layer 14 in a comprehensive manner, but the invention is not limited thereto. Next, as shown in FIG. 5B, an annealing process 16 is performed. Wherein the portion of the patterned oxide semiconductor layer 14 covered by the patterned hydrogen-containing material layer 15 is defined as a footprint 14A, a portion of the patterned oxide semiconductor layer 14 not covered by the patterned hydrogen-containing material layer 15. It is defined as uncovered area 14B. The annealing process 16 is used to drive the hydrogen of the patterned hydrogen-containing material layer 15 down into the footprint 14A such that the resistivity of the footprint 14A is less than the resistivity of the uncovered region 14B. Next, referring to FIG. 2, after the annealing process 16, as shown in FIG. 2, the substrate 10, the source electrode 13A, the drain electrode 13B, the patterned oxide semiconductor layer 14, and the patterned hydrogen-containing material layer 15 are formed. A gate dielectric layer 12 is formed thereon. The material of the gate dielectric layer 12 may include tantalum nitride, hafnium oxide, hafnium oxynitride or other suitable materials. Finally, a gate electrode 11 is formed on the gate dielectric layer 12 to complete the oxide semiconductor thin film transistor 21 as shown in FIG.

The invention utilizes a portion of the patterned oxide semiconductor layer covered with a patterned hydrogen-containing material layer, and an annealing process to reduce the resistivity of the patterned oxide semiconductor layer covered by the patterned hydrogen-containing material layer while controlling The amount of energy applied by the annealing process avoids affecting the semiconductor characteristics of the oxide semiconductor layer, thereby achieving the purpose of reducing the contact resistance between the oxide semiconductor layer and the source/drain electrodes to enhance their electron mobility.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Substrate

11. . . Gate electrode

12. . . Gate dielectric layer

13A. . . Source electrode

13B. . . Bipolar electrode

13A1. . . Upper surface

13A2. . . Side surface

13B1. . . Upper surface

13B2. . . Side surface

14. . . Patterned oxide semiconductor layer

14A. . . Coverage area

14B. . . Uncovered area

14C. . . Channel area

14D. . . Non-channel area

15. . . Patterned hydrogen-containing material layer

16. . . Annealing process

20. . . Oxide semiconductor thin film transistor

twenty one. . . Oxide semiconductor thin film transistor

FIG. 1 is a schematic view showing an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention.

2 is a schematic view showing an oxide semiconductor thin film transistor of another preferred embodiment of the present invention.

3A to 3F are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to a preferred embodiment of the present invention.

FIG. 4 is a schematic view showing the relationship between the energy of the excimer laser annealing process and the thickness of the patterned oxide semiconductor layer according to a preferred embodiment of the present invention.

5A to 5B are schematic views showing a method of fabricating an oxide semiconductor thin film transistor according to another preferred embodiment of the present invention.

10. . . Substrate

11. . . Gate electrode

12. . . Gate dielectric layer

13A. . . Source electrode

13B. . . Bipolar electrode

13A1. . . Upper surface

13A2. . . Side surface

13B1. . . Upper surface

13B2. . . Side surface

14. . . Patterned oxide semiconductor layer

14A. . . Coverage area

14B. . . Uncovered area

14C. . . Channel area

14D. . . Non-channel area

15. . . Patterned hydrogen-containing material layer

16. . . Annealing process

Claims (12)

An oxide semiconductor thin film transistor includes: a substrate; a gate electrode disposed on the substrate; a source electrode and a drain electrode disposed on the substrate, wherein the source electrode and the drain electrode Each has an upper surface and a side surface; a gate dielectric layer disposed between the gate electrode and the source/drain electrode; a patterned oxide semiconductor layer disposed on the substrate, wherein The patterned oxide semiconductor layer has a channel region and a non-channel region, the non-channel region at least partially covering the upper surface and the side surface of the source electrode and at least partially covering the upper surface and the side of the gate electrode a surface of the substrate between the source electrode and the gate electrode; and a patterned hydrogen-containing material layer disposed on the patterned oxide semiconductor layer, wherein the patterned hydrogen-containing layer The material layer covers at least a portion of the non-channel region of the patterned oxide semiconductor layer, and the resistivity of the patterned oxide semiconductor layer covered by the patterned hydrogen-containing material layer is less than And patterning the resistivity of the patterned oxide semiconductor layer covered by the hydrogen-containing material layer, wherein the patterned hydrogen-containing material layer further covers a portion of the channel region of the patterned oxide semiconductor layer, and exposing a portion thereof The channel region of the patterned oxide semiconductor layer. The oxide semiconductor thin film transistor according to claim 1, wherein the source electrode and the drain electrode are disposed on the substrate, and the gate dielectric layer is disposed on the source The pole electrode and the drain electrode are disposed on the gate dielectric layer. The oxide semiconductor thin film transistor according to claim 1, wherein the gate electrode is disposed on the substrate, the gate dielectric layer is disposed on the gate electrode, and the source electrode is A drain electrode is disposed on the gate dielectric layer. The oxide semiconductor thin film transistor according to claim 1, wherein the material of the patterned oxide semiconductor layer comprises indium gallium zinc oxide (InGaZnOx, IGZO) or zinc oxide (ZnOx). The oxide semiconductor thin film transistor according to claim 4, wherein the patterned oxide semiconductor layer has a thickness substantially between 10 nm and 60 nm. The oxide semiconductor thin film transistor according to claim 1, wherein the material of the patterned hydrogen-containing material layer comprises cesium hydrogen hydride hydride, cesium hydroxide or bismuth oxyhydroxide. A method for fabricating an oxide semiconductor thin film transistor, comprising: providing a substrate; forming a gate electrode on the substrate; forming a gate dielectric layer on the substrate and the gate electrode; and dielectrically blocking the gate Forming a source electrode and a drain electrode on the layer, wherein the source is electrically The pole and the drain electrode respectively have an upper surface and a side surface; and a patterned oxide semiconductor layer is formed on the source electrode, the drain electrode and the gate dielectric layer, wherein the patterned oxide semiconductor The layer has a channel region and a non-channel region, the non-channel region at least partially covering an upper surface and a side surface of the source electrode and at least partially covering an upper surface and a side surface of the gate electrode, the channel region a gate dielectric layer between the source electrode and the drain electrode; forming a patterned hydrogen-containing material layer on the patterned oxide semiconductor layer, wherein the patterned hydrogen-containing material layer covers at least a portion The non-channel region of the patterned oxide semiconductor layer, the patterned hydrogen-containing material layer further covering a portion of the channel region of the patterned oxide semiconductor layer, and exposing a portion of the patterned oxide semiconductor layer a channel region; and performing an annealing process to drive hydrogen of the patterned hydrogen-containing material layer into the patterned oxide semiconductor layer to be covered by the patterned hydrogen-containing material layer The resistivity of the patterned oxide semiconductor layer is not smaller than the resistivity of the semiconductor layer of the patterned oxide covered by the patterned layer of hydrogen-containing material. The method of fabricating an oxide semiconductor thin film transistor according to claim 7, wherein the annealing process comprises an Excimer Laser Annealing (ELA) process. The method of producing an oxide semiconductor thin film transistor according to claim 8, wherein the energy of the excimer laser annealing process is substantially between 50 mJ/cm ² and 600 mJ/cm ² . The method for producing an oxide semiconductor thin film transistor according to claim 7, wherein the material of the patterned oxide semiconductor layer comprises indium gallium zinc oxide (InGaZnOx, IGZO) or zinc oxide (ZnOx). The oxide semiconductor thin film transistor according to claim 10, wherein the patterned oxide semiconductor layer has a thickness substantially between 10 nm and 60 nm. The method for producing an oxide semiconductor thin film transistor according to claim 7, wherein the material for patterning the hydrogen-containing material layer comprises cesium hydrogen hydride hydride, cesium hydroxide or bismuth oxyhydroxide.