TWI421517B - System and method for testing integrated circuits - Google Patents

Description

Integrated circuit test system and method

The present invention relates to a test method for an integrated circuit, and more particularly to a test method for a memory device.

The fabrication of an integrated circuit involves a wafer process through which a series of fabrication steps are performed to fabricate a plurality of integrated circuits on the wafer. Once the wafer is fabricated, the wafer is diced into individual integrated circuits that are later subjected to processes involving different bond wires and packaging steps. However, it is desirable to be able to test the operation of the integrated circuit before use. In some cases, multiple integrated circuits can be tested before the wafer is cut. Alternatively, such integrated circuits can be tested after the wire bonding and packaging steps. In general, such tests are performed to verify the different electrical characteristics of such integrated circuits. The information obtained from these tests can be provided to a computer to compare the test results with the information stored in the memory and to provide a decision regarding the reliability of the integrated circuit.

Since the integrated circuits are each tested, the test is a process that is consumed for a while. Therefore, considerable effort has been placed on improving the efficiency of the testing process. However, despite this, the test efficiency of the integrated circuit still needs further improvement.

According to one aspect of the invention, a method of testing a semiconductor memory device is disclosed. The semiconductor memory device includes a plurality of data input/output (I/O) connectors, the method comprising simultaneously connecting through at least two data input/outputs Reading a previously written data from the semiconductor memory device, wherein signals from at least two data input/output connectors are combined to generate a composite output signal; comparing the synthesized output signal with a predetermined voltage level And determining whether the semiconductor memory device is operating properly based on a comparison result of the synthesized output signal and the predetermined voltage level.

In accordance with another aspect of the present invention, a method of testing a semiconductor memory device including a plurality of data input/output (I/O) connectors is provided, the method including data input through a semiconductor memory device/ a first data input/output connector and a second data input/output connector for writing one of the input/output channels of one of the testers to the plurality of memories of the semiconductor memory device In the cell, the first data input/output connector and the second data input/output connector are connected to the input/output channel of the tester through one of the nodes disposed outside the semiconductor memory device and the tester; a data input/output connector and a second data input/output connector for reading test data from the semiconductor memory device, wherein the plurality of data input/output connectors and the second data input/output connector are a signal is coupled to the node to generate a composite output signal; and based on the composite output signal and predetermined power One result of level comparison determines whether the semiconductor memory device operates properly.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Referring to FIG. 1, a block diagram for testing the structure of one of a plurality of semiconductor devices is illustrated, wherein each semiconductor device under test is regarded as a device under test ("DUT"). For example, each of the objects to be tested may be a semiconductor memory device including a plurality of memory cells having respective bits of stored data. Each semiconductor memory device can be implemented according to well-known implementations, including one or more pads or pins for data input/output ("I/O"), power, timing, and address data. installation. The testing of the semiconductor memory device can include writing data to a plurality of memory cells, then reading data written in this manner from the memory cells, and determining whether the read data and the written data match. A number of well known semiconductor memory testers are available for testing such semiconductor memory devices.

As shown in Fig. 1, a conventional tester 100 can be used to simultaneously test a plurality of analytes 102a-102c. An adapter 104 can be used as an interface between the tester 100 and the objects to be tested 102a-102c. The adapter 104 can be a passive component that allows the tester 100 to be electrically connected by providing each of the test object data input/output pins to a respective one of the tester input/output channels. Connected to the objects to be tested 102a-102c. The input/output channels of the tester 100 respectively write and read data from a plurality of memory cells of the object to be tested through the input/output pins of the object to be tested. Since the number of input/output channels of the tester is limited, and the data input/output pins of the input/output channels and the object to be tested are one-to-one connections, a limited number of objects to be tested can be given at any given time. Connected to the tester 100 internally. So, for example, if the tester 100 has 640 input/output channels and each of the objects to be tested has 16 data input/output pins, it can be arbitrarily given from the point of view of the input/output source. The maximum number of analytes connected to the tester 100 during the time is 640/16=40. Therefore, using the structure shown in Fig. 1, the tester 100 has 640 input/output channels, and each object to be tested has 16 data input/output pins, and only 40 objects to be tested can be made in parallel. test.

In order to increase the number of analytes that can be simultaneously tested, a plurality of analytes can be connected to each input/output channel of the semiconductor memory device tester. Please refer to FIG. 2, which shows a block diagram of such a structure. As shown in FIG. 2, the first and second objects to be tested 152a and 152b are connected together to a common input/output channel of a tester 150 through a plurality of connectors provided by an adapter 154. More specifically, the first and second analytes 152a and 152b each include the same number of data input/output pins. Each input/output channel of the tester 150 is simultaneously connected to a data input/output pin of the first object to be tested 152a and a data input/output pin of the second object to be tested 152b.

The structure shown in FIG. 2 is advantageous for allowing each input/output channel of the tester 150 to be tested in parallel with respect to the object 152 to be tested, as compared to the structure shown in FIG. Therefore, the time required to test a large number of groups of semiconductor memory devices can be reduced. However, the structure depicted in Figure 2 can cause some degree of excessive damage and reduce overall throughput. The topic of this excessive injury is summarized in Table 1:

As shown in Table 1, according to the structure shown in Fig. 2, each input/output channel of the tester 150 is connected to the data input/output pins of the objects to be tested 152a and 152b, and a plurality of objects to be tested are tested in parallel. There are four possible outcomes at this time. The first case (state 1) corresponds to the case where both of the objects to be tested pass the test. For example, a predetermined data pattern is written and then read from the memory of the objects 152a and 152b. Therefore, for this object to be tested 152a and 152b, the tester 150 gives a result of passing. The fourth case (state 4) corresponds to the case where both of the objects to be tested have not passed the test. For example, neither of the two objects to be tested can return the same data previously written in the memory of the object to be tested. Therefore, for this object to be tested 152a and 152b, the tester 150 gives a result of the failure. Therefore, State 1 and State 4 provide the expected and appropriate results.

However, State 2 and State 3 present a problem of excessive damage. State 2 corresponds to the case where the first DUT 152a does not pass this test, whereas the second DUT 152b passes this test. State 3 corresponds to the case where the first DUT 152a passes this test, but the second DUT 152b does not pass this test. In both cases, the tester 150 detects an incorrect response from the commonly connected test objects 152a and 152b and returns a failed result for the test object. Therefore, for state 2 and state 3, one of the two objects to be tested will be erroneously confirmed as a failed device.

Reference is now made to Figures 3 and 4. Figs. 3 and 4 show an alternative structure which allows a semiconductor tester 200 to connect twice the object to be tested compared to the structure of Fig. 1. Each input/output channel of the semiconductor tester 200 is connected to a single data input/output pin of a single object to be tested 202 through an adapter 204. In the example shown here, each input/output channel of tester 200 is coupled to a pair of data input/output pins D(n) and D(n+8), respectively. For example, input/output channel 1 is connected to data input/output pins D0 and D8, input/output channel 2 is connected to data input/output pins D1 and D9, and so on. Alternatively, each input/output channel of the tester 200 can be connected to a pair of data input/output pins D(n) and D(15-n), respectively. For example, input/output channel 1 can be connected to data input/output pins D(0) and D(15), and input/output channel 2 can be connected to data input/output pins D(1) and D(14). ),and many more. As another alternative, each input/output channel of the tester 200 can be coupled to a pair of data input/output pins D(n) and D(m), where n and m are integers, representing each of the testers 200. An input/output pin is connected to a pair of data input/output pins, respectively, without any special type described below.

Similarly, the adapter 204 can be a passive connection component, indicating that the adapter 204 allows multiple data input/output pins of the object to be tested to simultaneously provide respective output signals to a single input/output of the tester 200. The channel does not require a selector unit or the like to select an input/output signal between the object under test and the adapter end. As shown in FIG. 3, adapter 204 can include a plurality of nodes, including nodes N1-N8. Each node N1-N8 provides a connection point for signals outputted from a plurality of data input/output pins of the object to be tested 202, so that the output signals are combined into a composite signal for providing individual input/output channels of the tester 200. . For example, the node N1 combines the signals from the data input/output pin D0 and the data input/output pin D8 to generate a composite signal, which is supplied to the input/output channel 1 of the tester 200. The node N2 combines the signals from the data input/output pin D1 and the data input/output pin D9 to generate a composite signal which is supplied to the input/output channel 2 of the tester 200 and the like.

Compared to the structure shown in FIG. 1, the structures shown in FIGS. 3 and 4 allow one test input 202 to be tested using only half of the input/output channels of the tester 200. For example, if the tester 200 is smaller than the tester 100 and the tester 200 still has 640 input/output channels, and each of the objects to be tested 202 has 16 data input/output pins, then there are up to 80 The test object can be tested in parallel.

Next, a test flow will be described. This test allows each input/output channel of a semiconductor memory tester to be connected to each group of data input/output pins of a test object, for example, like the third. As shown in the figure and in Figure 4, this approach increases the parallel test capability for existing semiconductor testers. Advantageously, the increased ability in this manner allows for faster and more cost effective testing of semiconductor memory devices.

Referring next to FIGS. 5A and 5B, an embodiment of a test method for testing a semiconductor device using one of the connection structures shown in FIGS. 3 and 4 will be described. FIG. 5A depicts the generated waveform received by the input/output channels of the tester 200. For example, the signal shown in FIG. 5A can be taken as an example of a voltage level from the output of two input/output pins D(0) and D(8) of the object to be tested 202. Combined, and received on input/output channel 1 of tester 200.

The V _HIGH region is a voltage level approximately equal to V _CC and corresponds to the tester 200 when D(n)=output of data "1" and output of D(n+8)=data "1" Receive one of the voltage levels. The V _LOw region is a voltage level approximately equal to the ground potential (GND), and is tested corresponding to when D(n) = output of data "0" and output of D(n+8) = data "0" The device 200 receives one of the voltage levels. The V _MID region is a voltage level approximately equal to 1/2 V _CC and corresponds to when D(n) = output of data "1" and D(n+8) = output of data "0", or when D (n) = output of data "0" and D (n + 8) = one of the voltage levels received by the tester 200 at the output of the data "1".

The voltage output high (VOH) level and the voltage output low (VOL) level set by the tester can be set for the tester 200 to determine whether the test result is passed or failed. As shown in Figure 5B, the VOH level can be set to a voltage level between V _CC and 1/2V _CC , and the VOL level can be set to a voltage level between 1/2V _CC and GND. . Using the VOH and VOL settings shown in Figure 5B, the tester 200 can be used to determine if the object to be tested 202 is operating properly (passed) or improperly operated (failed).

Figures 6A through 6D illustrate four possible test flows for testing in the structures shown in Figures 2 through 5B. In general, the flow shown in Figures 6A through 6D and the description below describe the data input/output pins D(n) and D(n+8); however, this flow can be equally applied to other An alternative structure, such as each of the input/output channels of the tester 200 described above, is coupled to a pair of data input/output pins D(n) and D(15-n) or to a pair of data inputs. / Output pins D(n) and D(m).

FIG. 6A illustrates a first test flow in which the same test data “0” is written to individual memory cells through data input/output pins D(n) and D(n+8), and the work is performed. Read to determine if the memory device is operating properly. Block 250 shows the test data "0" being written from the tester 200 to the object to be tested 202. More specifically, each input/output channel of the tester 200 writes the test data "0" at a respective address through a pair of respective data input/output pins D(n) and D(n+8). "To the memory cell. That is, the test data “0” is written to a first memory cell through the data input/output pin D(n), and the test data “0” is written through the data input/output pin D(n+8). And a second memory cell, wherein the first memory cell and the second memory cell are respectively selected according to address data provided to the object to be tested 202. In some embodiments, the tester 200 can continuously provide write data, such that the test data "0" is first written to a first memory cell associated with the data input/output pin D(n), and then The test data “0” is written to a second memory cell associated with the data input/output pin D(n+8), or vice versa, although it is used to give the first memory cell and the second memory cell. The address data is separately and synchronously supplied to the object to be tested 202.

In some embodiments, the test object 202 can include a test mode, for example, according to a test mode data compression system located in the object to be tested 202, each data input/output pin D(n) and D ( n+8) can write and/or read test data to multiple memory cells, or each data input/output pin D(n) and D(n+8) can be written from multiple memory cells and / Or read test data. The flow shown in FIG. 6A (and the flow shown in FIGS. 6B to 6D) can be performed by writing test data to respective groups of memory cells and reading by respective groups of memory cells. The same applies to such a test object, where each of these memory cells is associated with one of the data input/output pins D(n) and D(n+8).

In block 252, the tester 200 reads the previously written test data from the object to be tested 202 (this test data is written at block 250). More specifically, each input/output channel of the tester 200 is read by a pair of data input/output pins D(n) and D(n+8) of the same memory cell of the selected location in block 250. The test data written. That is, the previously written test data is read simultaneously through the data input/output pins D(n) and D(n+8) of the first memory cell and the second memory cell.

In block 254, the tester 200 compares the VOL level with the output voltage level generated by the combination of pins D(n) and D(n+8) and received by the input/output channels of the tester 200. If the output voltage level is less than the VOL level, the tester 200 indicates that the result represents that the test data "0" was successfully written and then read from the object to be tested 202. If the result is obtained from all of the memory cells of the test object 202, the test object 202 is considered to have passed the test (block 258). Further, if the output voltage level is not less than the VOL level, the tester indicates that the result represents that the test data "0" has not been successfully written, and then reads from at least one of the memory cells 202. In this example, the test object 202 is considered to have failed this test (block 256).

Figure 6B illustrates a second test flow in which the same test data "1" is written to individual memory cells through data input/output pins D(n) and D(n+8), and the work is performed. Read to determine if the memory device is operating properly. Block 260 shows the test data "1" being written from the tester 200 to the object to be tested 202. More specifically, each input/output channel of the tester 200 writes the test data "1" at a respective address through a pair of respective data input/output pins D(n) and D(n+8). "To the memory cell. That is, the test data "1" is written to a first memory cell through the data input/output pin D(n), and the test data "1" is written through the data input/output pin D (n+8). And a second memory cell, wherein the first memory cell and the second memory cell are respectively selected according to address data provided to the object to be tested 202. In some embodiments, the tester 200 can continuously provide write data, such that the test data "1" is first written to a first memory cell associated with the data input/output pin D(n), and then The test data "1" is written to a second memory cell associated with the data input/output pin D (n+8), or vice versa, although it is used to give the first memory cell and the second memory cell. The address data is separately and synchronously supplied to the object to be tested 202.

In some embodiments, the test object 202 can include a test mode, for example, according to a test mode data compression system located in the object to be tested 202, each data input/output pin D(n) and D ( n+8) can write and/or read test data to multiple memory cells, or each data input/output pin D(n) and D(n+8) can be written from multiple memory cells and / Or read test data. The flow shown in FIG. 6B can be equally applied to such a test object by writing test data to respective groups of memory cells and reading by respective groups of memory cells, where Each of these memory cells is associated with one of the data input/output pins D(n) and D(n+8).

In block 262, the tester 200 reads the previously written test data from the object to be tested 202 (this test data is written at block 260). More specifically, each input/output channel of the tester 200 is read by a pair of data input/output pins D(n) and D(n+8) of the same memory cell of the selected location in block 260. The test data written. That is, the previously written test data is read simultaneously through the data input/output pins D(n) and D(n+8) of the first memory cell and the second memory cell.

In block 264, the tester 200 compares the VOH level with the output voltage levels generated by the combination of pins D(n) and D(n+8) and received by the input/output channels of the tester 200. . If the output voltage level is greater than the VOH level, the tester 200 indicates that the result represents that the test data "1" was successfully written and then read from the object to be tested 202. If the result is obtained from all of the memory cells of the test object 202, the test object 202 is considered to have passed the test (block 268). Furthermore, if the output voltage level is not greater than the VOH level, the tester indicates that the result represents that the test data "1" was not successfully written, and then reads from at least one of the memory cells 202. In this example, the test object 202 is considered to have failed this test (block 266).

FIG. 6C illustrates a third test flow in which different test data “0” and “1” are written into the respective memory cells through the data input/output pins D(n) and D(n+8), and Read the book to determine if the memory device is operating properly. Block 270 depicts the test data "0" and "1" being written from the tester 200 to the object to be tested 202. More specifically, each input/output channel of the tester 200 is written to the test data "1" through the data input/output pin D(n) and written to the test through the data input/output pin D (n+8). Data "0" to memory cells located at individual addresses. That is, the test data "1" is written to a first memory cell through the data input/output pin D(n), and the test data "0" is passed through the data input/output pin D (n+8). Write to a second memory cell, wherein the first memory cell and the second memory cell are respectively selected according to address data provided to the object to be tested 202. In some embodiments, the tester 200 can continuously provide write data, such that the test data "1" is first written to a first memory cell associated with the data input/output pin D(n), and then The test data “0” is written to a second memory cell associated with the data input/output pin D(n+8), or vice versa, although it is used to give the first memory cell and the second memory cell. The address data is separately and synchronously supplied to the object to be tested 202.

In some embodiments, the test object 202 can include a test mode, for example, according to a test mode data compression system located in the object to be tested 202, each data input/output pin D(n) and D ( n+8) can write and/or read test data to multiple memory cells, or each data input/output pin D(n) and D(n+8) can be written from multiple memory cells and / Or read test data. The flow shown in FIG. 6C can be equally applied to such a test object by writing test data to respective groups of memory cells and reading by respective groups of memory cells, where Each of these memory cells is associated with one of the data input/output pins D(n) and D(n+8).

In block 272, the tester 200 reads the previously written test data from the object to be tested 202 (this test data is written at block 270). More specifically, each input/output channel of the tester 200 is read by a pair of data input/output pins D(n) and D(n+8) of the same memory cell of the selected location in block 270. The test data written. That is, the previously written test data is read simultaneously through the data input/output pins D(n) and D(n+8) of the first memory cell and the second memory cell.

In block 274, the tester 200 sets the VOH level and the VOL level and the output voltage generated by the combination of pins D(n) and D(n+8) and received by the input/output channels of the tester 200. The position is compared. If the output voltage level is between the VOH level and the VOL level (eg, less than the VOH level, but greater than the VOL level), the tester 200 indicates that the result represents that the test data "0" and "1" are successful. The ground is written and then read from the object to be tested 202. If the result is obtained from all of the memory cells of the test object 202, the test object 202 is considered to have passed the test (block 278). In addition, if the output voltage level is not between the VOH level and the VOL level, the tester indicates that the result represents that the test data “0” and “1” were not successfully written, and then from the object to be tested 202. The memory cells in the memory are read. In this example, the test object 202 is considered to have failed this test (block 276).

FIG. 6D illustrates a fourth test flow in which different test data “1” and “0” are written into the respective memory cells through the data input/output pins D(n) and D(n+8), and Read the book to determine if the memory device is operating properly. Block 280 depicts the test data "0" and "1" being written from the tester 200 to the object to be tested 202. More specifically, each input/output channel of the tester 200 is written to the test data “0” through the data input/output pin D(n) and written to the test through the data input/output pin D(n+8). The data "1" to the memory cells located at the individual addresses. That is, the test data “0” is written to a first memory cell through the data input/output pin D(n), and the test data “1” is passed through the data input/output pin D(n+8). Write to a second memory cell, wherein the first memory cell and the second memory cell are respectively selected according to address data provided to the object to be tested 202. In some embodiments, the tester 200 can continuously provide write data, such that the test data "0" is first written to a first memory cell associated with the data input/output pin D(n), and then The test data "1" is written to a second memory cell associated with the data input/output pin D (n+8), or vice versa, although it is used to give the first memory cell and the second memory cell. The address data is separately and synchronously supplied to the object to be tested 202.

In some embodiments, the test object 202 can include a test mode, for example, according to a test mode data compression system located in the object to be tested 202, each data input/output pin D(n) and D ( n+8) can write and/or read test data to multiple memory cells, or each data input/output pin D(n) and D(n+8) can be written from multiple memory cells and / Or read test data. The flow shown in FIG. 6D can be equally applied to such a test object by writing test data to respective groups of memory cells and reading by respective groups of memory cells, where Each of these memory cells is associated with one of the data input/output pins D(n) and D(n+8).

In block 282, the tester 200 reads the previously written test data from the object to be tested 202 (this test data is written at block 280). More specifically, each input/output channel of the tester 200 is read by a pair of data input/output pins D(n) and D(n+8) of the same memory cell of the selected location in block 280. The test data written. That is, the previously written test data is read simultaneously through the data input/output pins D(n) and D(n+8) of the first memory cell and the second memory cell.

In block 284, the tester 200 sets the VOH level and the VOL level and the output voltage generated by the combination of pins D(n) and D(n+8) and received by the input/output channels of the tester 200. The position is compared. If the output voltage level is between the VOH level and the VOL level (eg, less than the VOH level, but greater than the VOL level), the tester 200 indicates that the result represents that the test data "1" and "0" are successful. The ground is written and then read from the object to be tested 202. If the result is obtained from all of the memory cells of the object to be tested 202, the object to be tested 202 is considered to have passed the test (block 288). Furthermore, if the output voltage level is not between the VOH level and the VOL level, the tester indicates that the result represents that the test data "1" and "0" were not successfully written, and then from the object to be tested 202. The memory cells in the memory are read. In this example, the test object 202 is considered to have failed this test (block 286).

The test systems and methods described herein can be used in a variety of semiconductor memory tests. For example, the idea of the present disclosure can be applied to wafer testing, final testing, and burn-in testing by setting corresponding connectors and using a suitable structure of the adapter to match the connection structure of the object to be tested. And loop testing. As such, the test systems and methods described herein can be used for testing various types of semiconductor memory devices, including, for example, SRAM memory, NOR flash memory, Pseudo SRAM memory, and bit-wise/ A memory device of such features as character switching capability, low/high bit control, or low/high character control.

Although the test system and method disclosed herein with reference to FIGS. 2 through 6D have primarily explained the reference of connecting the input/output channel of a tester to the data input/output pin of a test object, The scope of the disclosure is not limited to this structure. Those skilled in the art will appreciate that this concept can be extended to include more than two data input/output pins to which the tester input/output channels can be connected to a test object. For example, each input/output channel of a tester can be connected to a data input/output pin of 2N (where N is an integer greater than or equal to 1) of a test object. An alternative embodiment of this type may include two data input/output pins, four data input/output pins, eight data input/output pins, or multiple data input/output pins for one object to be tested. The foot is connected to an input/output channel of a tester to increase test throughput. Therefore, for example, if a sample to be tested has 16 data input/output pins D(0) to D(15), each input/output channel of the tester can be specified to be connected to each group of the object to be tested. (two, four, or eight) data input/output pins. For example, in a specific example, in one embodiment, each input/output channel of the tester is assigned to a set of four data input/output pins connected to the object to be tested, and the connectors can be imaged. Each input/output channel of the tester is connected to data input/output pins D(n), D(n+4), D(n+8), and D(n+12), where, one is n = 0 for the first input/output channel, n = 1 for a second input/output channel, n = 2 for a third input/output channel, and for a fourth input/output channel Word n=3. Further, more alternative connection structures can be used without departing from the scope of the present disclosure.

The above has been disclosed in various embodiments in accordance with the principles disclosed in the present disclosure. However, these embodiments are merely by way of example, and are not intended to limit the principles of the disclosure. Therefore, the breadth and scope of the present invention is defined by the scope of the appended claims and the scope of the claims In addition, the advantages and features described above are provided in the illustrated embodiments, but are not intended to limit the scope of the claimed invention to the process or structure to perform any or all of the above.

In addition, the category headings here are used to provide hints on the content group. These headings are not intended to limit or characterize the invention contained in the claims that may be issued in connection with the disclosure. By way of specific example, although the title is related to the "technical field", the request item should not be limited to the language used under the heading to describe the so-called technical field. In addition, a technique described in the "Background" section should not be taken as an admission that the technology is prior art to any of the inventions disclosed herein. The “Content” section should not be considered as a characterization of the invention contained in the request being issued. In addition, any "invention" referred to in the singular of this disclosure should not be used to contend for the only point of view that is merely novel in the disclosure. The features of a plurality of claims that are issued by the present disclosure are to be construed as a plurality of inventions, and such claims may be defined as the invention(s) and the equivalents thereof. In all cases, the scope of such claims is to be considered in its own right, and may be referred to in this disclosure, but the title thereof should not be used as a limitation.

100, 150, 200. . . Tester

102a-102c, 152a-152b, 202, 202a-202c. . . Analyte

104, 154, 204. . . Adapter

D1-D15. . . Data input/output pin

N1-N8. . . node

FIG. 1 is a block diagram showing a structure for testing a semiconductor memory device.

Figure 2 is a block diagram showing the structure of one of the semiconductor memory devices, wherein the two objects to be tested are connected to each input/output channel of a tester.

3 and 4 are block diagrams showing the structure of one of the semiconductor memory devices, wherein the two pins of one object to be tested are connected to each input/output channel of a tester.

FIGS. 5A and 5B illustrate the voltage levels associated with the method of testing the semiconductor memory device using the structures shown in FIGS. 3 and 4.

6A to 6D are flow charts showing the process of testing the semiconductor memory device with the structures shown in Figs. 3 and 4.

200. . . Tester

202. . . Analyte

204. . . Adapter

D1-D15. . . Data input/output pin

N1-N8. . . node

Claims (20)

A method of testing a semiconductor memory device, the semiconductor memory device comprising a plurality of data input/output (I/O) connectors, the method comprising: simultaneously passing at least two of the data input/output connectors from the semiconductor Reading, in the memory device, a previously written data, wherein signals from the at least two data input/output connectors are combined to generate a composite output signal; comparing the composite output signal with a predetermined voltage level; A comparison result of the composite output signal and the predetermined voltage level determines whether the semiconductor memory device is operating properly. The method of claim 1, wherein the composite output signal is received by a single input/output channel of a tester. The method of claim 1, wherein the reading comprises combining the signals of the at least two data input/output connectors on one of the connectors to generate the composite output signal. . The method of claim 3, wherein the adapter is disposed in series between the semiconductor memory device and a tester. The method of claim 1, further comprising writing a test data to the semiconductor memory device before reading, such that reading the previously written data comprises reading the write in the manner Test data. The method of claim 5, wherein the writing of the test data comprises writing the same data into at least two memory cells through the at least two data input/output connectors. The method of claim 6, wherein comparing the synthesized output signal with the predetermined voltage level comprises comparing the synthesized output signal with a voltage output high (VOH) level, and determining a voltage level of the synthesized output signal. Whether the bit is higher than the voltage output high level. The method of claim 6, wherein comparing the synthesized output signal with the predetermined voltage level comprises comparing the synthesized output signal with a voltage output low (VOL) level, and determining a voltage level of the synthesized output signal. Whether the bit is lower than the voltage output low level. The method of claim 5, wherein the writing of the test data comprises writing different data into at least two memory cells through the at least two data input/output connectors. The method of claim 9, wherein comparing the synthesized output signal with the predetermined voltage level comprises comparing the composite output signal with a voltage output low (VOL) level and a voltage output high (VOH) level. And determining whether the voltage level of the composite output signal is between the voltage output high level and the voltage output low level. A method of testing a semiconductor memory device, the semiconductor memory device comprising a plurality of data input/output (I/O) connectors, the method comprising: passing the data input/output connectors of the semiconductor memory device a first data input/output connector and a second data input/output connector for writing test data from one of the input/output channels of one of the testers to a plurality of memory cells of the semiconductor memory device, The first data input/output connector and the second data input/output connector are connected to the input/output channel of the tester through a node disposed at the semiconductor memory device and outside the tester; Simultaneously reading the test data from the semiconductor memory device through the first data input/output connector and the second data input/output connector, wherein the first data input/output connector and the second a plurality of signals of the data input/output connector are coupled to the node to generate a composite output signal; and based on the composite output No one of the predetermined voltage level comparison result determines whether or not the semiconductor memory device operates properly. The method of claim 11, wherein the composite output signal is received by the input/output channel of the tester. The method of claim 11, wherein the node is located inside an adapter. The method of claim 13, wherein the adapter is disposed in series between the semiconductor memory device and the tester. The method of claim 11, wherein the writing of the test data comprises writing the same data to the first data input/output connector and the second data input/output connector respectively The first memory cell and a second memory cell. The method of claim 15, further comprising comparing the composite output signal and the predetermined voltage level, wherein the predetermined voltage level is a voltage output high level, and determining a voltage of the composite output signal Whether the level is greater than the voltage output high level. The method of claim 15, further comprising comparing the composite output signal and the predetermined voltage level, wherein the predetermined voltage level is a voltage output low (VOL) level, and determining the composite output signal Whether the voltage level is less than the voltage output low level. The method of claim 11, wherein the writing of the test data comprises writing different data to the first data input/output connector and the second data input/output connector respectively. The first memory cell and a second memory cell. The method of claim 18, further comprising comparing the composite output signal and the predetermined voltage level, wherein the predetermined voltage level is a voltage output low level, and comparing the synthesized output signal with a The predetermined voltage outputs a high level, and determines whether a voltage level of the composite output signal is between the voltage output high level and the voltage output low level. The method of claim 11, wherein the writing of the test data further comprises: a third data input/output connector of the data input/output connectors of the semiconductor memory device and a first Writing, by the data input/output connector, the test data, the test data from the input/output channel of the tester to the memory cells of the semiconductor memory device, wherein the first data An input/output connector, the second data input/output connector, the third data input/output connector, and the fourth data input/output connector are disposed on the semiconductor memory device and outside the tester The node is connected to the input/output channel of the tester; and wherein the reading of the test data further comprises simultaneously passing the first data input/output connector, the second data input/output connector, a third data input/output connector and the fourth data input/output connector for reading the test data from the semiconductor memory device, wherein The plurality of signals of the first data input/output connector, the second data input/output connector, the third data input/output connector, and the fourth data input/output connector are coupled to the node To generate a composite output signal.