TWI420790B - Controller for switching power supply - Google Patents

Controller for switching power supply Download PDF

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TWI420790B
TWI420790B TW99123981A TW99123981A TWI420790B TW I420790 B TWI420790 B TW I420790B TW 99123981 A TW99123981 A TW 99123981A TW 99123981 A TW99123981 A TW 99123981A TW I420790 B TWI420790 B TW I420790B
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voltage
circuit
function
power supply
threshold
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TW99123981A
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TW201131949A (en
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Huanyu Lu
En Li
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Monolithic Power Systems Inc
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交換電源供應器之控制器Switching power supply controller

本案關係於電交換電源供應器。This case is related to the electric exchange power supply.

一交換電源供應器產生電輸出電流以供電一負載。一種如此之電源供應器包含變壓器及截波器。該截波器截波透過變壓器一次繞組所感應的一次電流。此感應輸出電流,流經變壓器的二次繞組至負載,以供電該負載。An exchange power supply generates an electrical output current to supply a load. One such power supply includes a transformer and a chopper. The chopper intercepts the primary current induced by the primary winding of the transformer. This induced output current flows through the secondary winding of the transformer to the load to power the load.

一交換電源供應器具有包含線圈的電感。一截波器電路載波自該線圈抽出之一次電流,以供電感輸出一感應電流。電源供應器的多功能接面具有多功能電壓,其係為驅動該線圈的一次電壓的函數。第一電路回應於跨越第一臨限的第一感應電壓,而暫停該截波,該第一感應電壓係為多功能電壓的函數。第二電路回應於跨越第二臨限的第二感應電壓而暫停該載波,該第二臨限為該多功能電壓的函數。An switched power supply has an inductance that includes a coil. A current drawn by the carrier circuit of the chopper circuit from the coil, and an induced current is outputted by the power supply. The multifunction junction of the power supply has a multi-function voltage that is a function of the primary voltage that drives the coil. The first circuit suspends the chopping in response to a first induced voltage across the first threshold, the first induced voltage being a function of the multi-function voltage. The second circuit suspends the carrier in response to a second induced voltage across the second threshold, the second threshold being a function of the multi-function voltage.

該第一電路可以為過電壓保護電路,其回應於該一次電壓的超出有關於第一臨限的過電壓臨限,而暫停該截波。The first circuit can be an overvoltage protection circuit that suspends the chopping in response to the overvoltage threshold of the first threshold exceeding the first threshold.

在另一例子中,第一電路可以為欠電壓保護電路,其回應於該一次電壓落下低於有關於第一臨限的欠電壓臨限而暫停該截波。一關斷電路被組態以補償該多功能電壓,以足夠使得該多功能電壓跨過該第一臨限,以使得第一電路暫停截波。In another example, the first circuit can be an undervoltage protection circuit that suspends the chopping in response to the primary voltage drop being below an undervoltage threshold with respect to the first threshold. A shutdown circuit is configured to compensate for the multi-function voltage sufficient to cause the multi-function voltage to cross the first threshold to cause the first circuit to suspend the chop.

第二電路也可以為叢發模式電路,其當流經負載的電源供應器輸出電流超出為該多功能電壓的函數之電流臨限時,暫停該截波。The second circuit can also be a burst mode circuit that suspends the chop when the output current of the power supply through the load exceeds the current threshold as a function of the multi-function voltage.

示於圖1A-1B中之設備具有在申請專利範圍中所舉的元件例子的部份。該設備為交換電源供應器10。其包含一次整流/濾波電路11,其整流及濾波來自交流源14的交流電流。以在一次供應電壓Vprim 得到直流一次電流Iprim ,以驅動變壓器20的一次繞組W1(或“線圈”)。控制器26截波經由一次繞組W1感應的電流Iprim 。經由一次繞組W1感應的所得變化電流Iprim 感應二次及三次(tertiary)電流Isec 及Itert ,以流經變壓器的二次及三次繞組W2、W3。感應之二次電流Isec 供電負載Rload ,及三次電流Itert 供電控制器26。控制器26具有多功能接面30。供應至此接面30的電壓Vmult 影響控制器26的六個不同功能的操作參數。這些功能為如下所解釋之工作循環控制、一次電流限制、過電壓保護、欠電壓保護、叢發模式及外部關閉。The apparatus shown in Figures 1A-1B has portions of the example of the elements cited in the scope of the patent application. The device is an exchange power supply 10. It includes a primary rectification/filtering circuit 11 that rectifies and filters the alternating current from the alternating current source 14. In order to obtain a DC supply voltage V prim primary current I prim, to drive the transformer primary winding W1 (or "coil") 20. The controller 26 intercepts the current I prim induced via the primary winding W1. The resulting varying current I prim induced via the primary winding W1 induces secondary and tertiary currents I sec and I tert to flow through the secondary and tertiary windings W2, W3 of the transformer. The induced secondary current I sec supplies the load R load and the tertiary current I tert supplies the controller 26. The controller 26 has a multi-function junction 30. The voltage Vmult supplied to this junction 30 affects the operating parameters of the six different functions of the controller 26. These functions are duty cycle control, primary current limit, over voltage protection, under voltage protection, burst mode, and external shutdown as explained below.

一次整流/濾波電路11包含全波整流器,其包含四個二極體D1、D2、D3及D4,以全波整流該交流電流。此電路11更包含儲存電容C1,以濾波及平滑驅動一次繞組W1的一次電壓VprimThe primary rectification/filtering circuit 11 includes a full-wave rectifier including four diodes D1, D2, D3, and D4 to rectify the alternating current in full wave. The circuit 11 further includes a storage capacitor C1 for filtering and smoothing the primary voltage V prim of the primary winding W1.

二次整流/濾波電路32包含:二極體D5,以半波整流變壓器二次繞組W2的輸出Vsec ,以得到施加至負載Rload 的輸出電壓Vout ;及一儲存電容C2,以濾波及平滑VoutThe secondary rectifying/filtering circuit 32 includes: a diode D5, an output V sec of the secondary winding W2 of the half-wave rectifying transformer, to obtain an output voltage V out applied to the load R load ; and a storage capacitor C2 for filtering and Smooth V out .

同樣地,三次整流/濾波電路33包含:二極體D6,以半波整流變壓器三次繞組W3的輸出Vtert 以得到供電控制器26的所有元件的供應電壓Vcc ;及一儲存電容C3,以濾波及平滑VccSimilarly, the tertiary rectifying/filtering circuit 33 includes: a diode D6, an output V tert of the tertiary winding W3 of the half-wave rectifying transformer to obtain a supply voltage V cc of all components of the power supply controller 26; and a storage capacitor C3 to Filter and smooth V cc .

控制器26具有一接地軌Gnd1,其係與電源供應器輸出的接地軌Gnd2隔離。為了該理由,個別接地軌係被標示以不同接地符號41、42。The controller 26 has a ground rail Gnd1 that is isolated from the ground rail Gnd2 of the power supply output. For this reason, individual ground rails are labeled with different ground symbols 41, 42.

在此例子中,控制器26的一部份係被製造為一積體電路晶片,其元件係密封於單一封裝51內。晶片封裝51具有接腳,用以介接至封裝外的電源供應器10的元件。這些接腳包含控制器供應接腳53綁至Vcc 、一控制器接地接腳54連接至控制器接地Gnd1、一汲極接腳55連接至一次繞組W1、一多功能接腳56、及一回授接腳57。In this example, a portion of controller 26 is fabricated as an integrated circuit wafer with components sealed within a single package 51. The chip package 51 has pins for interposing components of the power supply 10 outside the package. These pins include a controller supply pin 53 tied to V cc , a controller ground pin 54 connected to the controller ground Gnd1 , a drain pin 55 connected to the primary winding W1 , a multi-function pin 56 , and a The pin 57 is returned.

多功能接腳56分接至由Vprim 延伸至Gnd1的電阻分壓器60。電阻分壓器64具有上電阻R1及下電阻R2。因此,在多功能接腳的電壓Vmult 等於Vprim R2/(R1+R2)。這使得Vmult 正相關(即為其函數,更明確地說,成比例)於Vprim 並可藉由調整R1及/或R2加以調整。Multi-function pin 56 is tapped to a resistor divider 60 that extends from V prim to Gnd1. The resistor divider 64 has an upper resistor R1 and a lower resistor R2. Therefore, the voltage V mult at the multi-function pin is equal to V prim R2/(R1+R2). This makes V mult positively correlated (ie, its function, more specifically, proportional) to V prim and can be adjusted by adjusting R1 and/or R2.

回授電路70輸出相關於負載電流Iload 的回授電壓Vfb 給回授接腳57。回授部包含光耦合器62,其具有一LED透過電阻R3 及齊納二極體Dz連接至Gnd1。只要Vout 足夠高於齊納二極體崩潰電壓,則LED的光強度正相關於Vout 。因此,當負載電流Iload 降低時,Vout 增加,這增加了LED的光強度。這增加了光耦合器62的光電晶體Tr1的導通,而將回授電壓Vfb 加高向Vcc 以對抗偏壓電阻R4 的向下偏壓。因此,Vfb 係正相關於供應至負載Rload 的輸出電壓Vout ,並逆相關於為負載所吸取的負載電流IloadThe feedback circuit 70 outputs a feedback voltage V fb related to the load current I load to the feedback pin 57. The feedback unit includes an optical coupler 62 having an LED transmission resistor R 3 and a Zener diode Dz connected to Gnd1. As long as V out sufficiently higher than the breakdown voltage of zener diode, the LED light intensity positively correlated V out. Therefore, as the load current I load decreases, V out increases, which increases the light intensity of the LED. This increases the optocoupler phototransistor Tr1 62 is turned on while the feedback voltage V fb raised to V cc downwardly against the bias resistor R bias 4. Therefore, V fb is positively related to the output voltage V out supplied to the load R load and inversely related to the load current I load drawn for the load .

在此例子中之電晶體,場效電晶體(FET)具有源極接面S連接至晶片的接地接腳54、汲極接面D連接至晶片的汲極接腳55、及一閘極接面G。將閘極G向上拉,導通FET,以透過一次繞組W1排放一次電流Iprim 至控制器接地Gnd1。此一次電流Iprim 係被電動地驅動-與感應地相反-在於其係藉由施加電位差於線圈W1之間加以產生。將FET閘極G下拉關斷FET,以停止一次線圈電流Iprim 流經該FET。這係與二次及三次電流Isec 及Itert 相反,這些係感應產生-與電動產生相反。In the transistor of this example, the field effect transistor (FET) has a ground pad S to which the source pad S is connected to the wafer, a pad junction 55 to which the drain pad D is connected to the wafer, and a gate connection. Face G. Pulling the gate G up, turning on the FET to discharge the primary current I prim through the primary winding W1 to the controller ground Gnd1. This primary current I prim is electrically driven - inductively opposite - in that it is generated by applying a potential difference between the coils W1. The FET gate G is pulled down to turn off the FET to stop the primary coil current I prim flowing through the FET. This is in contrast to the secondary and tertiary currents I sec and I tert , which are induced to produce - as opposed to electrodynamic generation.

FET的閘極G係連接至具有四輸入74的第一AND閘A1的輸出。這些輸入之一係為具有兩輸入75的二次AND閘極A2所驅動。只有在AND閘A1及A2之所有輸入74、75均為高時,FET導通。將AND閘的輸入74、75的任一拉下為低,將會關斷FET。AND閘輸入74、75可以為該六電路之任一所拉下為低-明確地說,如下所述之截波器電路81、一次線圈電流限制電路82、過電壓保護電路83、欠電壓保護84、叢發模式電路85及遠端關斷電路86。The gate G of the FET is connected to the output of the first AND gate A1 having four inputs 74. One of these inputs is driven by a secondary AND gate A2 having two inputs 75. The FET is turned on only when all inputs 74, 75 of AND gates A1 and A2 are high. Pulling any of the inputs 74, 75 of the AND gate low will turn off the FET. The AND gate inputs 74, 75 can be pulled low for any of the six circuits - specifically, the chopper circuit 81, the primary coil current limiting circuit 82, the overvoltage protection circuit 83, undervoltage protection as described below 84. The burst mode circuit 85 and the remote turn-off circuit 86.

一開關控制器電路90係被組態以輸出一開關控制器輸出91至開關S1、S2及S3。如果FET被截波器電路81或叢發模式電路85之任一或兩者所關斷,則開關控制信號為高。這係為具有兩OR輸入94、95的OR閘極O1所完成。透過反相器Inv1,一OR輸入94係為叢發模式電路85所驅動。另一OR輸入95係為第三AND閘A3所驅動,該AND閘A3之一AND輸入96透過反相器Inv2連接至截波器電路81。第三AND閘A3更具有另兩輸入98,連接至過電壓電路83及欠電壓電路84的輸出。開關S1及S2係為開關控制器輸出91變高而接通。相反地,開關控制器輸出91變高而開關S3斷開。A switch controller circuit 90 is configured to output a switch controller output 91 to switches S1, S2, and S3. If the FET is turned off by either or both of the chopper circuit 81 or the burst mode circuit 85, the switch control signal is high. This is done for the OR gate O1 with two OR inputs 94, 95. An OR input 94 is driven by the burst mode circuit 85 through the inverter Inv1. The other OR input 95 is driven by a third AND gate A3, and an AND input 96 of the AND gate A3 is coupled to the chopper circuit 81 via an inverter Inv2. The third AND gate A3 further has two other inputs 98 connected to the output of the overvoltage circuit 83 and the undervoltage circuit 84. Switches S1 and S2 are turned "on" by the switch controller output 91 going high. Conversely, switch controller output 91 goes high and switch S3 opens.

截波器電路81限制最大許可工作循環。截波器電路81包含一截波器比較器CR1及一鋸齒波產生器Osc1,其具有鋸齒波輸出104。比較器CR1具有正輸入連接至鋸齒波輸出104,及負輸入透過開關S3連接至多功能接腳56。當鋸齒波104落於多功能電壓Vmult 之下時,比較器CR1的輸出變低,使得第二AND閘A2的輸出變低,這使得第一AND閘A1將FET閘極G拉下為低,這使得FET關斷。The chopper circuit 81 limits the maximum allowable duty cycle. The chopper circuit 81 includes a chopper comparator CR1 and a sawtooth generator Osc1 having a sawtooth output 104. Comparator CR1 has a positive input coupled to sawtooth output 104 and a negative input through switch S3 to multifunction pin 56. When the sawtooth wave 104 falls below the multi-function voltage Vmult , the output of the comparator CR1 goes low, causing the output of the second AND gate A2 to go low, which causes the first AND gate A1 to pull the FET gate G low. This causes the FET to turn off.

圖2顯示Vmult 導通,截波器電路比較器CR1的輸出信號110的作用。這顯示出將Vmult 由較低位準112上升至較高位準114,減少了比較器輸出110為高的時間116並增加了為低之時間118。這減少了FET的導通時間112並增加了關斷時間114。因此,截波器的最大值允許工作循環反比於Vmult 。如圖1A-1B所示,因為Vmult 本身相關於Vprim 、R1及R2,所以工作循環隨著Vprim 變化,並且,可以藉由調整R1及R2加以調整。然而,截波頻率等於鋸齒波的頻率並無關於VmultFigure 2 shows the effect of V mult on, the output signal 110 of the chopper circuit comparator CR1. This shows that Vmult is raised from the lower level 112 to the higher level 114, reducing the time 116 at which the comparator output 110 is high and increasing the time 118 to be low. This reduces the on time 112 of the FET and increases the off time 114. Therefore, the maximum value of the chopper allows the duty cycle to be inversely proportional to V mult . As shown in Figures 1A-1B, since Vmult itself is related to Vprim , R1, and R2, the duty cycle varies with Vprim and can be adjusted by adjusting R1 and R2. However, the chopping frequency is equal to the frequency of the sawtooth wave and is not related to V mult .

為截波器電路81對一次線圈電流Iprim 的截波係有效為任一AND閘輸入為一次電流限制電路82、過電壓保護電路83、欠電壓保護電路84、叢發模式電路85及遠端關斷電路86之任一所拉為低所暫停。The cutoff system for the primary coil current I prim of the chopper circuit 81 is effective for any AND gate input is a primary current limiting circuit 82, an overvoltage protection circuit 83, an undervoltage protection circuit 84, a burst mode circuit 85, and a remote end. Any one of the shutdown circuits 86 is pulled low to be suspended.

當流經一次線圈W1的電流Iprim 超過一次電流臨限,於圖1A-1B中之一次電流限制電路82關斷FET,並甚至在Iprim 下降低於電流臨限後,仍保持FET為關斷,直到鋸齒波的下一上升為止。電流臨限係相反關係於多功能電壓VmultWhen the current I prim flowing through the primary winding W1 exceeds the primary current limit, the primary current limiting circuit 82 in FIG. 1A-1B turns off the FET and remains FET off even after I prim falls below the current threshold. Break until the next rise in the sawtooth wave. The current threshold is inversely related to the multi-function voltage V mult .

一次電流限制電路82利用方波120。此方波120係以類似於藉由比較Vmult 與鋸齒波104加以產生輸出110的方式,比較回授電壓Vfb 與鋸齒波104加以產生。此方波120係輸出至正反器122的Set輸入S。正反器122的Reset接腳R係連接至過電流比較器CR2的輸出。比較器的正輸入係透過前緣遮沒電路LEB連接至VDD ,該前緣遮沒電路LEB於FET關斷時,遮沒感應尖波。The primary current limiting circuit 82 utilizes a square wave 120. The square wave 120 is generated by comparing the feedback voltage Vfb with the sawtooth wave 104 in a manner similar to the manner in which the output 110 is generated by comparing Vmult with the sawtooth wave 104. This square wave 120 is output to the Set input S of the flip-flop 122. The Reset pin R of the flip-flop 122 is connected to the output of the overcurrent comparator CR2. The positive input of the comparator is coupled to V DD through a leading edge blanking circuit LEB that masks the inductive spike when the FET is turned off.

此致使電路81控制FET。在沒有故障狀態下,FET的on/off係為正反器輸出Q所控制。Vfb 與鋸齒波104比較,以產生方波120。當方波120為高時,表示正反器的Set輸入為高,及FET導通,及一次電流Iprim 上升。當電流到達臨限時,電路82輸出高信號至正反器Reset輸入,以關斷FET。This causes circuit 81 to control the FET. In the absence of a fault condition, the on/off of the FET is controlled by the flip-flop output Q. V fb is compared to sawtooth wave 104 to produce square wave 120. When square wave 120 is high, it indicates that the set input of the flip-flop is high, and the FET is turned on, and the primary current I prim rises. When the current reaches the threshold, circuit 82 outputs a high signal to the flip-flop Reset input to turn off the FET.

因為於FET間之電壓隨著電流之增加而增加,所施加至過電流比較器CR2的正輸入的電壓係正相關,更明確地說大約成比例於一次繞組電流Iprim 。比較器CR2的負輸出係連接至汲極臨限電壓Vdrnth ,這係為臨限電壓產生器130所輸出。此產生器130包含op放大器OP1、電壓參考Vref1 、及互連之電阻R5-R8的網路,使得汲極臨限電壓Vdrnth 等於(Vref1 /R5-Vmult /R7)×R6,其中Vmult =Vprim R2/(R1+R2)。只要VDD 超出Vdrnth ,則比較器CR2驅動正反器Reset輸入R為高,這驅動AND閘A2的輸出為低,這驅動AND閘A1的輸出為低,這關斷了FET。Since the voltage between the FETs increases with increasing current, the voltage applied to the positive input of the overcurrent comparator CR2 is positively correlated, more specifically approximately proportional to the primary winding current I prim . The negative output of comparator CR2 is coupled to the drain threshold voltage V drnth , which is output by threshold voltage generator 130. The generator 130 includes a network of an op amplifier OP1, a voltage reference V ref1 , and an interconnected resistor R5-R8 such that the drain threshold voltage V drnth is equal to (V ref1 /R5-V mult /R7)×R6, wherein V mult =V prim R2/(R1+R2). As long as V DD exceeds V drnth , comparator CR2 drives the flip-flop Reset input R high, which drives the output of AND gate A2 low, which drives the output of AND gate A1 low, which turns off the FET.

只要VDD 超出Vdrnth ,則此暫停了一次線圈電流Iprim 的截波。但是VDD 為正相關於一次線圈電流Iprim 。及Vdrnth 為負相關於Vmult ,此Vmult 等於Vprim R2/(R1+R2)。因此,此電路82在Iprim 超出一次電流臨限後,暫停一次線圈電流Iprim 的截波,該一次電流臨限負相關於Vprim 並可以藉由調整R1及/或R2加以調整。This suspends the chopping of the coil current I prim as long as V DD exceeds V drnth . But V DD is positively related to the primary coil current I prim . And V drnth negative correlation to V mult, this equals V mult V prim R2 / (R1 + R2 ). Therefore, this circuit 82 suspends the chopping of the coil current I prim after I prim exceeds the primary current limit, which is negatively correlated with V prim and can be adjusted by adjusting R1 and/or R2.

通常,本質峰值電流限制係為整流器中之內部電路所設定為常數。一旦,汲極電流Iprim 到達電流限制臨限,切換循環應立即終止。然而,固定時間延遲ΔT係由到達臨限直到FET最後關斷為止的時間所衍生。在此延遲中,汲極電流Iprim 持續以等於一次電壓Vprim 除以一次線圈W1的電感Lprim 的速率上升。因此,實際電流限制為本質電流限制臨限及上升率相關成份的總和,該上升率相關成份為汲極電流上升率ΔI/Δt=Vprim /LprimTypically, the intrinsic peak current limit is set to a constant for the internal circuitry in the rectifier. Once the drain current I prim reaches the current limit threshold, the switching cycle should be terminated immediately. However, the fixed time delay ΔT is derived from the time until the threshold is reached until the FET is finally turned off. In this delay, the drain current I prim continues to rise at a rate equal to the primary voltage V prim divided by the inductance L prim of the primary winding W1. Therefore, the actual current limit is the sum of the essential current limit threshold and the rise rate related component, which is the threshold current increase rate ΔI / Δt = V prim / L prim .

將此乘以固定時間延遲ΔT得到ΔT(ΔI/Δt)。因此,DC輸入電壓愈高,則實際電流限制上升至一在低直流輸入電壓之超出本質電流限制位準之位準愈高。這可以造成最大輸出功率Po =Lprim Ip 2 /2的變化,其中Lprim 為一次線圈電感及Ip 為在輸入線電壓範圍內的峰值電流限制。Vmult 可以用以調整在整個輸入線電壓範圍內的固定最大輸出功率。真峰值電流限制等於(Vrefl /R5-Vmult /R7)×R6+ΔTVprim /Lprim ,其中Vmult =Vprim R2/(R1+R2)。輸入電壓Vprim 愈高,則(Vrefl /R5-Vmult /R7)×R6愈小,及ΔTVprim /Lprim 愈大。但在整個輸入線電壓,真峰值電流限制(Vrefl /R5-Vmult /R7)×R6+ΔTVprim /Lprim 仍保持於定值。This is multiplied by a fixed time delay ΔT to obtain ΔT (ΔI/Δt). Therefore, the higher the DC input voltage, the higher the actual current limit rises to a higher level than the intrinsic current limit level of the low DC input voltage. This can result in a change in maximum output power P o = L prim I p 2 /2, where L prim is the primary coil inductance and I p is the peak current limit over the input line voltage range. V mult can be used to adjust the fixed maximum output power over the entire input line voltage range. The true peak current limit is equal to (V refl /R5-V mult /R7)×R6+ΔTV prim /L prim , where V mult =V prim R2/(R1+R2). The higher the input voltage V prim , the smaller (V refl /R5-V mult /R7)×R6 and the larger ΔTV prim /L prim . However, at the entire input line voltage, the true peak current limit (V refl /R5-V mult /R7) × R6 + ΔTV prim /L prim remains at a constant value.

當驅動一次線圈W1的一次電壓Vprim 超出過電壓臨限時,過電壓保護電路83關斷FET。此電路83包含過電壓比較器CR3,其具有正輸入連接至過電壓臨限參考Vref2 及負輸入透過開關S3連接至多功能電壓VmultThe overvoltage protection circuit 83 turns off the FET when the primary voltage Vprim that drives the primary winding W1 exceeds the overvoltage threshold. This circuit 83 includes an overvoltage comparator CR3 having a positive input coupled to the overvoltage threshold reference Vref2 and a negative input transmissive switch S3 coupled to the multifunction voltage Vmult .

因此,當Vmult 超出Vref2 時,過電壓比較器CR3的輸出變低,而關斷FET。只要Vmult 超出Vref2 ,這有效地暫停截波。因為Vmult 相關於Vprim (的函數),所以,當Vmult 超出相關於Vref2 的有效過電壓臨限時,電路83有效地暫停該截波。更明確地說,因為Vmult =Vprim R2/(R1+R2),所以有效過電壓臨限等於Vref2 (R1+R2)/R2。因此,有效過電壓臨限可以藉由調整R1及/或R2加以調整。當開關S3為OR閘O1變高所斷開時,比較器CR3的負輸入與Vmult 相隔,及施加至比較器的負輸入之最後電壓係為電壓保持電容C4所維持。Therefore, when V mult exceeds V ref2 , the output of the overvoltage comparator CR3 goes low, and the FET is turned off. This effectively suspends the chop as long as V mult exceeds V ref2 . Since V mult is related to the function of V prim , circuit 83 effectively suspends the chop when V mult exceeds the effective overvoltage threshold associated with V ref2 . More specifically, since V mult =V prim R2/(R1+R2), the effective overvoltage threshold is equal to V ref2 (R1+R2)/R2. Therefore, the effective overvoltage threshold can be adjusted by adjusting R1 and/or R2. When switch S3 is turned off when OR gate O1 goes high, the negative input of comparator CR3 is separated from Vmult , and the final voltage applied to the negative input of the comparator is maintained by voltage holding capacitor C4.

當驅動一次線圈W1的一次電壓Vprim 低於欠電壓臨限時,欠電壓保護電路84關斷FET。電路84包含欠電壓比較器CR4,其具有負輸入連接至欠電壓臨限Vref3 及正輸入經由第三開關S3連接多功能電壓Vmult 。因此,當Vmult 低於Vref3 時,欠電壓比較器之輸出將變低,以關斷FET。只要Vmult 低於Vref3 時,這有效地暫停截波。The undervoltage protection circuit 84 turns off the FET when the primary voltage Vprim that drives the primary winding W1 is below the undervoltage threshold. The circuit 84 includes an undervoltage comparator CR4 having a negative input coupled to the undervoltage threshold Vref3 and a positive input coupled to the multifunction voltage Vmult via a third switch S3. Therefore, when V mult is lower than V ref3 , the output of the undervoltage comparator will go low to turn off the FET. This effectively suspends the chop as long as V mult is lower than V ref3 .

在欠電壓保護電路84中,因為Vmult 係有關於Vprim ,所以當Vmult 低於相關於Vref3 的有效欠電壓臨限時,電路84有效地暫停截波。更明確地說,因為Vmult =Vprim R2/(R1+R2),所以有效欠電壓臨限等於Vref3 (R1+R2)/R2。因此,有效欠電壓臨限可以藉由調整R1及/或R2調整。In the under-voltage protection circuit 84, since the line V mult relates V prim, so that when the effective temporary undervoltage limit V mult below in relation to V ref3, the suspension circuit 84 effectively cut-off wave. More specifically, since V mult =V prim R2/(R1+R2), the effective undervoltage threshold is equal to V ref3 (R1+R2)/R2. Therefore, the effective undervoltage threshold can be adjusted by adjusting R1 and/or R2.

藉由將一輸入電阻(未示出)加至各個正輸入及一具有較遠大於該輸入電阻的電阻值之回授電阻(未示出)加於個別比較器正輸入及其輸出間,磁滯現象可以施加至過電壓及欠電壓比較器CR3、CR4的輸出。當比較器輸出為高時,此電阻組態略提昇比較器正輸入,及當比較器輸出低以加入磁滯現象時,則略降低比較器正輸入。A feedback resistor (not shown) is applied between each positive input and its output by applying an input resistor (not shown) to each positive input and a feedback resistor (not shown) having a resistance value greater than the input resistance. The hysteresis can be applied to the outputs of the overvoltage and undervoltage comparators CR3, CR4. When the comparator output is high, this resistor configuration slightly boosts the comparator positive input, and when the comparator output is low to add hysteresis, the comparator positive input is slightly reduced.

當相關於輸出電壓Vout 的Vfb 超出臨限電壓時,叢發模式電路85關斷FET。此發生於當為負載Rload 所吸引的輸出電流Iload 下降低於臨限電流時。這藉由增加了FET關斷的時間長度及有效地暫停於二次儲存電容C2並不需要被補充的時間段中之截波,而增加了電源供應器10的效率。When the output voltage V out related to the V fb exceeds the threshold voltage, the burst mode circuit 85 off FET. This occurs when the load R load is attracted by the output current I load drops below the threshold current. This increases the efficiency of the power supply 10 by increasing the length of time the FET is turned off and effectively suspending the secondary storage capacitor C2 without the need for a clipping in the supplemented period.

叢發模式電路85包含叢發模式比較器CR5。此比較器CR5具有負輸入連接至在回授接腳57的Vfb 。其更有一正輸入透過開關S1及S2連接至Vmult 及定電流源140(例如由NXP半導體公司之IC晶片PSSI2021SAY)。電流源140由Vcc 導通一固定電流Iref 至比較器CR5的正輸入並透過電阻R2至Gnd1。因此,當開關S1及S2為OR閘變高所接通時,在比較器的正輸入的電壓為Vprim R2/(R1+R2)+Iref R2,其中Iref R2等於當FET為關斷時的固定電壓及當FET為導通時,其大約為零。當兩開關S1及S2為OR閘O1之變低所斷開時,比較器CR5的正輸入隔離開Vmult 及Iref ,及施加至比較器輸入的最後電壓係為電壓維持電容C5所維持。The burst mode circuit 85 includes a burst mode comparator CR5. This comparator CR5 has a negative input connected to Vfb at the feedback pin 57. Further, a positive input is connected to V mult and constant current source 140 through switches S1 and S2 (for example, IC chip PSSI2021SAY by NXP Semiconductors). Current source 140 conducts a fixed current I ref from V cc to the positive input of comparator CR5 and through resistors R2 through Gnd1. Therefore, when switches S1 and S2 are turned "OR gate high", the positive input voltage at the comparator is V prim R2 / (R1 + R2) + I ref R2, where I ref R2 is equal to when the FET is off The fixed voltage at the time and when the FET is turned on, it is approximately zero. When the two switches S1 and S2 are turned off when the OR gate O1 goes low, the positive input of the comparator CR5 isolates V mult and I ref , and the final voltage applied to the comparator input is maintained by the voltage sustain capacitor C5.

當Vfb 超出Vprim R2/(R1+R2)+Iref R2時,叢發模式電路85暫停截波。這重合於輸出電流Iload 下降低於輸出電流臨限。這是因為Vfb 係負相關於Iload 。叢發模式進入點係正相關於等於Vprim R2/(R1+R2)之Vmult 與Iref R2。因此,輸出電壓臨限及輸出電流臨限可以藉由調整R1及/或R2加以調整。When V fb exceeds V prim R2 / (R1 + R2) + I ref R2 , the burst mode circuit 85 suspends the chop. This coincides with the output current I load falling below the output current threshold. This is because V fb is negatively related to I load . The burst mode entry point is positively correlated with V mult and I ref R2 equal to V prim R2/(R1+R2). Therefore, the output voltage threshold and output current threshold can be adjusted by adjusting R1 and/or R2.

遠端關斷電路86包含連接多功能接腳56至Gnd1的電晶體Tr2。這使得可以以開關S4關斷截波,該開關S4可以在晶片外殼52外、在控制器26外及在電源供應器10之外。在此例子中,開關S4為手動控制機械開關,但也可以為電子控制開關。當開關S4接合時,其將電晶體Tr2的閘極連接至Vcc,這使得電晶體Tr2將Vmult 排放至Gnd1,這補償Vmult 至低於欠電壓臨限Vref3 的位準。這造成欠電壓電路84關斷FET。只要外部開關S4作動,這就有效地暫停截波。當開關S4釋放時,偏壓電阻R9將電晶體Tr的閘極拉下,以關斷電晶體Tr並重新開始截波。The remote turn-off circuit 86 includes a transistor Tr2 that connects the multi-function pins 56 to Gnd1. This makes it possible to switch off the cutoff with switch S4, which can be outside the wafer housing 52, outside the controller 26 and outside of the power supply 10. In this example, switch S4 is a manually controlled mechanical switch, but can also be an electronically controlled switch. When the switch S4 is engaged, which is connected to the gate of the transistor Tr2 Vcc, which makes the discharge transistor Tr2 to V mult Gnd1, which compensates for V mult undervoltage below the threshold level V ref3 of. This causes the undervoltage circuit 84 to turn off the FET. This effectively suspends the chopping as long as the external switch S4 is actuated. When the switch S4 is released, the bias resistor R9 pulls off the gate of the transistor Tr to turn off the transistor Tr and restart the chopping.

過電壓、欠電壓及外部關斷電路83、84及86共享一共用特性,即根據Vmult 與一參考值的比較而暫停截波。這與該截波器、一次電流限制及叢發模式電路81、82及85不同,其中Vmult 係為該參考值,並被用以與其他感應電壓作比較。The overvoltage, undervoltage, and external shutdown circuits 83, 84, and 86 share a common characteristic that suspends the chopping based on a comparison of Vmult with a reference value. This is different from the chopper, primary current limiting and burst mode circuits 81, 82 and 85, where Vmult is the reference value and is used to compare with other induced voltages.

圖1A-1B之例示電源供應器係為“隔離”型電源供應器,其中該電感係為變壓器,其中,一次線圈W1電隔離開該二次線圈W2、W3。控制器26截波流經一次線圈W1的電流,以藉由在一次線圈W1及二次線圈W2、W3間之互感,而產生流經二次線圈W2、W3的輸出電流。1A-1B illustrate an "isolated" type power supply, wherein the inductance is a transformer, wherein the primary winding W1 electrically isolates the secondary windings W2, W3. The controller 26 intercepts the current flowing through the primary coil W1 to generate an output current flowing through the secondary coils W2, W3 by the mutual inductance between the primary coil W1 and the secondary coils W2, W3.

另一類型之電源供應器210係示於圖3A-3B,其中元件係被標示與圖1A-1B中之對應元件相同的元件符號。這是“非隔離”,更明確地說,“升壓”類型電源供應器,其中電感只包含一單一線圈W4。在此類型之電源供應器中,控制器截波經由線圈W4的一次電流,以感應產生藉由自感之流經相同線圈W4的感應電流。對此非隔離電源供應器10’的控制器26的功能係與圖1A-1B的“隔離”供應器相同。Another type of power supply 210 is shown in Figures 3A-3B, wherein the components are labeled with the same component symbols as the corresponding components of Figures 1A-1B. This is "non-isolated", more specifically, a "boost" type power supply where the inductor contains only a single coil W4. In this type of power supply, the controller intercepts a primary current through coil W4 to induce an induced current flowing through the same coil W4 by self-inductance. The function of controller 26 for this non-isolated power supply 10' is the same as the "isolated" supply of Figures 1A-1B.

於此所用之說明係使用例子以揭示本發明,包含最佳模式,並使得熟習於本技藝者完成並使用本發明。本發明之專利範圍係為以下之申請專利範圍所界定,並可以包含為熟習於本技藝者所知之其他例子。此等其他例子係在本案申請專利範圍內,其可以具有與申請專利範圍中所用之不同表達方式之元件,或者,其可以用與申請專利範圍中大致相同的等效元件。The illustrations used herein are intended to be illustrative of the invention, including the best mode, and are in The patentable scope of the invention is defined by the scope of the claims These other examples are within the scope of the present patent application, and may have elements that are different from those used in the scope of the patent application, or may use substantially equivalent elements in the scope of the patent application.

10...交換電源供應器10. . . Switching power supply

11...一次整流濾波電路11. . . Primary rectification filter circuit

14...交流源14. . . Exchange source

20...變壓器20. . . transformer

26...控制器26. . . Controller

30...多功能接面30. . . Multi-functional joint

32...二次整流/濾波電路32. . . Secondary rectification/filter circuit

33...三次整流/濾波電路33. . . Triple rectification/filter circuit

41...Gnd141. . . Gnd1

42...Gnd242. . . Gnd2

51...單一封裝51. . . Single package

52...晶片外殼52. . . Chip housing

53...控制器供應接腳53. . . Controller supply pin

54...控制器地端接腳54. . . Controller ground pin

55...汲極接腳55. . . Bungee pin

56...多功能接腳56. . . Multi-function pin

57...回授接腳57. . . Feedback pin

60...電阻分壓器60. . . Resistor divider

62...光耦合器62. . . Optocoupler

70...回授電路70. . . Feedback circuit

74...輸入74. . . Input

75...輸入75. . . Input

81...截波電路81. . . Chopper circuit

82...一次線圈電流限制電路82. . . Primary coil current limiting circuit

83...過電壓保護電路83. . . Overvoltage protection circuit

84...欠電壓保護84. . . Undervoltage protection

85...叢發模式電路85. . . Cluster mode circuit

86...遠端關斷電路86. . . Remote shutdown circuit

90...開關控制器電路90. . . Switch controller circuit

91...開關控制器輸出91. . . Switch controller output

94...OR輸入94. . . OR input

95...OR輸入95. . . OR input

96...AND輸入96. . . AND input

98...輸入98. . . Input

104...鋸齒波輸出104. . . Sawtooth output

110...輸出信號110. . . output signal

112...較低位準112. . . Lower level

114...較高位準114. . . Higher level

120...方波120. . . Square wave

122...正反器122. . . Positive and negative

130...產生器130. . . Generator

140...電流源140. . . Battery

210...電源供應器210. . . Power Supplier

D1-D6...二極體D1-D6. . . Dipole

C1-C5...儲存電容C1-C5. . . Storage capacitor

W1...一次繞組W1. . . Primary winding

W2...二次繞組W2. . . Secondary winding

W3...三次繞組W3. . . Third winding

A1-A3...AND閘A1-A3. . . AND gate

CR1...截波比較器CR1. . . Chop comparator

Osc1...鋸齒波產生器Osc1. . . Sawtooth generator

LEB...前緣遮沒電路LEB. . . Leading edge masking circuit

CR2...過電流比較器CR2. . . Overcurrent comparator

CR3...過電壓比較器CR3. . . Overvoltage comparator

CR4...欠電壓比較器CR4. . . Undervoltage comparator

CR5...叢發模式比較器CR5. . . Burst mode comparator

圖1A及1B為隔離電源供應器示意圖的兩個半部1A and 1B are two halves of an isolated power supply schematic

圖2顯示電源供應器的波形。Figure 2 shows the waveform of the power supply.

圖3A及3B為非隔離電源供應器示意圖的兩個半部。3A and 3B are two halves of a schematic diagram of a non-isolated power supply.

10...交換電源供應器10. . . Switching power supply

11...一次整流濾波電路11. . . Primary rectification filter circuit

14...交流源14. . . Exchange source

20...變壓器20. . . transformer

26...控制器26. . . Controller

30...多功能接面30. . . Multi-functional joint

32...二次整流/濾波電路32. . . Secondary rectification/filter circuit

33...三次整流/濾波電路33. . . Triple rectification/filter circuit

41...Gnd141. . . Gnd1

42...Gnd242. . . Gnd2

51...單一封裝51. . . Single package

52...晶片外殼52. . . Chip housing

53...控制器供應接腳53. . . Controller supply pin

54...控制器地端接腳54. . . Controller ground pin

55...汲極接腳55. . . Bungee pin

56...多功能接腳56. . . Multi-function pin

57...回授接腳57. . . Feedback pin

60...電阻分壓器60. . . Resistor divider

62...光耦合器62. . . Optocoupler

70...回授電路70. . . Feedback circuit

74...輸入74. . . Input

75...輸入75. . . Input

81...截波電路81. . . Chopper circuit

82...一次線圈電流限制電路82. . . Primary coil current limiting circuit

83...過電壓保護電路83. . . Overvoltage protection circuit

84...欠電壓保護84. . . Undervoltage protection

85...叢發模式電路85. . . Cluster mode circuit

86...遠端關斷電路86. . . Remote shutdown circuit

90...開關控制器電路90. . . Switch controller circuit

91...開關控制器輸出91. . . Switch controller output

94...OR輸入94. . . OR input

95...OR輸入95. . . OR input

96...AND輸入96. . . AND input

98...輸入98. . . Input

104...鋸齒波輸出104. . . Sawtooth output

110...輸出信號110. . . output signal

120...方波120. . . Square wave

122...正反器122. . . Positive and negative

130...產生器130. . . Generator

140...電流源140. . . Battery

D1-D6...二極體D1-D6. . . Dipole

C1-C5...儲存電容C1-C5. . . Storage capacitor

W1...一次繞組W1. . . Primary winding

W2...二次繞組W2. . . Secondary winding

A1-A3...AND閘A1-A3. . . AND gate

CR1...截波比較器CR1. . . Chop comparator

LEB...前緣遮沒電路LEB. . . Leading edge masking circuit

CR2...過電流比較器CR2. . . Overcurrent comparator

CR3...過電壓比較器CR3. . . Overvoltage comparator

CR4...欠電壓比較器CR4. . . Undervoltage comparator

CR5...叢發模式比較器CR5. . . Burst mode comparator

Claims (23)

一種交換電源供應器,包含:包含線圈的電感;截波器電路,組態以截波自該線圈抽出之一次電流,以供該電感輸出感應電流;多功能接面,具有多功能電壓,其係為驅動該線圈的一次電壓之函數;第一電路,組態以回應於越過第一臨限的第一感應電壓而暫停該截波,該第一感應電壓係為該多功能電壓的函數;及第二電路,組態以回應於越過第二臨限的第二感應電壓而暫停該截波,該第二臨限係為該多功能電壓的函數,其中該第二電路為叢發模式電路,當流經負載的該電源供應器的輸出電流超出為該多功能電壓的函數之電流臨限時,該叢發模式電路暫停該截波。 An exchange power supply comprising: an inductor comprising a coil; a chopper circuit configured to intercept a primary current drawn from the coil for outputting an induced current of the inductor; a multi-functional junction having a multi-function voltage; Is a function of a primary voltage that drives the coil; the first circuit is configured to suspend the chopping in response to a first induced voltage across the first threshold, the first induced voltage being a function of the multi-function voltage; And a second circuit configured to suspend the chopping in response to a second induced voltage across the second threshold, the second threshold being a function of the multi-function voltage, wherein the second circuit is a burst mode circuit The burst mode circuit suspends the chopping when the output current of the power supply flowing through the load exceeds the current threshold as a function of the multi-function voltage. 如申請專利範圍第1項所述之交換電源供應器,其中該第一電路為過電壓保護電路,其回應於該一次電壓超出相關於該第一臨限的過電壓臨限而暫停該截波。 The switching power supply of claim 1, wherein the first circuit is an overvoltage protection circuit that suspends the chopping in response to the primary voltage exceeding an overvoltage threshold associated with the first threshold . 如申請專利範圍第1項所述之交換電源供應器,其中該第一電路為欠電壓保護電路,其回應於該一次電壓下降低於相關於該第一臨限的欠電壓臨限而暫停該截波。 The switching power supply of claim 1, wherein the first circuit is an undervoltage protection circuit that suspends the primary voltage drop in response to the undervoltage threshold associated with the first threshold. Cut off. 如申請專利範圍第3項所述之交換電源供應器,更包含關斷電路,組態以補償該多功能電壓超出該第一臨限,以使得該第一電路暫停該截波。 The switching power supply of claim 3, further comprising a shutdown circuit configured to compensate for the multi-function voltage exceeding the first threshold to cause the first circuit to suspend the chop. 如申請專利範圍第4項所述之交換電源供應器,其中該關斷電路係為一在該電源供應器外的開關所控制。 The switching power supply of claim 4, wherein the shutdown circuit is controlled by a switch external to the power supply. 如申請專利範圍第1項所述之交換電源供應器,其中該第二電路為叢發模式電路,當驅動負載的該電源供應器的輸出電壓超出電壓臨限時,該叢發模式電路暫停該截波,該電壓臨限為該第二臨限的函數,其本身為該多功能電壓之函數。 The switching power supply device of claim 1, wherein the second circuit is a burst mode circuit, and the burst mode circuit suspends the cut when the output voltage of the power supply driving the load exceeds a voltage threshold Wave, the voltage threshold is a function of the second threshold, which is itself a function of the multi-function voltage. 如申請專利範圍第1項所述之交換電源供應器,其中該第二電路為一次電流限制電路,及該第二感應電壓為經由該線圈抽出之該一次電流的函數,藉以該第二電路回應於該一次電流超出相關於該多功能電壓的一次電流臨限,而暫停該截波。 The switching power supply of claim 1, wherein the second circuit is a primary current limiting circuit, and the second induced voltage is a function of the primary current drawn through the coil, whereby the second circuit responds The cutoff is suspended when the primary current exceeds a primary current threshold associated with the multi-function voltage. 如申請專利範圍第7項所述之交換電源供應器,其中,當暫停該截波時,即使在該一次電流下降低於該一次電流臨限後,該第二電路仍持續暫停該截波,直到下一時鐘循環開始(onset)為止。 The switching power supply of claim 7, wherein when the chop is suspended, the second circuit continues to suspend the chopping even after the primary current drops below the primary current threshold. Until the next clock cycle begins (onset). 如申請專利範圍第7項所述之交換電源供應器,其中該第二感應電壓係為在該截波器電路與該線圈間之接面所導出之一次電壓。 The switching power supply of claim 7, wherein the second induced voltage is a primary voltage derived from a junction between the chopper circuit and the coil. 如申請專利範圍第7項所述之交換電源供應器,其中該一次電流臨限為負相關於該多功能電壓,該多功能電壓係本身正相關於在該截波器電路與該線圈間之接面處的一次電壓。 The switching power supply of claim 7, wherein the primary current threshold is negatively related to the multi-function voltage, the multi-function voltage system itself being positively correlated between the chopper circuit and the coil A voltage at the junction. 如申請專利範圍第1項所述之交換電源供應器,其 中該截波器電路被組態以截波具有一工作循環之該一次電流,該工作循環係為該多功能電壓的函數。 An exchange power supply as described in claim 1 of the patent scope, The chopper circuit is configured to chop the primary current having a duty cycle as a function of the multi-function voltage. 如申請專利範圍第11項所述之交換電源供應器,其中當藉由重覆地導通及阻擋該一次電流而截波該一次電流時,該截波器電路根據波形輸出與為該多功能電壓的函數之波形臨限的比較,而決定何時導通及何時阻擋該一次電流。 The switching power supply device of claim 11, wherein when the primary current is chopped by repeatedly turning on and blocking the primary current, the chopper circuit outputs and the multi-function voltage according to the waveform The waveform of the function is compared to determine when to turn on and when to block the primary current. 如申請專利範圍第1項所述之交換電源供應器,其中該多功能電壓為自較高電壓向較低電壓延伸之電阻分壓器所分接。 The switching power supply of claim 1, wherein the multi-function voltage is tapped by a resistor divider extending from a higher voltage to a lower voltage. 如申請專利範圍第13項所述之交換電源供應器,其中該較高電壓為供電該線圈的一次電壓,及該較低電壓為接地軌,該截波器電路對該接地軌排放該一次電流。 The switching power supply according to claim 13, wherein the higher voltage is a primary voltage for supplying the coil, and the lower voltage is a ground rail, and the chopper circuit discharges the primary current to the ground rail. . 如申請專利範圍第1項所述之交換電源供應器,更包含多數開關及一開關控制電路,其一起組態為一第一狀態,以將該多功能接面連接至該第一電路,而將該多功能接面與該第二電路隔離開;及一起組態為一第二狀態,以將該多功能接面連接至該第二電路,而將該多功能接面與該第一電路隔離開。 The switching power supply device of claim 1, further comprising a plurality of switches and a switch control circuit configured together to be in a first state to connect the multi-function junction to the first circuit, and Isolating the multi-function junction from the second circuit; and configuring together as a second state to connect the multi-function junction to the second circuit, and the multi-function junction and the first circuit Isolated. 如申請專利範圍第15項所述之交換電源供應器,其中該第一電路為過電壓保護電路,該第二電路為叢發模式電路,及該第二狀態係根據為該叢發模式電路所中斷之該一次電流。 The switching power supply of claim 15, wherein the first circuit is an overvoltage protection circuit, the second circuit is a burst mode circuit, and the second state is based on the burst mode circuit. This primary current is interrupted. 如申請專利範圍第1項所述之交換電源供應器,其 中該電感為變壓器,該線圈為該變壓器的一次線圈,及該感應電流為藉由在該一次及二次線圈間之互感,透過該變壓器的二次線圈輸出。 An exchange power supply as described in claim 1 of the patent scope, The inductor is a transformer, the coil is a primary coil of the transformer, and the induced current is output through a secondary coil of the transformer by mutual inductance between the primary and secondary coils. 如申請專利範圍第1項所述之交換電源供應器,其中該感應電流以自感透過該線圈本身輸出。 The switching power supply of claim 1, wherein the induced current is outputted by the coil itself by self-inductance. 一種交換電源供應器,更包含:包含線圈的電感;截波器電路,組態以截波以一工作循環透過該線圈抽出的一次電流,該工作循環係相關於有關於驅動該線圈的該一次電壓的多功能電壓,用以供該電感輸出一感應電流;及該截波器電路以外之第一電路,組態以回應於第一感應電壓越過第一臨限,而暫停該截波,該第一感應電壓及該第一臨限之一或兩者為該多功能電壓的函數,其中該第二電路為叢發模式電路,當流經負載的該電源供應器的輸出電流超出為該多功能電壓的函數之電流臨限時,該叢發模式電路暫停該截波。 An exchange power supply, further comprising: an inductor including a coil; a chopper circuit configured to intercept a primary current drawn through the coil in a duty cycle, the duty cycle being related to the one of driving the coil a multi-function voltage of a voltage for the inductor to output an induced current; and a first circuit other than the chopper circuit configured to suspend the chopping in response to the first induced voltage crossing the first threshold One or both of the first induced voltage and the first threshold are functions of the multi-function voltage, wherein the second circuit is a burst mode circuit, and when the output current of the power supply flowing through the load exceeds The burst mode circuit suspends the cutoff when the current of the function voltage is thresholded. 如申請專利範圍第19項所述之交換電源供應器,其中該第一感應電壓為該多功能電壓的函數。 The switching power supply of claim 19, wherein the first induced voltage is a function of the multi-function voltage. 如申請專利範圍第19項所述之交換電源供應器,其中該第一感應臨限為該多功能電壓的函數。 The switching power supply of claim 19, wherein the first sensing threshold is a function of the multi-function voltage. 如申請專利範圍第19項所述之交換電源供應器,其中當藉由重覆導通及阻擋該一次電流以截波該一次電流時,該截波器電路根據波形輸出與為該多功能電壓之函數 的臨限之比較,而決定何時導通及何時阻擋該一次電流。 The switching power supply device of claim 19, wherein when the primary current is chopped by repeatedly turning on and blocking the primary current, the chopper circuit outputs and the multi-function voltage according to the waveform. function The comparison of the thresholds, and decide when to turn on and when to block the primary current. 一種用於交換電源供應器之控制器,該電源供應器具有一輸出接面,其組態以輸出一輸出電流至負載,並更具有一電感,其包含一線圈,用以由該線圈抽出之變化一次電流感應產生該輸出電流,該控制器包含:截波器電路,組態以截波該一次電流;多功能接面,具有一多功能電壓,其為驅動該線圈的一次電壓的函數,用以供該截波器電路截波具有工作循環的一次電流,該工作循環為該多功能電壓的函數;過電壓保護電路,組態以回應於該多功能電壓超出過電壓臨限,暫停該截波;欠電壓保護電路,組態以回應於該多功能電壓下降低於欠電壓臨限,而暫停該截波;關斷電路,組態以將該多功能電壓下降低於該欠電壓臨限,以使得該欠電壓保護電路暫停該截波;叢發模式電路,組態以當該輸出電流超出為該多功能電壓的函數之電流臨限時暫停該截波;及一次電流限制電路,回應於該一次電流超出一次電流臨限,而暫停該截波,該一次電流臨限係相關於該多功能電壓,及即使在該一次電流下降低於該一次電流臨限後,仍持續暫停該截波,直到下一時鐘循環開始為止。 A controller for exchanging a power supply, the power supply having an output junction configured to output an output current to the load and further having an inductance including a coil for extracting the change from the coil The current sense generates the output current, the controller comprises: a chopper circuit configured to intercept the primary current; the multi-function junction has a multi-function voltage, which is a function of a primary voltage for driving the coil, For the chopper circuit to intercept a primary current having a duty cycle, the duty cycle being a function of the multi-function voltage; the overvoltage protection circuit configured to suspend the intercept in response to the multi-function voltage exceeding an overvoltage threshold Wave; an undervoltage protection circuit configured to suspend the chopping in response to the multifunction voltage drop being below an undervoltage threshold; shutting down the circuit, configured to drop the multifunction voltage below the undervoltage threshold So that the undervoltage protection circuit suspends the chopping; the burst mode circuit is configured to suspend the chopping when the output current exceeds a current threshold that is a function of the multifunction voltage; a primary current limiting circuit suspending the chopping in response to the primary current exceeding a primary current threshold, the primary current threshold being related to the multi-function voltage, and even after the primary current drops below the primary current threshold , the intercept is still paused until the next clock cycle begins.
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