TWI420704B - Method for manufacturing light-emitting semiconductor chip - Google Patents

Description

Semiconductor light emitting wafer manufacturing method

The present invention relates to a method of fabricating an illuminating wafer, and more particularly to a method of fabricating a semiconductor luminescent wafer.

As an emerging light source, light-emitting diodes have been widely used in many occasions and have a tendency to replace traditional light sources.

The most important component of the light-emitting diode is a light-emitting chip, which determines various light-emitting parameters of the light-emitting diode, such as intensity, color, and the like. A conventional light-emitting wafer is generally composed of an N-type semiconductor layer, a light-emitting layer, and a P-type semiconductor layer which are sequentially grown on a sapphire substrate. The electrons of the N-type semiconductor layer of the light-emitting chip and the holes of the P-type semiconductor layer are combined in the light-emitting layer to emit light outward by the excitation of the external current.

Since the lattice constant of the epitaxial layer of the light-emitting chip (ie, the N-type semiconductor layer, the P-type semiconductor layer, and the light-emitting layer) generally does not match the lattice constant of the sapphire substrate, it may be due to internal stress during its growth. A dislocation occurs. Such defects capture minority carriers inside the epitaxial layer, causing them to be released by thermal energy in a nonradiative recombination manner, affecting the luminous efficiency of the luminescent wafer.

Therefore, it is necessary to provide a method of manufacturing a semiconductor light-emitting wafer having high luminous efficiency.

A semiconductor light emitting wafer manufacturing method comprising the steps of: 1) providing a substrate having an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer sequentially grown on the substrate, the epitaxial layer having a through layer a defect of a semiconductor layer, a light-emitting layer and a second semiconductor layer; 2) etching a surface of the second semiconductor layer, the defects of the epitaxial layer being etched to form a recess deep into the light-emitting layer; 3) the first semiconductor layer and the second semiconductor Electrodes were fabricated on the layers.

The semiconductor light-emitting wafer manufacturing method not only removes defects affecting the combination of electrons and holes by etching, but also increases the light-emitting area of the light-emitting layer, so that more light is radiated from the light-emitting layer. Therefore, this method can effectively improve the light extraction efficiency of the semiconductor light emitting element.

10‧‧‧Substrate

12‧‧‧ trench

14‧‧‧ ridge

20‧‧‧ epitaxial layer

22‧‧‧ Defects

24‧‧‧ Groove

30‧‧‧First semiconductor layer

40‧‧‧Lighting layer

50‧‧‧Second semiconductor layer

60‧‧‧buffer layer

70‧‧‧Insulation

80‧‧‧Transparent conductive layer

90‧‧‧First electrode

92‧‧‧second electrode

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a first step of the method of fabricating a semiconductor light-emitting wafer of the present invention.

2 is a second step of the method of fabricating a semiconductor light-emitting wafer of the present invention.

3 is a third step of the method of fabricating a semiconductor light-emitting wafer of the present invention.

4 is a fourth step of the method of fabricating a semiconductor light-emitting wafer of the present invention.

Figure 5 is a fifth step of the method of fabricating a semiconductor light-emitting wafer of the present invention.

The present invention is directed to a method for fabricating a semiconductor light-emitting wafer, which can effectively improve the light-emitting efficiency of a semiconductor light-emitting chip, and mainly includes the following steps. First, a substrate 10 having an epitaxial layer 20 is provided as shown in FIG. The substrate 10 may be made of a suitable material such as sapphire, tantalum carbide (SiC), bismuth (Si), or gallium nitride (GaN). In this embodiment, sapphire is preferably used as the material of the substrate 10. The thickness of the substrate 10 is between 300 μm and 600 μm, and is preferably 430 μm in this embodiment. The substrate 10 is formed with a plurality of trenches 12 on its top surface by wet etching or other means, and portions of the top surface of the substrate 10 that are not etched form a plurality of ridges 14. The trenches 12 and the ridges 14 are alternately distributed on the top surface of the substrate 10, that is, there is a ridge 14 between each two adjacent trenches 12, and a trench is formed between each two adjacent ridges 14. 12. The depth of the trench 12 is determined by factors such as etching time, etching material, and the like, and ranges from 0.3 μm to 1.5 μm. Preferably, the depth of the trench 12 is controlled to about 1 μm in the present embodiment to be on the substrate. 10 surface to obtain a more ideal pattern. In order to improve the growth quality of the epitaxial layer 20 on the substrate 10, a buffer layer 60 is grown in the trench 12 of the substrate 10 by a low temperature technique. The thickness of the buffer layer 60 is preferably 20 nm to facilitate the growth of the epitaxial layer 20. The buffer layer 60 may be made of a material such as aluminum nitride (AlN), gallium nitride or the like having a lattice constant matched with the epitaxial layer 20 to reduce defects 22 which occur when the epitaxial layer 20 is grown. The epitaxial layer 20 includes a first semiconductor layer 30, a light emitting layer 40, and a second semiconductor layer 50 grown in sequence. In this embodiment, the first semiconductor layer 30 is an N-type gallium nitride layer, the second semiconductor layer 50 is a P-type gallium nitride layer, and the light-emitting layer 40 is a multiple quantum well layer. The thickness of the first semiconductor layer 30 is preferably 4 μm, the thickness of the second semiconductor layer 50 is preferably 0.1 μm, and the thickness of the light-emitting layer 40 is preferably 0.125 μm. To further reduce the defects 22 generated during the growth process, The epitaxial layer 20 can be grown on the surface of the substrate 10 by techniques such as ELOG (epitaxy lateral overgrowth), FIELO (facet-initiated ELO), PENDEO epitaxy, and FACELO (facet-controlled ELO). In this embodiment, the epitaxial layer 20 is preferably grown using the FIELO technique, whereby the defects 22 generated during the growth process will collect above the ridges 14 of the substrate 10, while the upper portion of the trenches 12 is deflected due to the defects 22 Defect 22 is distributed. These defects 22 extend through the light emitting layer 40 from the bottom of the first semiconductor layer 30 and extend to the top of the second semiconductor layer 50.

Then, as shown in FIG. 2, the top surface of the second semiconductor layer 50 is etched by wet etching to form a plurality of grooves 24. The solvent used for the wet etching may be a corrosive material such as KOH or H ₃ PO ₄ . Since the surface energy of the defect 22 on the epitaxial layer 20 is the lowest, the bond reaction with the solvent is most easily performed, so the etching will first start from the position of the defect 22 on the top surface of the second semiconductor layer 50 and gradually go down. The surface energy of the (10-1-1) lattice plane of the epitaxial layer 20 made of GaN is relatively lowest, so the solvent will also etch the lattice plane to form a triangular shaped recess 24. The depth of the groove 24 can be limited to be between 0.1 μm and 1 μm by controlling the etching time. This embodiment preferably controls the depth of the recess 24 to be 0.225 μm, i.e., just etched to the bottom of the luminescent layer 40. By the action of the etching, the defects 22 in the light-emitting layer 40 that affect the bonding of electrons and holes are removed, thereby increasing the probability of the electrons and holes being combined, and improving the light-emitting efficiency of the semiconductor light-emitting chip. At the same time, the groove 24 formed by the etching can increase the surface area of the light-emitting layer 40, so that more light can be radiated from the light-emitting layer 40 to the outside, thereby further improving the luminous efficiency of the semiconductor light-emitting chip. In addition, since the wall surface of the groove 24 formed by wet etching is inclined downwardly, the probability of light exiting from the side is increased, thereby increasing the semiconductor, compared to forming a groove having a vertical wall surface by dry etching. Luminous efficiency of the luminescent wafer. On the other hand, in addition to providing a growth pattern for the FIELO technology, the ridge 14 formed on the substrate 10 can also reflect the light radiated downward from the luminescent layer 40, causing it to be emitted upward, and thus was originally wasted due to downward radiation. The light can also be reused to increase the luminous efficiency of the semiconductor light-emitting wafer (as shown in Figure 5).

Subsequently, as shown in FIG. 3, by plasma chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sol-gel (Sol-Gel), electron beam evaporation (E-beam gun evaporation), ions An insulating layer 70 is formed on the surface of the epitaxial layer 20 by methods such as Ion beam sputtering and physical vapor deposition (Physical Vapor Deposition). The insulating layer 70 fills the recesses 24 and covers the top surface of the second semiconductor layer 50. The insulating layer 70 is used to limit the current path to the light-emitting layer 40 and the second semiconductor layer 50 which are divided into the tapered shape by the recess 24 to prevent the conductive material in the subsequent process from entering the recess 24 and causing uneven current distribution. occur. The insulating layer 70 may be made of cerium oxide (SiO2), and its thickness (excluding a portion filling the groove 24) is preferably between 0.1 μm and 0.2 μm.

Thereafter, the portion of the insulating layer 70 covering the top surface of the second semiconductor layer 50 is removed, the top surface of the second semiconductor layer 50 is exposed, and the portion of the insulating layer 70 filling the recess 24 is left. Methods of removing the insulating layer 70 include, but are not limited to, chemical mechanical polishing (CMP), chemical etching (wet etching), physical etching (dry etching), and the like. Then, on the top surface of the second semiconductor layer 50, vacuum evaporation, sputtering, chemical vapor deposition, electron beam (E-gun) or the like is formed as shown in FIG. A transparent conductive layer 80. The transparent conductive layer 80 may be made of a material having good conductivity such as indium tin oxide (ITO) or nickel gold alloy (Ni/Au) so that current can be uniformly distributed in the second semiconductor layer 50. Due to the insulation inside the groove 24 With the blocking of 70, current will flow from the second semiconductor layer 50 and the light-emitting layer 40 located between the grooves 24 and into the first semiconductor layer 30, thereby ensuring normal light emission of the semiconductor light-emitting wafer.

Finally, the surface of the transparent conductive layer 80 is etched using a yellow lithography technique to define an electrode region exposing the top surface of the first semiconductor layer 30. Further, as shown in FIG. 5, a first electrode 90 is formed on the surface of the electrode region defined on the first semiconductor layer 30 by electron beam, evaporation, sputtering, or the like, and a second electrode is formed on the top surface of the transparent conductive layer 80. 92.

The semiconductor light-emitting chip fabricated by the above method can obtain relatively high light-emitting efficiency, and thus can be widely applied to various occasions requiring high light intensity, especially in some high-power lighting fixtures.

It is to be understood that the term "semiconductor light-emitting chip" as used in the present invention refers to a light-emitting diode chip, a laser diode chip, or the like, which is made of a semiconductor material and has a light-emitting function. Wafer.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

10‧‧‧Substrate

30‧‧‧First semiconductor layer

40‧‧‧Lighting layer

50‧‧‧Second semiconductor layer

70‧‧‧Insulation

80‧‧‧Transparent conductive layer

90‧‧‧First electrode

92‧‧‧second electrode

Claims (9)

A semiconductor light emitting wafer manufacturing method comprising the steps of: 1) providing a substrate having an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer sequentially grown, the epitaxial layer having a first semiconductor therethrough a defect of the layer, the light-emitting layer and the second semiconductor layer, the top surface of the substrate has a plurality of trenches and a plurality of ridges, the defects are located above the ridges; 2) the epitaxial layer is etched, and the defects of the epitaxial layer are etched to form a deep a recess of the light-emitting layer; 3) forming a first electrode and a second electrode electrically connecting the first semiconductor layer and the second semiconductor layer, respectively. The method of fabricating a semiconductor light-emitting wafer according to claim 1, wherein the trench and the ridge are alternately distributed on the top surface of the substrate. The method for fabricating a semiconductor light-emitting wafer according to claim 1, wherein a buffer layer is formed inside the trench, the buffer layer has a thickness smaller than a depth of the trench, and the buffer layer is located between the epitaxial layer and the substrate. The method of fabricating a semiconductor light-emitting wafer according to claim 1, wherein the recess extends from the top surface of the second semiconductor and terminates at a bottom surface of the light-emitting layer. The method of fabricating a semiconductor light-emitting wafer according to claim 4, wherein the width of the groove gradually decreases from the second semiconductor layer toward the light-emitting layer to form an inclined inner wall. The semiconductor light-emitting wafer manufacturing method according to any one of claims 1 to 5, wherein the wet etching is employed in the step 2). The method for fabricating a semiconductor light-emitting chip according to claim 6, wherein the step 2) and the step 3) further comprise a process of forming an insulating layer on the surface of the epitaxial layer, the insulating layer comprising a portion filling the groove. The method of fabricating a semiconductor light-emitting wafer according to claim 7, wherein the insulating layer further comprises a portion covering the top surface of the second semiconductor layer. The method for fabricating a semiconductor light emitting wafer according to claim 8 , wherein the step 2) and the step 3) further comprise removing a portion of the insulating layer covering the top surface of the second semiconductor layer and exposing the second semiconductor layer The step of forming a transparent conductive layer on the surface.