TWI416852B - Switching power converters and switching control circuits therefor - Google Patents

Abstract

A system and method is provided to support airport runway traffic controllers managing landing, takeoff and runway taxi operations at a single airport or integrated multiple airports. The system and method determine the traffic situation on the airport surface and in the airspace proximate to the airport to identify candidate aircraft or other vehicles for runway landing, takeoff and taxi entry at the current instant and assesses a comprehensive set of constraints to determine which aircraft or other vehicle should initiate a runway operation immediately. The constraints include inter- aircraft distance and time minimum spacing requirement, blockages due to aircraft and other vehicles on the runway and externally- derived traffic restrictions. The system and method generate runway takeoff clearance advisories for departure aircraft, initiate missed approach instruction advisories for arrival aircraft and runway clearance advisories to taxi across or along runways for aircraft and other vehicles.

Description

Switching power converter and its switching control circuit

The present invention relates to a switching control circuit, and more particularly to a switching control circuit for switching a power converter.

The power converter is used to convert an unregulated power supply to a stable voltage or current source. Power converters typically include a transformer or magnetic element having a primary side coil and a secondary side coil to provide isolation. A diverter switch coupled to the primary side coil is used to control the transfer of energy from the primary side coil to the secondary side coil. The power converter operates at high frequencies so that size and weight can be reduced.

However, the switching operation of the switch will result in switching loss and electromagnetic-interference (EMI). Figure 1 shows the fly-back power converter, and the waveform of the associated signal is shown in Figure 2. Q ₁ based switch to switch control of the power transformer T ₁ and T ₁ is transmitted by the transformer primary side coil of the transformer T ₁ N _P to the secondary winding N _S. The switching signal V _G is generated to drive the switching switch Q ₁ . When the conduction period T _ON switch Q ₁ is V _G when the switching signal is turned on, energy stored in the transformer T _1. When the switch Q ₁ turns off, the energy of _a transformer T via rectifier D _S is discharged to the output of the flyback converter the power. At the same time, the voltage across the output capacitor C _O and ₁ of the transformer T turns ratio of the transformer T ₁ N _P of the primary coil according to the reflection signal voltage V _R (not shown in FIG. 1). Thus, once the switch Q ₁ is closed, the voltage across the switching device Q V _{D 1} is equal to the input voltage V _IN plus the reflected voltage signal V _R. The energy from the voltage V _D is stored in the dummy parasitic capacitor C _Q , wherein the virtual parasitic capacitor C _Q corresponds to the parasitic capacitor of the switching switch Q ₁ . After a discharge time T _DS , the energy of the transformer T ₁ is completely discharged, and the energy stored in the parasitic capacitance C _Q is reversed to the input voltage V _IN through the primary side coil N _{P of the} transformer T ₁ . The parasitic capacitor C _Q forms a resonant tank with the primary side coil inductor of the transformer T ₁ . Wherein, the resonant tank frequency f _R can be expressed by the formula (1):

Here, C _j represents the capacitance value of the parasitic capacitor C _Q , and L _P represents the inductance value of the primary side coil inductance of the transformer T ₁ .

During the resonance period, the energy of the parasitic capacitor C _Q is transferred back and forth to the primary side coil inductor of the transformer T1. The power converter has a delay time _Tq that corresponds to the time it takes for the parasitic capacitor _{CQ to} discharge until the voltage _VD reaches a minimum. The delay time T _q is a period of quasi-resonant, and it can be expressed by the formula (2):

In summary, if the switching period of the switch Q ₁ valley voltage across switch Q ₁ is turned on, soft switching may be achieved, in order to minimize the power converter switching losses and electromagnetic interference (EMI).

The invention provides a switching control circuit suitable for switching power converters. The switching control circuit is coupled to the switch and the auxiliary coil of the transformer. The switching control circuit includes a valley detecting circuit, a valley locking circuit, and a pulse width modulation (PWM) circuit. The valley detecting circuit receives the reflected voltage signal from the auxiliary coil of the transformer to output a control signal according to the reflected voltage signal. The valley lock circuit receives the control signal to output a determination signal according to the control signal in the first period and the second period, wherein the second period is continued in the first period. The pulse width modulation (PWM) circuit outputs a switching signal based on the determination signal.

The present invention provides a switching power converter including a switching switch, a transformer, and a switching control circuit. The switch is controlled by the switching signal. The transformer has a primary side coil and an auxiliary coil. The switching control circuit is coupled to the switch and the auxiliary coil of the transformer. The switching control circuit includes a valley detecting circuit, a valley locking circuit, and a pulse width modulation (PWM) circuit. The valley detecting circuit receives the reflected voltage signal from the auxiliary coil of the transformer to output a control signal according to the reflected voltage signal. The reflected voltage signal is self-resisting when the switch is turned off, and the resistor is coupled to the auxiliary coil of the transformer. The valley lock circuit receives the control signal to output a determination signal according to the control signal in the first period and the second period, wherein the second period is continued in the first period. The pulse width modulation circuit is coupled to the valley lock circuit to receive the determination signal, and outputs a switching signal according to the determination signal to turn on the switch.

The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

Figure 3 is a diagram showing a switching power converter in accordance with the present invention. The switching control circuit 30 includes a feedback terminal FB, a current sensing terminal CS, a voltage detecting terminal DET, an output terminal OUT, a power terminal VCC, and a reference terminal GND. The transformer T ₁ includes a primary side coil N _P , a secondary side coil N _S , and an auxiliary coil N _A . The primary side coil is coupled to the switch Q ₁ . The secondary side coil N _S is coupled to the output of the switching power converter through the first rectifier D _S and the output capacitor C _O . The auxiliary winding N _A is coupled to the power supply terminal VCC of the switching control circuit 30 through the second rectifier D _A and the capacitor C _ST to supply the power supply V _CC to the switching control circuit 30.

Referring again to FIG. 3, the voltage detecting terminal DET of the switching control circuit 30 is coupled to the auxiliary winding N _A through the resistors R ₁ and R ₂ , wherein when the switching switch Q _{1 is} turned off, the switching control circuit 30 receives the resistor R _{2 .} The reflected voltage signal V _A . The output terminal OUT of the switching control circuit 30 generates a switching signal V _G to drive the switching switch Q ₁ . The current sensing resistor R _{S is} coupled to the switching switch Q ₁ such that when the switching switch Q _{1 is} turned on, a switching current signal V _{CS is} generated. In addition, the current sensing terminal CS of the switching control circuit 30 is coupled to the current sensing resistor R _S to receive the switching current signal V _CS . Furthermore, the feedback terminal FB of the switching control circuit 30 is coupled to the optical coupler 35 to receive a feedback signal V _FB . Optical coupler 35 through the resistor 31 and the regulator 32 is coupled to switch the output of the power converter to receive converted into cross feedback signal V _FB at the output capacitor C _O V _O of the output signal and the output signal V _O .

Referring to Figure 3, when the switch Q ₁ is closed, the switching control circuit ₃₀₂ receives the voltage signal V _A reflected from the secondary _coil of the transformer T N _A through resistors R ₁ and R. Next, the switching control circuit 30 detects whether the voltage across the switching switch Q ₁ in a resonance period is close to a valley voltage of the reflected voltage signal V _A and whether the detection has the same comparison with the previous resonance period. Or more troughs. When detected the same number or more of the valley, the switching control circuit 30 is turned on switch Q _1. This increases the efficiency of switching power converters and avoids noise.

Figure 4 is a diagram showing a switching control circuit 30 in accordance with an embodiment of the present invention. The switching control circuit 30 includes a valley detecting circuit 10, a valley locking circuit 20, a minimum off time circuit 70, an unlocking circuit 40, and a pulse width modulation (PWM) circuit 50. The valley detecting circuit 10 includes a switch 101, a first current mirror composed of transistors 100 and 102, a sampling resistor R _M , and a comparator 103. The first current mirror is coupled to the auxiliary winding N _A of the transformer T ₁ through the switch 101 and the resistors R ₁ and R ₂ (shown in FIG. 3 ). When the switch Q ₁ is closed, the switch 101 receives the reflected voltage signal V _A from the resistance R _2, wherein the reflected signal V _A and the voltage across the switch is proportional to the voltage V _D Q ₁ '. The reflected voltage signal V _A alternately oscillates between a positive voltage and a negative voltage during the resonance period.

When the reflected voltage signal V _{A is} at a negative voltage, the switch 101 is turned on, and the first current I ₁ flows through the switch 101. At this time, the first current mirror is mirrored to the second current I ₂ according to the first current I ₁ . Then, the sampling resistor R _M coupled to the first current mirror receives the second current I ₂ and generates a peak voltage signal V _M .

The magnitude of the peak voltage signal V _M is also proportional to the voltage V _D across the switching switch Q ₁ . The valley detecting circuit 10 further includes a peak comparator 103 that receives the peak voltage signal V _M to generate a control signal S _C (comparison result) according to the peak voltage signal V _M and the first threshold voltage V _T1 .

The valley lock circuit 20 includes a counter 200, a register 201, a subtractor 202, and an arbiter 203. The counter 200 receives the control signal S _C to count the number of troughs of the reflected voltage signal V _A in each cycle and generate count data (e.g., C ₀ - C ₃ ) based on the count result. Among them, the counter 200 counts the number of troughs of the reflected voltage signal V _A generated in a current period. Register 201 storing data R ₀ ~ R _3, wherein R ₀ ~ R ₃ data lines from a number of troughs reflected voltage signal V _A of the counter 200 are generated on the previous period and. The subtractor 202 is coupled to the output of the counter 200 and the output of the register 201 to receive the data C ₀ - C ₃ and R ₀ - R ₃ , and perform subtraction operations on the data C ₀ - C ₃ and R ₀ - R ₃ To generate subtraction result data D ₀ to D ₃ . The arbiter 203 receives the data D ₀ - D ₃ for arbitration and outputs a decision signal S _L to the PWM circuit 500. Once the subtraction result data D ₀ to D _{3 are} not less than zero (positive value), the determination signal S _L is enabled, which means that the same or more trough numbers are detected as compared with the previous resonance period. On the other hand, when the subtraction result data D ₀ to D _{3 are} smaller than zero (negative value), the judgment signal S _{L is} disabled, which means that when the number of troughs is detected as compared with the previous resonance period The valley lock circuit 20 performs locking.

Refer again to FIG. 4, the minimum off-time circuit 70 receives the feedback signal V _FB, in order to produce a minimum off-time signal S _RT according to the feedback signal V _FB. The unlocking circuit 40 receives the minimum off time signal S _RT and the control signal S _C to detect the time after the minimum off time of the minimum off time signal S _RT and to detect the time between the two wave valleys. Once the time after the minimum off time of the minimum off time signal S _RT is longer than the time between the two waves, the unlock signal S _UNLOCK is enabled.

The PWM circuit 50 includes an OR gate 51, a gate 52, and a flip-flop 53. The OR gate 51 receives the unlock signal S _UNCLOCK and the decision signal S _L . One of the gates 52 is coupled to the output of the gate 51. The other input of the AND gate 52 receives the minimum off time signal S _RT . The AND gate 52 produces an output signal S ₅₂ . The flip-flop 53 has a clock terminal ck, a data terminal D, a reset terminal R, and an output terminal Q. The clock terminal ck receives the control signal S _C to enable the switching of the signal V _G . The data terminal D is pulled up according to the output signal of the OR gate 51 and the minimum off time signal S _RT . The reset terminal R is coupled to the output of the comparator 60. The comparator 60 is coupled to the feedback terminal FB and the current sensing terminal CS to respectively receive the feedback signal V _FB and the switching current signal V _CS to reset the flip-flop 53 and turn off the switching signal V _G .

Figure 5 is a diagram showing a minimum off time circuit 70 in accordance with an embodiment of the present invention. The minimum off time circuit 70 includes a first comparator 701, an inverter 702, a current source I _REF , a capacitor C ₇₀ , a second comparator 706 , and or a gate 707 . The minimum off time circuit 70 further includes three switches 703 , 704 . With 705. The first comparator 701 receives the feedback signal V _FB and the second threshold voltage V _T2 for a comparison operation. The inverter 702 is coupled to the output of the first comparator 701. Switch 703 receives feedback signal V _FB and is controlled by the output of the first comparator. Switch 704 receives second threshold voltage V _T2 and is controlled by the output of the first comparator through inverter 702. The switch 705 is coupled to the switches 703 and 704 and is controlled by the switching signal V _G . Current source I _REF and capacitor C _{70 are} connected in series between power supply V _CC and ground. The second comparator 706 is coupled to a node between the current source I _REF and the capacitor C ₇₀ and receives the reference voltage V _REF for a comparison operation. The OR gate 707 is coupled to the output of the second comparator 706 and receives the switching signal V _G . Or gate 707 produces a minimum off time signal S _RT .

Figure 6 shows an unlocking circuit 40 in accordance with an embodiment of the present invention. In the unlock circuit 40, the flip-flop 80, the switch 81, the current source 82, the capacitor 83, and the maximum sustain circuit 84 together form a detection circuit to detect the time between the two waves in each cycle. Inverter 85, switch 86, current source 87, capacitor 88, and comparator 89 together form a limiting circuit for limiting the time after the minimum time. Referring to FIG. 7, when the switch Q ₁ turns on, the voltage signal V _A reflector having alternating positive and negative voltage. When the magnitude of the peak voltage signal V _M is greater than the first threshold voltage V _T1 (see FIG. 4), the control signal S _C is enabled. The output signal S ₈₀ from the flip-flop 80 is disabled according to the rising edge of the control signal S _C (as shown in Fig. 6), at which time the switch 81 is turned off and charged by the current source 82 and the capacitor 83. The circuit generates a ramp signal S ₈₁ . Next, the maximum voltage signal V _{MAX is} generated at the output of the maximum sustain circuit 84 (eg, a sampling circuit) and is passed to the negative input of the comparator 89. In addition, another ramp signal S ₈₈ is generated at the positive input of comparator 89 based on the pulse width of the minimum on-time signal S _RT . Once the ramp signal S _{88 is} greater than the maximum voltage signal V _MAX , the unlock signal S _UNLOCK is enabled through the other flip-flop 890 and is disabled by the delay circuit 891 after a delay time.

Figure 8 is a diagram showing a counter 200 of a valley lock circuit 20 in accordance with an embodiment of the present invention. Counter 200 is the fourteen yuan counter comprising four flip-flop 204, to generate data C to the rising edge of the control signal S _{C 0} ~ C _3. Each flip-flop 204 further has a reset terminal R, to the rising edge of the switching signal V _G is reset. This counter is a conventional counter and has been widely used, and thus the description is omitted here.

Figure 9 is a diagram showing the register 201 of the valley lock circuit 20 in accordance with an embodiment of the present invention. The register 201 has input terminals IN0 to IN3 for receiving the data C ₀ to C ₃ outputted by the counter 200 in accordance with the rising edge of the switching signal V _G . The register 201 also has output terminals O ₀ to O ₃ to output data R ₀ to R ₃ .

Figure 10 shows a subtractor 202 in accordance with an embodiment of the present invention. The subtracter 202 is composed of a full adder for receiving data C ₀ to C ₃ and R ₀ to R ₃ , respectively, and performing a subtraction operation. Next, the subtraction result data D ₀ to D ₃ and NEG are output. When the subtraction result is positive, the subtraction result data NEG is enabled; and when the subtraction result is negative, the subtraction result data NEG is disabled.

Figure 11 is a diagram showing an arbiter 203 of a valley lock circuit 202 in accordance with an embodiment of the present invention. The arbiter 203 includes either the gate 90 and the inverse gate 91. Or the gate 90 is coupled to the output subtraction result data D ₀ to D ₃ through the inverse gate 91, and the gate 90 also receives the output subtraction result data NEG. The OR gate 90 outputs a decision signal S _L after a logic operation.

Referring to FIGS. 12A and 4, when the switching signal V _A has alternating positive and negative voltages, the magnitude of the peak voltage signal V _M is inversely proportional to the first voltages V _V1 , V _V2 , V _V3 V _V4 . When the magnitude of the peak voltage signal V _M is greater than the first threshold voltage V _T1 , it represents a valley generation, and the control signal S _C is enabled. In other words, the number of enable signals S _C enabled in a cycle represents the number of troughs generated. When the number of troughs in the second period (current period) P2 is larger than the number of troughs in the first period (previous period) P1, the determination signal S _L becomes a high logic level (enabled). At this time, since the minimum off time signal S _RT is also a high logic level, the switching signal V _G is enabled according to the rising edge of the control signal S _C .

See Section 12B of FIG. 4 second after switching off the switch Q _1, the reflected signal voltage V _A having alternating positive and negative voltage. Once the time after the minimum off time T _off,min is longer than the time between the two valleys T _valley , the unlock signal S _UNLOCK will be enabled during the first period P ₁ . In the second period P ₂ , since the number of troughs of the second period P ₂ is smaller than the number of troughs of the first period P ₁ , the determination signal S _{L is} still disabled (low logic level). At this time, if the minimum off time signal S _RT is at a high logic level, the switching signal V _G is turned to a high logic level (on state) according to the rising edge of the control signal S _C .

According to the above, the switching control circuit of the embodiment of the present invention can detect whether the voltage V _D across the switching switch Q ₁ is close to the valley voltage according to the reflected voltage signal V _A when the switching switch Q _{1 is} turned off. In addition, once the number of troughs per cycle is less than the number of troughs corresponding to the previous cycle, the switching signal V _{G is} enabled after the next trough is detected to avoid noise from valley switching. Therefore, the switching control circuit of the embodiment of the present invention can provide higher efficiency to the switching power converter when operating under different loads.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

Figure 1:

C _O . . . Output capacitor

C _Q . . . Virtual parasitic capacitor

D _S . . . Rectifier

N _P . . . Primary side coil

N _S . . . Secondary side coil

Q ₁ . . . Toggle switch

T ₁ . . . transformer

V _D . . . Voltage

V _G . . . Switching signal

V _IN . . . Input voltage

V _O . . . output signal

Figure 2:

f _R . . . Resonant tank frequency

T _D . . . Discharge time

T _ON . . . During conduction

T _q . . . delay

V _D . . . Voltage

V _G . . . Switching signal

V _IN . . . Input voltage

V _R . . . Reflected voltage signal

Figure 3:

30. . . Switching control circuit

31. . . resistance

32. . . Stabilizer

35. . . Optocoupler

C _O . . . Output capacitor

C _Q . . . Virtual parasitic capacitor

C _ST . . . Capacitor

CS. . . Current sensing terminal

D _A . . . Second rectifier

D _S . . . Rectifier

DET. . . Voltage detection terminal

FB. . . Feedback side

GND. . . Reference end

N _A . . . Auxiliary coil

N _P . . . Primary side coil

N _S . . . Secondary side coil

OUT. . . Output

Q ₁ . . . Toggle switch

R ₁ , R ₂ . . . resistance

R _S . . . Current sense resistor

T ₁ . . . transformer

V _A . . . Reflected voltage signal

V _CC . . . power supply

V _CS . . . Switching current signal

V _FB . . . Feedback signal

V _D . . . Voltage

V _G . . . Switching signal

V _IN . . . Input voltage

V _O . . . output signal

VCC. . . Power terminal

Figure 4:

10. . . Valley detection circuit

20. . . Valley lock circuit

40. . . Unlock circuit

50. . . Pulse width modulation (PWM) circuit

51. . . Gate

52. . . Gate

53. . . Positive and negative

60. . . Comparators

70. . . Minimum off time circuit

101. . . switch

100, 102. . . Transistor

103. . . Comparators

200. . . counter

201. . . Register

202. . . Subtractor

203. . . Arbitrator

Ck. . . Clock end

CS. . . Current sensing terminal

D. . . Data side

DET. . . Voltage detection terminal

FB. . . Feedback side

I ₁ . . . First current

I ₂ . . . Second current

R. . . Reset end

R _M . . . Sampling resistor

Q. . . Output

S ₅₂ . . . output signal

S _C . . . control signal

S _L . . . Judgment signal

S _RT . . . Minimum off time signal

S _UNLOCK . . . Unlock signal

V _A . . . Reflected voltage signal

V _CC . . . power supply

V _FB . . . Feedback signal

V _G . . . Switching signal

V _M . . . Wave voltage signal

V _T1 . . . First threshold voltage

Figure 5:

70. . . Minimum off time circuit

701. . . First comparator

702. . . inverter

703, 704, 705. . . switch

706. . . Second comparator

707. . . Gate

I _REF . . . Battery

C ₇₀ . . . Capacitor

S _RT . . . Minimum off time signal

V _CC . . . power supply

V _FB . . . Feedback signal

V _G . . . Switching signal

V _REF . . . Reference voltage

V _T2 . . . Second threshold voltage

Figure 6:

40. . . Unlock circuit

80. . . Positive and negative

81. . . switch

82. . . Battery

83. . . Capacitor

84. . . Maximum sustain circuit

85. . . inverter

86. . . switch

87. . . Battery

88. . . Capacitor

89. . . Comparators

890. . . Positive and negative

891. . . Delay circuit

S ₈₀ . . . output signal

S ₈₁ , S ₈₈ . . . Ramp signal

S _C . . . control signal

S _RT . . . Minimum off time signal

S _UNLOCK . . . Unlock signal

V _CC . . . power supply

V _G . . . Switching signal

V _MAX . . . Maximum voltage signal

Figure 7:

Q, . . . The output of the flip-flop 80

S _C . . . control signal

S _RT . . . Minimum off time signal

S ₈₁ , S ₈₈ . . . Ramp signal

T _off,min . . . Minimum closing time

V _A . . . Reflected voltage signal

V _G . . . Switching signal

V _MAX . . . Maximum voltage signal

Figure 8:

200. . . counter

204. . . Positive and negative

C ₀ ... C ₃ . . . data

S _C . . . control signal

Vd. . . Voltage

V _G . . . Switching signal

Figure 9:

201. . . Register

C ₀ to C ₃ . . . data

IN0...IN3. . . Input

O ₀ ~ O ₃ . . . Output

R ₀ to R ₃ . . . Output data

V _G . . . Switching signal

Figure 10:

202. . . Subtractor

C ₀ to C ₃ . . . data

D ₀ ... D ₃ . . . Subtraction result data

R ₀ to R ₃ . . . Output data

NEG. . . Subtraction result data

Figure 11:

90. . . Gate

91. . . Reverse or gate

203. . . Arbitrator

D ₀ ... D ₃ . . . Subtraction result data

NEG. . . Subtraction result data

S _L . . . Judgment signal

Figure 12A:

P1. . . First cycle (previous cycle)

P2. . . Second cycle (current cycle)

S _C . . . control signal

S _L . . . Judgment signal

S _RT . . . Minimum off time signal

V _G . . . Switching signal

V _M . . . Wave voltage signal

T _off,min . . . Minimum closing time

V _T1 . . . First threshold voltage

V _V1 /V _V2 /V _V3 /V _V4 . . . First voltage

Figure 12B:

P1. . . First cycle (previous cycle)

P2. . . Second cycle (current cycle)

S _C . . . control signal

S _L . . . Judgment signal

S _RT . . . Minimum off time signal

S _UNLOCK . . . Unlock signal

V _A . . . Reflected voltage signal

V _G . . . Switching signal

V _M . . . Wave voltage signal

T _off,min . . . Minimum closing time

V _T1 . . . First threshold voltage

V _V1 , V _V2 , V _V3 , V _V4 . . . First voltage

T _valley . . . trough

Figure 1 shows a flyback power converter;

Figure 2 is a diagram showing the signal waveform of the flyback power converter in Fig. 1;

Figure 3 shows a switching power converter in accordance with the present invention;

Figure 4 is a diagram showing a switching control circuit for switching a power converter in Fig. 3 according to an embodiment of the present invention;

Figure 5 is a diagram showing the minimum off time circuit of the switching control circuit in Fig. 4 according to an embodiment of the present invention;

Figure 6 is a diagram showing the unlocking circuit of the switching control circuit in Fig. 4 according to an embodiment of the present invention;

Figure 7 is a diagram showing the signal waveform of the switching power converter in Fig. 3;

Figure 8 is a diagram showing the counter of the valley lock circuit of the switching control circuit in Fig. 4 according to an embodiment of the present invention;

Figure 9 is a view showing a register of a valley lock circuit of a switching control circuit in Fig. 4 according to an embodiment of the present invention;

Figure 10 is a diagram showing a subtractor of the valley lock circuit of the switching control circuit in Fig. 4 according to an embodiment of the present invention;

Figure 11 is a diagram showing an arbiter of a valley lock circuit for switching a control circuit in Fig. 4 according to an embodiment of the present invention;

12A and 12B are diagrams showing signal waveforms of the switching power converter in FIG. 3;

10. . . Valley detection circuit

20. . . Valley lock circuit

40. . . Unlock circuit

50. . . Pulse width modulation (PWM) circuit

51. . . Gate

52. . . Gate

53. . . Positive and negative

60. . . Comparators

70. . . Minimum off time circuit

101. . . switch

100, 102. . . Transistor

103. . . Comparators

200. . . counter

201. . . Register

202. . . Subtractor

203. . . Arbitrator

Ck. . . Clock end

CS. . . Current sensing terminal

D. . . Data side

DET. . . Voltage detection terminal

FB. . . Feedback side

I ₁ . . . First current

I ₂ . . . Second current

R. . . Reset end

R _M . . . Sampling resistor

Q. . . Output

S ₅₂ . . . output signal

S _C . . . control signal

S _L . . . Judgment signal

S _RT . . . Minimum off time signal

S _UNLOCK . . . Unlock signal

V _A . . . Reflected voltage signal

V _CC . . . power supply

V _FB . . . Feedback signal

V _G . . . Switching signal

V _M . . . Wave voltage signal

V _T1 . . . First threshold voltage

Claims (12)

A switching control circuit is applicable to a switching power converter, the switching control circuit is coupled to a switching switch and an auxiliary winding of a transformer, the switching control circuit comprises: a valley detecting circuit, receiving the auxiliary coil from the transformer One of the reflected voltage signals to output a control signal according to the reflected voltage signal; a valley lock circuit receiving the control signal to output a determination signal according to the control signal in a first period and a second period, wherein The second period is continued from the first period; and a pulse width modulation (PWM) circuit outputs a switching signal according to the determination signal. The switching control circuit of claim 1, further comprising: a minimum off time circuit, receiving a feedback signal to generate a minimum off time signal; and an unlocking circuit receiving the minimum off time signal and the control Signaling to generate an unlock signal; wherein the minimum off time signal is associated with the feedback signal, and the unlock signal is associated with the minimum off time signal and the control signal. The switching control circuit of claim 2, wherein the unlocking circuit comprises: a detecting circuit that receives the control signal to output a maximum voltage signal; A limiting circuit receives the minimum off time signal and the maximum voltage signal to generate the unlock signal. The switching control circuit of claim 2, wherein the minimum off time circuit comprises: a first comparator receiving the feedback signal and a threshold voltage for performing a comparison operation; and an inverter coupled An output of the first comparator; a first switch receiving the feedback signal and being controlled by an output of the first comparator; a second switch receiving the threshold voltage and receiving the reverse voltage through the inverter Controlled by the output of the first comparator; a third switch coupled to the first switch and the second switch and controlled by the switching signal; a current source and a capacitor coupled in series to a power supply and a ground a second comparator coupled to a common point between the current source and the capacitor, and receiving a reference voltage for comparison operation; and an OR gate coupled to the output of the second comparator and receiving The switching signal is to generate the minimum off time signal. The switching control circuit of claim 1, wherein the valley detecting circuit comprises: a switch coupled to the auxiliary coil of the transformer through a resistor to receive the resistor when the switch is turned off The reflected voltage signal; a first current mirror coupled to the switch to flow through one of the switches Converting a current into a second current; a sampling resistor coupled to the first current mirror to receive the second current and generating a peak voltage signal; and a comparator coupled to the sampling resistor to compare the peak voltage The signal is coupled to a threshold voltage and the control signal is output. The switching control circuit of claim 1, wherein the valley locking circuit comprises: a counter receiving the control signal to count the reflected voltage in each of the first period and the second period a number of troughs of the signal and a data is generated according to the counting result; a register coupled to the counter to store the data on the number of troughs of the reflected voltage signal in the first period; a subtractor coupled to the data a counter and the register for receiving the data about the number of troughs of the reflected voltage signal during the second period and the number of troughs of the reflected voltage signal during the first period, and The data about the number of troughs of the reflected voltage signal during the second period and the data about the number of troughs of the reflected voltage signal in the first period are subjected to a subtraction operation to generate a subtraction result data; and an arbiter receives the The subtraction result data is used to perform arbitration to generate the judgment signal. A switching power converter includes: a switch that is controlled by a switching signal; a transformer having a primary side coil and an auxiliary coil; and a switching control circuit coupled to the switching switch and the transformer An auxiliary coil, wherein the switching control circuit includes: a valley detecting circuit that receives a reflected voltage signal from one of the auxiliary coils of the transformer to output a control signal according to the reflected voltage signal, wherein the reflected voltage signal is When the switch is turned off, a resistor is generated, and the resistor is coupled to the auxiliary coil of the transformer; a valley lock circuit receives the control signal to output according to the control signal in a first period and a second period a determination signal, wherein the second period is subsequent to the first period; and a pulse width modulation (PWM) circuit coupled to the valley lock circuit to receive the determination signal, and according to the determination signal The switching signal is output to turn on the switching switch. The switching power converter of claim 7, wherein the switching control circuit further comprises: a minimum off time circuit, receiving a feedback signal to generate a minimum off time signal; and an unlocking circuit to receive the And a minimum off time signal and the control signal to generate an unlock signal; wherein the minimum off time signal is associated with the feedback signal, and the unlock signal is associated with the minimum off time signal and the control signal. The power converter of claim 8, wherein the unlocking circuit comprises: a detecting circuit that receives the control signal to output a maximum voltage signal; and a limiting circuit that receives the minimum off time signal and the Maximum electricity The signal is pressed to generate the unlock signal. The power converter of claim 8, wherein the minimum off time circuit comprises: a first comparator receiving the feedback signal and a threshold voltage for performing a comparison operation; and an inverter coupled An output of the first comparator; a first switch receiving the feedback signal and being controlled by an output of the first comparator; a second switch receiving the threshold voltage and receiving the reverse voltage through the inverter Controlled by the output of the first comparator; a third switch coupled to the first switch and the second switch and controlled by the switching signal; a current source and a capacitor coupled in series to a power supply and a ground a second comparator coupled to a common point between the current source and the capacitor, and receiving a reference voltage for comparison operation; and an OR gate coupled to the output of the second comparator and receiving The switching signal is to generate the minimum off time signal. The power converter of claim 7, wherein the valley detecting circuit comprises: a switch coupled to the auxiliary coil of the transformer through the resistor to receive the resistor when the switch is turned off The reflected voltage signal; a first current mirror coupled to the switch to convert a first current flowing through the switch to a second current; a sampling resistor coupled to the first current mirror to receive the second current and generate a peak voltage signal; and a comparator coupled to the sampling resistor to compare the peak voltage signal with a threshold voltage, and output the control signal. The power converter of claim 7, wherein the valley lock circuit comprises: a counter receiving the control signal to count the reflected voltage in each of the first period and the second period a number of troughs of the signal and a data is generated according to the counting result; a register coupled to the counter to store data on the number of troughs of the reflected voltage signal in the first period; a subtractor coupled to the counter And the register to receive data on the number of troughs of the reflected voltage signal during the second period and the number of troughs in the first period with respect to the reflected voltage signal, and in the second period The data on the number of troughs of the reflected voltage signal and the data on the number of troughs of the reflected voltage signal in the first period are subjected to a subtraction operation to generate a subtraction result data; and an arbiter receives the subtraction result data to Arbitration is performed to generate the determination signal.