TWI414926B - Controlling device and related controlling method - Google Patents

Abstract

A controlling device includes: a first delay circuit having a first delay time for selectively delaying one of a first input clock and a second input clock to generate an output clock for a storage device according to a selecting signal; a second delay circuit for delaying the selecting signal by a second delay time to generate a second delayed selecting signal; a first controlling circuit for selectively accessing the storage device according to the second delayed selecting signal; a third delay circuit for delaying the selecting signal by a third delay time to generate a third delayed selecting signal; and a second controlling circuit for selectively accessing the storage device according to the third delayed selecting signal.

Description

Control device and related control method

The present invention relates to a control device and related control method thereof, and more particularly to a control device for a first-in first-out memory and a related control method thereof.

In an access system, a storage device, such as a One-port FIFO memory, is typically assigned to control circuits having different clock characteristics (eg, different clock frequencies or duty cycles). The action to access. Taking the 單埠 first-in first-out memory as an example, an input/output port of the 單埠 first-in first-out memory must often switch between different control circuits. However, in the process of switching, in order to avoid the generation of the clock burst signal (Glitch), the firmware of the conventional access system performs a protection mechanism to ensure that no burst signal is generated. Further, when a first control circuit having a first clock is accessing the first-in first-out memory, the firmware is to be switched to access (use) the first-in first-out memory. The circuit switches the circuit for accessing (using) the first-in first-out memory from the first control circuit to a second control circuit. The first control circuit has a first control clock and the second control circuit has a second control clock. At this time, the firmware of the conventional access system inputs the first input of the first-in first-out memory. The control clock is switched to the second control clock. Then, the firmware will count the specific delay time before controlling the second control circuit to start accessing the first-in first-out memory. In other words, the specific delay time must be long enough to ensure that the first control clock received by the first-in first-out memory successfully switches to the second control clock, and the second control circuit begins to save. Take the 單埠 first-in first-out memory to avoid clock burst signals. However, when the clock frequency of the first control clock and the second control clock is a high frequency, the cycle time thereof is relatively reduced, so the first control clock is switched to the second control clock. The time required is also reduced. However, if the specific delay time remains unchanged at this time, the specific delay time is too long to waste unnecessary time, thereby slowing down a control circuit to access a first-in first-out memory. speed. Therefore, how to adjust the specific delay time to improve the speed of accessing a first-in first-out memory by a control circuit has become an urgent problem to be solved by an access system.

Accordingly, an embodiment of the present invention provides a control device for a first-in first-out memory and associated control method thereof to solve the problems faced by the prior art.

According to a first embodiment of the invention, a control device is provided. The control device includes a first delay circuit, a second delay circuit, a first control circuit, a third delay circuit, and a second control circuit. The first delay circuit has a first delay amount and is configured to selectively delay one of a first input clock and a second input clock to generate an output clock to a storage device according to a selection signal. The second delay circuit is coupled to the first delay circuit and configured to delay the selection signal by a second delay amount to generate a second delay selection signal. The first control circuit is coupled to the first input clock and coupled to the second delay circuit, and is configured to selectively access the storage device according to the second delay selection signal. The third delay circuit is coupled to the first delay circuit and configured to delay the selection signal by a third delay amount to generate a third delay selection signal. The second control circuit is coupled to the second input clock and coupled to the third delay circuit, and is configured to selectively access the storage device according to the third delay selection signal.

According to a second embodiment of the present invention, a control method is provided. The control method includes the steps of: selectively delaying one of a first input clock and a second input clock to generate an output clock to a storage device according to a selection signal; delaying the selection signal by one a second delay amount to generate a second delay selection signal; instructing a first control circuit to selectively access the storage device according to the second delay selection signal; delaying the selection signal by a third delay amount to generate a And delaying the selection signal; and instructing a second control circuit to selectively access the storage device according to the third delay selection signal.

Certain terms are used throughout the description and following claims to refer to particular elements. Those of ordinary skill in the art should understand that a hardware manufacturer may refer to the same component by a different noun. The scope of this specification and the subsequent patent application do not use the difference of the names as the means for distinguishing the elements, but the difference in function of the elements as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection means. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the device. The second device is indirectly electrically connected to the second device through other devices or connection means.

Please refer to Figure 1. Figure 1 is a schematic illustration of one embodiment of a control device 100 in accordance with the present invention. The control device 100 includes a first delay circuit 101, a second delay circuit 102, a first control circuit 103, a third delay circuit 104, a second control circuit 105, and a selection circuit 106.

The first delay circuit 101 has a first delay amount D1 for selectively delaying one of the first input clock C1 and the second input clock C2 according to a selection signal Ss to generate an output clock Cout. To a storage device 107.

The second delay circuit 102 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a second delay amount D2 to generate a second delay selection signal Ssd2. The first control circuit 102 operates on the first input clock C1 and is coupled to the second delay circuit 102 for selectively accessing the storage device 107 according to the second delay selection signal Ssd2.

The third delay circuit 104 is coupled to the first delay circuit 101 for delaying the selection signal Ss by a third delay amount D3 to generate a third delay selection signal Ssd3. The second control circuit 105 is operative to the second input clock C2 and coupled to the third delay circuit 104 for selectively accessing the storage device 107 according to the third delay selection signal Ssd3.

The selection circuit 106 is coupled to the first delay circuit 101, the second delay circuit 102, the third delay circuit 104, the first control circuit 103, and the second control circuit 105 for generating a number according to the first control circuit 103. A control signal Sc1 and a second control signal Sc2 generated by the second control circuit 105 generate the selection signal Ss to the first delay circuit 101, the second delay circuit 102, and the third delay circuit 104. In the present embodiment, the storage device 107 is implemented in a first-in-first-out (FIFO) memory, which is not a limitation of the present invention.

The first delay circuit 101 includes an AND gate 101a, 101b, 101c, 101d, a D-Flip-Flop 101e, 101f, 101g, 101h, an OR Gate 101i, and a Inverter 101j. The D-type flip-flops 101e, 101f are connected in series with each other for providing a delay amount 1.5Ta according to the first input clock C1, wherein Ta is the period of the first input clock C1. The D-type flip-flops 101g, 101h are connected in series to provide a delay amount of 1.5 Tb according to the second input clock C2, wherein Tb is the period of the second input clock C2. An input terminal N1 of the gate 101a is used to receive the selection signal Ss, and an output terminal N2 is coupled to an input terminal of the D-type flip-flop 101e. A positive phase output terminal N3 of the D-type flip-flop 101f is coupled to an input terminal of the AND gate 101c. The other input terminal N4 of the gate 101c receives the first input clock C1. In addition, the inverter 101j is coupled between the input terminal N1 and an input terminal N5 of the AND gate 101b. The other input terminal N6 of the gate 101b is coupled to an inverting output terminal of the D-type flip-flop 101f, and an output terminal N7 of the gate 101b is coupled to an input terminal of the D-type flip-flop 101g. A positive phase output terminal N8 of the D-type flip-flop 101h is coupled to an input terminal of the AND gate 101d. The other input terminal N9 of the AND gate 101d receives the second input clock C2. The respective output terminals N10 and N11 of the gate 101c and the gate 101d are respectively coupled to the two input ends of the OR gate 101i. The output terminal N12 of the OR gate 101i is used to output the output clock Cout. Please note that the detailed connection relationship of the first delay circuit 101 is referred to in FIG. 1 of the present invention, and will not be further described herein.

Due to the structure of the first delay circuit 101, the first control signal Sc / the second control signal Sc2 is generated from the first control circuit 103 / the second control circuit 105 to indicate that the storage device 107 is to be accessed (used) until the storage device 107 After receiving the changed output clock Cout, a total delay of 1.5 Ta + 1.5 Tb will be required. Since the clock burst signal (Glitch) is often generated when switching the clock, in order to prevent the storage device 107 from receiving the clock signal with the clock burst signal, the first delay circuit 101 is delayed for a period of time (for example, 1.5Ta+1.5Tb), the clock signal after the frequency change is stabilized and then input to the storage device 107. The first delay circuit 101 shown in FIG. 1 is merely an exemplary embodiment, and is not a limitation of the present invention. Those skilled in the art will be able to change the D in the first delay circuit 101 under the teaching of the present invention. The number of flip-flops is implemented, and the first delay circuit 101 is implemented in various variations, for example, a first delay circuit 101 of 2.5 Ta + 1.5 Tb can be generated or a 2.5 Ta + 2.5 Tb first delay circuit 101 can be generated.

The second delay circuit 102 includes a plurality of first specific delay units that are connected in series to provide a delay amount. In this embodiment, the plurality of first specific delay units include a first delay unit 1022 and a second delay unit 1024, wherein the first delay unit 1022 operates under the second input clock C2, and the second delay Unit 1024 operates below the first input clock C1. The first delay unit 1022 includes D-type flip-flops 1022a, 1022b that are connected in series to provide a delay amount 2Tb. The second delay unit 1024 includes D-type flip-flops 1024a, 1024b which are connected in series to provide a delay amount 2Ta. Please note that the serial sequence of the D-type flip-flops 1022a, 1022b, 1024a, 1024b in this embodiment is for illustrative purposes only, and is not a limitation of the present invention. The D-type flip-flops 1022a, 1022b, 1024a, 1024b The concatenation sequence can be adjusted arbitrarily. In the present embodiment, the sum of the delay amounts of the first delay unit 1022 and the second delay unit 1024 is substantially equal to the second delay amount D2, that is, 2Ta+2Tb=D2. In other words, the second delay circuit 102 is configured to provide the delay amount 2Ta+2Tb to the selection signal Ss, and the second delay selection signal Ssd2 generated after the delay is outputted to an output terminal N13 of the D-type flip-flop 1024b.

On the other hand, the third delay circuit 104 includes a plurality of second specific delay units which are connected in series to provide a delay amount. In this embodiment, the plurality of second specific delay units include a third delay unit 1042 and a fourth delay unit 1044, wherein the third delay unit 1042 operates under the first input clock C1, and the fourth delay Unit 1044 operates below the second input clock C2. The third delay unit 1042 includes D-type flip-flops 1042a, 1042b that are connected in series to provide a delay amount 2Ta. The fourth delay unit 1044 includes D-type flip-flops 1044a, 1044b that are connected in series to provide a delay amount 2Tb. Please note that the serial sequence of the D-type flip-flops 1042a, 1042b, 1044a, 1044b in this embodiment is for illustrative purposes only, and is not a limitation of the present invention. The D-type flip-flops 1042a, 1042b, 1044a, 1044b The concatenation sequence can be adjusted arbitrarily. In addition, the third delay circuit 104 of the present invention further includes an inverter 1046 coupled between the input terminal N1 and an input terminal N14 of the D-type flip-flop 1042a to generate an inverted selection signal Ssb according to the selection signal Ss. . In the present embodiment, the sum of the delay amounts of the third delay unit 1042 and the fourth delay unit 1044 is substantially equal to the third delay amount D3, that is, 2Ta+2Tb=D3. In other words, the third delay circuit 104 is configured to provide the delay amount 2Ta+2Tb to the inverted selection signal Ssb, and output the third delay selection signal Ssd3 generated after the delay to an output terminal of the D-type flip-flop 1044b. N15. It should be noted that the present invention does not limit the coupling manner of the inverter 1046. In other words, as long as it is serially connected to the third delay unit 1042 and the fourth delay unit 1044, it is within the scope of the present invention. For example, the inverter 1046 can also be coupled between the fourth delay unit 1044 and the second control circuit 105.

In addition, the selection circuit 106 of the embodiment includes a first toggle circuit 1062, a second touch circuit 1064, and a logic gate 1066. The first thixotropic circuit 1062 is operated under the first input clock C1 for thixo-switching a first thixotropic output signal St1 according to the first control signal Sc1. The second thixotropic circuit 1064 is operated under the second input clock Sc2 for thiking a second thixotropic output signal St2 according to the second control signal Sc2. The logic gate 1066 is coupled to the first thixotropic circuit 1062 and the second thixotropic circuit 1064 for generating the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. In the present embodiment, the logic gate 1066 is implemented as an exclusive OR gate.

Please refer to Figure 2. 2 is a selection signal Ss, a first input clock C1, a second input clock C2, a signal S1, a signal S2, a signal S3, a signal S4, a signal S5, a signal S6, and a first input clock S1 of the first delay circuit 101 of the embodiment of the present invention. The timing diagram of the signal S7, the signal S8, and the signal S9, wherein the signal S1 is the signal of the output terminal N2 of the gate 101a, the signal S2 is the signal of the output terminal N16 of the D-type flip-flop 101e, and the signal S3 is the D-type positive and negative. The signal of the output terminal N3 of the device 101f, the signal S4 is the signal of the inverted output terminal N17 of the D-type flip-flop 101f, the signal of the signal S5 and the output terminal N7 of the gate 101b, and the signal S6 is the D-type flip-flop 101g. The signal of the output terminal N18, the signal S7 is the signal of the output terminal N8 of the D-type flip-flop 101h, the signal S8 is the signal of the inverted output terminal N19 of the D-type flip-flop 101h, and the output of the signal S9-series inverter 101j The signal of the end N5.

To further illustrate the spirit of the present invention, this embodiment assumes that the first input clock C1 is synchronized to the second input clock C2. When the selection signal Ss is switched from a low voltage level to a high voltage level at time T1, the signal S9 and the signal S5 are also switched from the high voltage level to the low voltage level. Since the D-type flip-flop 101g is a rising-edge triggered D-type flip-flop, the second input clock C2 triggers the D-type flip-flop 101g at time T2 to cause the signal S6 to switch from the high-voltage level to the Low voltage level. Then, since the D-type flip-flop 101h is a D-type flip-flop triggered by a falling edge, the second input clock C2 triggers the D-type flip-flop 101h at time T3 to switch the signal S7 from the high-voltage level. To this low voltage level. At the same time, the signal S8 of the D-type flip-flop 101h is switched from the low voltage level to the high voltage level, so that the signal S1 is switched from the low voltage level to the high voltage level. Similarly, the first input clock C1 triggers the D-type flip-flop 101e (the D-type flip-flop 101e is a D-type flip-flop triggered by a rising edge) at time T4 to switch the signal S2 from the low voltage level. To this high voltage level. Then, the first input clock C1 triggers the D-type flip-flop 101f at time T5 (the D-type flip-flop 101f is a D-type flip-flop triggered by a falling edge) to switch the signal S3 from the low voltage level to The high voltage level. Therefore, after time T5, the output signal of the gate 101d is at the low voltage level, and the output signal of the gate 101c is the first input clock C1. In other words, after time T5, the output clock Cout (i.e., the output of the OR gate 101i) is switched from the second input clock C2 to the first input clock C1.

On the other hand, please refer to FIG. 2 again, when the selection signal Ss is switched from the high voltage level to the low voltage level at time T6 (ie, the output clock Cout is to be switched from the first input clock C1 to The second input clock C2), the signal S1 also switches from the high voltage level to the low voltage level. Since the D-type flip-flop 101e is a rising-edge triggered D-type flip-flop, the first input clock C1 triggers the D-type flip-flop 101e at time T7 to switch the signal S2 from the high-voltage level to the Low voltage level. Then, since the D-type flip-flop 101f is a D-type flip-flop triggered by a falling edge, the first input clock C1 triggers the D-type flip-flop 101f at time T8 to switch the signal S3 from the high-voltage level. To this low voltage level. At the same time, the signal S4 of the D-type flip-flop 101f is switched from the low voltage level to the high voltage level, so that the signal S5 is switched from the low voltage level to the high voltage level. Similarly, the second input clock C2 triggers the D-type flip-flop 101g at time T9 to switch the signal S6 from the low voltage level to the high voltage level. Then, the second input clock C2 triggers the D-type flip-flop 101h at time T10 to switch the signal S7 from the low voltage level to the high voltage level. Therefore, after time T10, the output signal of the gate 101c is at the low voltage level, and the output signal of the gate 101d is the second input clock C2. In other words, after time T10, the output clock Cout (i.e., the output of the gate 101i) is switched from the first input clock C1 to the second input clock C2.

Furthermore, the delay unit formed by the D-type flip-flops 101g and 101h can be delayed by 1.5Tb for the signal S5, and the delay unit formed by the D-type flip-flops 101e and 101f can be delayed by 1.5Ta for the signal S1. Therefore, the first delay amount D1 of the first delay circuit 101 can have a delay time of 1.5 Ta + 1.5 Tb at the longest. In other words, when the selection signal Ss is switched from the low voltage level to the high voltage level, the delay time of the output clock Cout not exceeding 1.5Ta+1.5Tb for the longest time is switched from the second input clock C2. Enter the clock C1 for the first time. Conversely, when the selection signal Ss is switched from the high voltage level to the low voltage level, the delay time of the output clock Cout not exceeding 1.5 Ta+1.5 Tb for the longest time is switched from the first input clock C1 to the first Two input clocks C2. Therefore, when the selection signal Ss is switched from the low voltage level to the high voltage level, the first control circuit 103 can only access the storage device after the delay time (1.5Ta+1.5Tb) of the first delay circuit 101 is exceeded. When access is made 107, the storage device 107 (i.e., the output terminal N12) can avoid malfunction caused by the generation of the clock burst signal (Glitch). Please note that those skilled in the art, under the teachings of the present invention, may change the number and type of flip-flops (D-type flip-flops or other types of flip-flops) and triggers in the first delay circuit 101. The aspect (rising edge trigger or falling edge trigger) changes the delay time of the first delay circuit 101.

Therefore, for the selection signal Ss, the second delay circuit 102 of the present embodiment provides a delay time of 2Ta+2Tb to generate the second delay selection signal Ssd2. The first control circuit 103 accesses the storage device 107 according to the second delay selection signal Ssd2. As can be seen from FIG. 1, the D-type flip-flops 1022a, 1022b in the second delay circuit 102 provide a delay time of 2Tb, and the D-type flip-flops 1024a, 1024b provide a delay time of 2Ta, so The two delay circuits 102 provide a total delay time of 2Ta + 2Tb.

On the other hand, for the selection signal Ss, the third delay circuit 104 also provides a delay time of 2Ta+2Tb to generate the third delay selection signal Ssd3, which is caused by the second delay circuit 102, and therefore will not be further described. It should be noted that the present invention is not limited to the above embodiments, as long as the delay time provided by the second delay circuit 102 and the third delay circuit 104 is longer than the delay time provided by the first delay circuit 101. It is the scope of the present invention, that is, those skilled in the art, under the teachings of the present invention, when changing the number, type, and triggering pattern of the flip-flops in the second delay circuit 102 or the third delay circuit 104 To change the delay time of the first delay circuit 101. Therefore, after the first delay amount D1 (ie, 2Ta+2Tb), the second delay selection signal Ssd2 is switched from the low voltage level to the high voltage level to allow the first control circuit 103 to access the storage device 107. . Please note that after reading the above-mentioned technical contents, the general knowledge in this field should be able to understand the corresponding operation of the control device 100, that is, when the selection signal Ss is switched from a high voltage level to a low voltage level. The operation also has the advantages described above, and therefore will not be further described herein.

Please note that the second delay circuit 102, the third delay circuit 104, and the selection circuit 106 of the control device 100 of the present embodiment are pure hardware circuits. In other words, in an embodiment, the control device 100 can control the first control circuit 103 or the second control circuit 105 to access the storage device 107 without being through a firmware. Therefore, when the first control circuit 103 needs to access the storage device 107, the first control circuit 103 generates the first control signal Sc1 to the selection circuit 106 to generate the selection signal Ss. Similarly, when the second control circuit 105 needs to access the storage device 107, the second control circuit 105 generates the second control signal Sc2 to the selection circuit 106 to generate the selection signal Ss. For example, if the second control circuit 105 is accessing the storage device 107 and the first control circuit 103 is to access the storage device 107, the first control circuit 103 first generates the first control signal Sc1 to the first touch. The variable circuit 1062, wherein the first control signal Sc1 is a pulse signal, as shown in FIG.

FIG. 3 is a waveform timing diagram of the first control signal Sc, the second control signal Sc2, the first thixotropic output signal St1, the second thixotropic output signal St2, and the selection signal Ss of the control device 100 according to the embodiment of the present invention. When the first control circuit 103 generates the first control signal Sc1 at time To, the first thixotropic circuit 1062 is triggered by the first control signal Sc1 and the first thixotropic output signal St1 is from a low voltage at time Tx. The level is switched to a high voltage level. Then, the logic gate 1066 (that is, the mutex or gate) generates the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. Since the voltage level of the second thixotropic output signal St2 is the low voltage level at this time, the logic gate 1066 switches the selection signal Ss from the low voltage level to the high voltage level at time Tb. Then, the first delay circuit 101 performs the operation as shown in FIG. 2 to switch the output clock Cout from the second input clock C2 to the first input clock C1. After receiving the first delay amount D1 (that is, 2Ta+2Tb), the first control circuit 103 is allowed to access the storage device 107.

On the contrary, when the first control circuit 103 is accessing the storage device 107 and the second control circuit 105 is to access the storage device 107, the second control circuit 105 first generates the second control signal Sc2 to the second touch circuit. 1064, wherein the second control signal Sc2 is also a pulse signal, as shown in FIG. When the second control circuit 105 generates the second control signal Sc2 at time To', the second thixotropic circuit 1064 is triggered by the second control signal Sc2 and the second thixotropic output signal St2 is low from the time Ty. The voltage level is switched to a high voltage level. Since the voltage levels of the first thixotropic output signal St1 and the second thixotropic output signal St2 are at the high voltage level, the logic gate 1066 switches the selection signal Ss from the high voltage level to the time Ty. The low voltage level. Similarly, the first delay circuit 101 performs the operation as shown in FIG. 2 to switch the output clock Cout from the first input clock C1 to the second input clock C2. After receiving the first delay amount D1 (ie, 2Ta+2Tb), the second control circuit 105 is allowed to access the storage device 107. Therefore, the first control circuit 103 and the second control circuit 105 can be operated without the firmware according to the operation of the first thixotropic circuit 1062, the second thixotropic circuit 1064 and the logic gate 1066 in the selection circuit 106. Control to selectively access the storage device 107. Therefore, compared with the conventional storage device access system, the control device 100 of the present invention not only has a faster response time (also immediate pulse switching time), but also overcomes the problem of the clock burst signal.

Please refer to Figure 4. 4 is a schematic diagram of another embodiment of a first delay circuit 101 of the control device 100 of the present invention, the other embodiment being designated by reference numeral 201. The first delay circuit 201 includes gates 201a, 201b, 201c, 201d, D-type flip-flops 201e, 201f, a gate 201g, and an inverter 201h. The D-type flip-flop 101e provides a delay amount 0.5Ta' according to a first input clock C1', wherein Ta' is the period of the first input clock C1'. The D-type flip-flop 201f is for providing a delay amount of 0.5 Tb' according to a second input clock C2', wherein Tb' is the period of the second input clock C2'. An input terminal N1' of the gate 201a is for receiving a selection signal Ss', and an output terminal N2' is coupled to an input terminal of the D-type flip-flop 201e. A positive phase output terminal N3' of the D-type flip-flop 201e is coupled to an input of the AND gate 201c, and another input terminal N4' of the gate 201c receives the first input clock C1'. In addition, the inverter 201h is coupled between the input terminal N1' and an input terminal N5' of the AND gate 201b. The other input terminal N6' of the gate 201b is coupled to an inverting output terminal of the D-type flip-flop 201e, and an output terminal N7' of the gate 201b is coupled to an input terminal of the D-type flip-flop 201f. A positive phase output terminal N8' of the D-type flip-flop 201f is coupled to an input terminal of the AND gate 201d. The other input terminal N9' of the AND gate 201d receives the second input clock C2'. The output terminals N10' and N11' of the gate 201c and the gate 201d are respectively coupled to the two input terminals of the OR gate 201g. The output terminal N12' of the OR gate 201g is used to output the output clock Cout'. Referring to the operation of the first delay circuit 101, those skilled in the art should understand that the first delay circuit 201 can have a delay time of up to 0.5 Ta' + 0.5 Tb'. In other words, when the selection signal Ss' is switched from the low voltage level to the high voltage level, the output clock Cout' will not exceed 0.5 Ta'+0.5Tb' for the longest delay time from the second input. The clock C2' is switched to the first input clock C1'. Conversely, when the selection signal Ss' is switched from the high voltage level to the low voltage level, the output clock Cout' will not exceed 0.5 Ta' + 0.5 Tb' for the longest delay time from the first input clock. C1' switches to the second input clock C2'. Therefore, in the embodiment in which the first delay circuit 201 is used to construct the control device 100, when the selection signal Ss' is switched from the low voltage level to the high voltage level, as long as the first control circuit 103 can exceed 0.5. If the storage device 107 is accessed after the delay time of Ta'+0.5Tb', the storage device 107 (i.e., the output terminal N12) can avoid the problem caused by the clock burst signal (Glitch). In other words, in this embodiment, the second delay amount D2 of the second delay circuit 102 and the third delay amount D3 of the third delay circuit 103 are set to be longer than 0.5Ta'+0.5Tb' (for example, 1Ta'+1Tb') can avoid the generation of clock burst signals.

Please refer to Figure 5. Figure 5 is a flow chart showing an embodiment of a control method 500 in accordance with the present invention. In order to clarify the spirit of the present invention, the control method 500 is implemented by the control device 100 of the embodiment of FIG. 1, but the embodiments provided are not intended to limit the scope of the present invention. In addition, if the same result can be substantially achieved, it is not necessary to perform the sequence of steps in the flow shown in FIG. 5, and the steps shown in FIG. 5 do not have to be performed continuously, that is, other steps may also be performed. Insert it. The control method 500 includes the following steps: Step 501: generate at least one of the first control signal Sc1 and the second control signal Sc2; Step 502: respectively change the first according to the first control signal Sc1 or the second control signal Sc2 Step 503: generating a selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2, and skipping to step 504; step 504: selecting the signal according to the selection signal Ss delays one of the first input clock C1 and the second input clock C2 by a first delay amount D1 to generate an output clock Cout to the storage device 107; Step 505: delays the selection signal Ss by a second delay amount D2 Generating a second delay selection signal Ssd2; step 506: selectively accessing the storage device 107 according to the second delay selection signal Ssd2; step 507: delaying the selection signal Ss by a third delay amount D3 to generate a third delay selection signal Ssd3; Step 508: Selectively access the storage device 107 according to the third delay selection signal Ssd3.

In step 501, when a control circuit of the first control circuit 103 and the second control circuit 105 wants to access the storage device 107, the control circuit generates a control signal to the first thixotropic circuit 1062 or the first Two thixotropic circuit 1064. For example, when the first control circuit 103 wants to access the storage device 107, the first control circuit 103 generates a control signal Sc1 to the first thixotropic circuit 1062. When the second control circuit 105 wants to access the storage device 107, the second control circuit 105 generates a control signal Sc2 to the second touch circuit 1064. Then, the thixotropic circuit that is touched by the control signal switches the voltage level of the output signal (the first thixotropic output signal St1 or the second thixotropic output signal St2) (step 502). Next, in step 503, the logic gate 1066 generates the selection signal Ss according to the first thixotropic output signal St1 and the second thixotropic output signal St2. Correspondingly, the selection signal Ss can indicate which of the first control circuit 103 or the second control circuit 105 is to access the storage device 107. Referring to the operation description of the control device 100, the selection signal Ss passes through three delay circuits (i.e., the first delay circuit 101 (step 504), the second delay circuit 102 (step 505), and the third delay circuit 104 (step 507). ) respectively generating three output signals (ie, output clock Cout, second delay selection signal Ssd2, and third delay selection signal Ssd3), wherein the delay times of the second delay circuit 102 and the third delay circuit 104 (D2, D3) It is greater than the delay time (D1) of the first delay circuit 101. Next, if the output clock Cout is the first input clock C1, the first control circuit 103 starts to access the storage device 107 according to the instruction of the second delay selection signal Ssd2 (step 506). On the other hand, if the output clock Cout is the second input clock C2, the second control circuit 105 starts to access the storage device 107 according to the instruction of the third delay selection signal Ssd3 (step 508). Please note that the control device 100 generates three output signals (ie, the output clock Cout, the second delay selection signal Ssd2, and the third delay selection signal Ssd3) according to the selection signal Ss, wherein the second delay selection signal Ssd2 is used. When the first control circuit 103 is instructed to start accessing the storage device 107, the third delay selection signal Ssd3 is used to indicate when the second control circuit 105 begins to access the storage device 107. Under normal operation, when the second delay selection signal Ssd2 instructs the first control circuit 103 to access the storage device 107, the third delay selection signal Ssd3 instructs the second control circuit 105 not to access the storage device 107, and vice versa. Since the corresponding input clock has been transmitted to the storage device 107 earlier when the first control circuit 103 or the second control circuit 105 starts accessing the storage device 107, the storage device 107 can avoid the clock burst signal. The problem caused.

In summary, the control device 100 of the present invention and the control method 500 thereof can be implemented in a pure hardware circuit without using a firmware, compared to the conventional storage device access system. The fast response time (also the instant pulse switching time) also overcomes the problem of the burst signal.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Control device

101, 201. . . First delay circuit

102. . . Second delay circuit

103. . . First control circuit

104. . . Third delay circuit

105. . . Second control circuit

106. . . Selection circuit

107‧‧‧Storage device

101a, 101b, 101c, 101d, 201a, 201b, 201c, 201d‧‧‧ and gate

101e, 101f, 101g, 101h, 201e, 201f, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b‧‧‧D type flip-flop

101i, 201g‧‧‧ or gate

101j‧‧‧Inverter

1022‧‧‧First delay unit

1024‧‧‧second delay unit

1042‧‧‧3rd delay unit

1044‧‧‧4th delay unit

1062‧‧‧First thixotropic circuit

1064‧‧‧Second touch circuit

1066‧‧‧Logic gate

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of one embodiment of a control device of the present invention.

2 is a timing diagram of a selection signal, a first input clock, a second input clock, and a plurality of signals thereof in a first delay circuit of the present invention.

FIG. 3 is a waveform timing diagram of a first control signal, a second control signal, a first thixotropic output signal, a second thixotropic output signal, and the selection signal of the control device of the present invention.

Figure 4 is a schematic view showing another embodiment of the first delay circuit of one of the control devices of the present invention.

Figure 5 is a flow diagram of an embodiment of a control method in accordance with the present invention.

100. . . Control device

101. . . First delay circuit

102. . . Second delay circuit

103. . . First control circuit

104. . . Third delay circuit

105. . . Second control circuit

106. . . Selection circuit

107. . . Storage device

101a, 101b, 101c, 101d. . . Gate

101e, 101f, 101g, 101h, 1022a, 1022b, 1024a, 1024b, 1042a, 1042b, 1044a, 1044b. . . D-type flip-flop

101i. . . Gate

101j. . . inverter

1022. . . First delay unit

1024. . . Second delay unit

1042. . . Third delay unit

1044. . . Fourth delay unit

1062. . . First thixotropic circuit

1064. . . Second thixotropic circuit

1066. . . Logic gate

Claims (16)

A control device includes: a first delay circuit having a first delay amount for selectively delaying one of a first input clock and a second input clock to generate a signal according to a selection signal Outputting a clock to a storage device; a second delay circuit coupled to the first delay circuit for delaying the selection signal by a second delay amount to generate a second delay selection signal; a first control circuit, The first input clock is coupled to the second delay circuit for selectively accessing the storage device according to the second delay selection signal; a third delay circuit coupled to the first delay a circuit for delaying the selection signal by a third delay amount to generate a third delay selection signal; and a second control circuit, coupled to the second input clock and coupled to the third delay circuit, for The storage device is selectively accessed according to the third delay selection signal. The control device of claim 1, wherein the third delay selection signal does not allow the second control circuit to access the second delay selection signal when the first control circuit accesses the storage device Storage device. The control device of claim 1, wherein at least one of the second delay amount and the third delay amount is greater than the first delay amount. The control device of claim 1, wherein the second delay circuit comprises: a plurality of first specific delay units, which are connected in series to provide a delay amount, wherein the plurality of first specific delay units include At least a first delay unit and a second delay unit, wherein the first delay unit operates under the first input clock, and the second delay unit operates below the second input clock. The control device of claim 4, wherein the sum of the delay amounts of the first delay unit and the second delay unit is equal to the second delay amount. The control device of claim 1, wherein the third delay circuit package comprises: a plurality of second specific delay units connected in series to provide a delay amount, wherein the plurality of second specific delay units comprise There is at least a third delay unit and a fourth delay unit, wherein the third delay unit operates under the first input clock, and the fourth delay unit operates under the second input clock; and And an inverter connected in series to the delay unit of the plurality of second specific delay units. The control device of claim 6, wherein the sum of the delay amounts of the third delay unit and the fourth delay unit is equal to the third delay amount. The control device of claim 1, further comprising: a selection circuit coupled to the first delay circuit, the second delay circuit, the third delay circuit, the first control circuit, and the The second control circuit is configured to generate the selection signal to the first delay circuit according to a first control signal generated by the first control circuit and a second control signal generated by the second control circuit, and the second delay a circuit and the third delay circuit. The control device of claim 8, wherein the second delay circuit, the third delay circuit, and the selection circuit are pure hardware circuits. The control device of claim 8, wherein the selection circuit comprises: a first toggle circuit controlled by the first input clock for touching according to the first control signal Changing a first thixotropic output signal; a second thixotropic circuit controlled by the second input clock for igniting a second thixotropic output signal according to the second control signal; and a logic gate The first thixotropic circuit and the second thixotropic circuit are coupled to generate the selection signal according to the first thixotropic output signal and the second thixotropic output signal. The control device of claim 10, wherein the logic gate is an exclusive OR gate. A control method includes: selectively delaying one of a first input clock and a second input clock to generate an output clock to a storage device according to a selection signal; delaying the selection signal by one a delay amount to generate a second delay selection signal; instructing a first control circuit to selectively access the storage device according to the second delay selection signal; delaying the selection signal by a third delay amount to generate a third Delaying the selection signal; and instructing a second control circuit to selectively access the storage device according to the third delay selection signal. The control method of claim 12, wherein when the second delay selection signal indicates that the first control circuit allows access to the storage device, the third delay selection signal indicates that the second control circuit is not allowed to save. Take the storage device. The control method of claim 12, wherein at least one of the second delay amount and the third delay amount is greater than the first delay amount. The control method of claim 12, further comprising: generating the selection signal according to a first control signal and a second control signal. The control method of claim 15, wherein the step of generating the selection signal according to the first control signal and the second control signal comprises: Typing a first thixotropic output signal according to the first control signal; stroking a second thixotropic output signal according to the second control signal; and according to the first thixotropic output signal and the second thixotropic output Signal to generate the selection signal.