TWI414186B - Dct/idct circuit - Google Patents

Abstract

A DCT/IDCT circuit includes a microcode memory, a controller, and a butterfly operation circuit. The microcode memory is operable to store a plurality of microcode lists corresponding to a plurality kinds of DCT/IDCT. The controller is operable to obtain one microcode corresponding to a DCT/IDCT from the microcode memory and control the butterfly operation circuit to operate a butterfly operation in the DCT/IDCT so as to operate the DCT/IDCT. The butterfly operation circuit includes a coefficient storing module, a selecting module, an operating module, and a result storing module. The coefficient storing module is operable to store coefficients of the butterfly operation. The result storing module is operable to store operation results of the butterfly operation. The selecting module is operable to select data from the coefficients or the operation results according to the obtained microcode and then output the selected data. The operating module is operable to operate the data according to the obtained microcode so as to obtain the operation results and then store the operation results in the result storing module.

Description

Discrete cosine transform and its inverse conversion circuit

The invention relates to video codec, in particular to a discrete cosine transform and an inverse conversion circuit thereof.

Discrete Cosine Transform and Inverse Discrete Cosine Transform (DCT/IDCT) are used in the encoding and decoding process of digital image data. In the process of digital image encoding, the image is usually subdivided into a number of 8*8 Pixel squares, and then discrete cosine transform (DCT) is performed on a pair of blocks to convert to a frequency domain (Frequency Domain) data form. And the decoding process performs inverse discrete cosine transform (IDCT) on the frequency domain data to be reduced to pixel data. Usually, performing a two-dimensional DCT/IDCT can be done by first performing a one-dimensional row or column transformation, and then performing a one-dimensional row or column conversion. These operations include a large number of butterfly operations.

At present, video coding and decoding protocols are of various types. For mainstream applications such as H.264, WMV9, MPEG-2, etc., DCT/IDCT operations are required for both encoding and decoding processes. However, the specific operation methods corresponding to various codec protocols are different. Since the actual completion of these operations is the underlying hardware circuit, correspondingly, various underlying hardware circuits of different designs are required to cooperate with various codec protocols. Based on market demand, all kinds of video products on the market need to support multiple codec protocols. Therefore, it is necessary to provide complex arithmetic circuits, which makes the underlying hardware circuits have the disadvantages of complicated design, large size and high cost.

In view of this, it is necessary to provide a Discrete Cosine Transform / Inverse Discrete Cosine Transform (DCT/IDCT) circuit for implementing various types of butterfly operations to simultaneously support multiple codec protocols and further improve Codec efficiency.

The DCT/IDCT circuit in the embodiment of the present invention is used to implement various types of DCT/IDCT. Each DCT/IDCT includes a complex butterfly operation, and each butterfly operation includes a complex operation coefficient. The DCT/IDCT circuit includes a microcode memory, a controller, and a butterfly operation circuit. The microcode memory is used to store a microcode list corresponding to the DCT/IDCT, wherein the microcode list includes multiple sets of microcodes, and each DCT/IDCT corresponds to a set of microcodes. The controller is configured to search the microcode group corresponding to the DCT/IDCT to be implemented from the microcode memory, and sequentially read the microcode therein. The butterfly operation circuit is used to perform a butterfly operation according to the microcode read by the controller to implement DCT/IDCT. The butterfly operation circuit includes a coefficient registration module, a selection input module, an operation module, and a result registration module. The coefficient registration module is used to store the operation coefficients of the butterfly operation. The result registration module is used to store the operation result of the butterfly operation. The input module is selected for outputting the operation coefficient stored in the module or the result stored in the result registration module according to the microcode selection coefficient read by the controller. The operation module is configured to calculate the data output by the input module according to the microcode read by the controller, and store the operation result in the result registration module.

The above and the technical effects of the invention can be easily understood from the following detailed description of the embodiments and the accompanying drawings.

Referring to FIG. 1, a block diagram of a Discrete Cosine Transform (Inverse Discrete Cosine Transform, DCT/IDCT) circuit 10 according to an embodiment of the present invention is shown.

In general, the DCT/IDCT included in various video codec protocols can be converted into a complex butterfly operation (Butterfly Operation), and the video codec protocol has detailed provisions for this, except for the specific video codec protocol. Butterfly operations are different. Therefore, if the efficiency of the butterfly operation is increased, the efficiency of the DCT/IDCT will also increase. Referring to FIG. 2, a schematic diagram of the 8*8 IDCT conversion of the WMV9 protocol into a complex butterfly operation is shown. Among them, C0, C1, ..., C7, etc. are operation coefficients of DCT/IDCT, and -3, 8, 3, -5, etc. are operation constants of DCT/IDCT, and D0, D1, ..., D7, etc. are calculation results of DCT/IDCT. The operation coefficients of the DCT/IDCT differ according to the parameters of the pixel block, and the operational constants of the DCT/IDCT are fixed for each DCT/IDCT. As can be seen from the figure, the 8*8 IDCT can be converted to a butterfly operation. The various IDCTs of other video codec protocols can also be converted into similar butterfly operations, since this conversion is a conventional technique and will not be described here.

It should be noted that FIG. 2 is only an example. The DCT/IDCT circuit 10 shown in the present invention is not only for the IDCT operation shown in FIG. 2, but can solve all IDCT operations, such as 2*2, 4*4, and the like. The DCT/IDCT circuit 10 shown in the present invention can support a variety of video codec protocols, such as H.264, MPEG-2, and the like.

Referring again to FIG. 1, in the present embodiment, the DCT/IDCT circuit 10 includes a microcode memory 12, a controller 13, and a butterfly operation circuit 14.

The microcode memory 12 is used to store a list of microcodes corresponding to the DCT/IDCT. In this embodiment, each type of video protocol corresponds to multiple types of DCT/IDCT, such as 2*2, 4*4, 8*8, and the like. Each DCT/IDCT corresponds to a set of microcodes. Since each video protocol specifies its corresponding DCT/IDCT and its butterfly operation, the microcode memory 12 stores a plurality of sets of microcodes to form a microcode list, and each set of microcodes includes a complex microcode. Each butterfly operation corresponds to at least one microcode. In the present embodiment, the microcode list is preset and stored in the microcode memory 12 in accordance with the video protocol.

The controller 13 is for reading the microcode from the microcode memory 12 and controlling the butterfly operation circuit 14 to perform a butterfly operation to implement DCT/IDCT.

In the present embodiment, the butterfly operation circuit 14 is configured to perform a butterfly operation based on the microcode, and includes a coefficient registration module 140, a selection input module 142, a calculation module 144, and a result registration module 146.

The coefficient registration module 140 is used to store the coefficients of the butterfly operation.

The result registration module 146 is used to store the results of the butterfly operation.

The selection input module 142 is configured to output the result of the butterfly operation stored in the coefficient registration module 140 or the result of the butterfly operation stored in the result registration module 146 according to the microcode selection.

The operation module 144 is configured to perform a butterfly operation on the data received from the selection input module 142 according to the microcode, and store the operation result in the result registration module 146 according to the microcode. In detail, the controller 13 controls the selection input module 142 to input specific data to the operation module 144 for a specific clock cycle for the operation module 144 to perform operations.

Referring to FIG. 3, a specific circuit diagram of an embodiment of the butterfly operation circuit 14 shown in FIG. 1 is shown. It should be noted that, in the drawings of the present invention, for the sake of simplicity and clarity, if the component names are identical, only one of them is identified, and is used to refer to all components having the same name. Moreover, since the arithmetic unit has the same structure, the detailed circuit of the partial arithmetic unit is omitted.

In the present embodiment, the selection input module 142 includes a complex multiplexer 1420 and a complex D flip-flop 1422.

The multiplexer 1420 is configured to select a coefficient of a butterfly operation stored in the output coefficient registration module 140 or a result of a butterfly operation stored in the result registration module 146. In the present embodiment, the multiplexer 1420 is further configured to select the operation result of the previous round of the output operation module 144 when the calculation module 144 performs a new round of calculation.

The D flip-flop 1422 is used to control the clock cycle of the output data of the multiplexer 1420 to synchronize the data input to the computing module 144. In the present embodiment, the controller 13 first sends a specific coefficient to the D flip-flop 1422 via the multiplexer 1420, and then sends it to the computing module 144 through the D flip-flop 1422 for a specific time period.

The arithmetic circuit 144 includes at least two arithmetic units 145. In the present embodiment, each arithmetic unit 145 includes a shifter 1450 and an adder-subtractor 1452.

The shifter 1450 is connected to the selection input module 142 for performing a shift operation on the data input by the selection input module 142. In the present embodiment, if the shifter 1450 shifts the input data to the left by n bits, it means that the input data is multiplied by 2 ⁿ , and if the data is shifted to the right by n bits, the input data is divided by 2 ^{n .} . For example, shifting 1 bit to the left means that the shifter 1450 multiplies the input data by 2, and if it shifts 2 bits to the left, it means multiplying the input data by 4, and if it shifts 3 bits to the left, it means Multiply the entered data by 8.

The first input end of the addition and subtraction unit 1452 is connected to the output end of the shifter 1450, and the second input end is connected to the selection input module 142 for outputting data to the output end of the shifter 1450, and selecting the input module 142. The input data is subjected to addition and subtraction, and the result is stored in the result registration module 146.

Please refer to FIG. 4, which is a schematic diagram of preparing a microcode according to a butterfly operation and performing a butterfly operation according to a microcode according to an embodiment of the present invention. In the present embodiment, each microcode includes an operation instruction, a result storage location, a complex data source, and a shift value.

The result storage location is used to indicate the storage location of the operation result output by the add/drop operator 1452 in the result registration module 146. In the present embodiment, the result storage location is set in advance, and the addition/subtraction unit 1452 stores the result in a predetermined area based on the instruction of the result storage location. For example, if the operation result needs to be stored in the first register, the result storage location can be set to r1. If the operation result needs to be stored in the second register, the result storage location can be set to r2.

The data source is used to indicate the source of the data computed by the computing module 144. In the present embodiment, the data source indicates the source of the data obtained by the shifter 1450 and the add/drop operator 1452 from the selection input module 142. The data input to the operation module 144 by the input module 142 includes two types, one is the operation coefficient of the DCT/IDCT that needs to be operated, and the other is the operation result stored in the result registration module 146. For example, if it is necessary to obtain the operation coefficient of the DCT/IDCT, the data source may be set as the output end of the corresponding D flip-flop 1422, and then the corresponding D flip-flop 1422 is controlled to output the required coefficient in a specific clock cycle, if necessary, As a result of the operation, the data source can be set to the result of the operation result, such as the first register.

The shift value is used to indicate the number of bits in which the shifter 1450 in the arithmetic module 144 shifts the data input by the select input module 142.

The operation instruction is used to instruct the operation module 144 to perform calculations on the data and the calculation rules on the data to be operated, including the shift direction, the complex operation data, and the complex operation rule. The arithmetic circuit 144 shifts the complex arithmetic data according to the shift value and the shift direction to obtain a shift result, and calculates the shift result and the complex arithmetic data according to the complex arithmetic rule. For example, the operation instruction may include a shift direction, a first operation data, a second operation data, a third operation data, a fourth operation data, a first operation rule, and a second operation rule. An operation data is first subjected to a shift operation according to the shift value and the shift direction, and then the result of the shift operation and the second operation data are operated according to the first operation rule, and the third operation data is first shifted according to the shift value. The bit direction is shifted, and the result of the shift operation and the fourth operation data are calculated according to the second operation rule.

The operation rule includes an operation that can be implemented by the operation unit 145, such as adding, subtracting, and finding the opposite number.

The operational data includes the information indicated by the source of the data. When the computing module 144 performs a new round of operations, the operational data further includes the operation result of the previous round of the operation of the computing module 144.

In this embodiment, a butterfly operation corresponds to at least one microcode. If the operation module 144 includes two operation units 145, it takes only one clock cycle to run each microcode. If the operation speed needs to be increased, only the operation needs to be increased. The number of units. As shown in FIG. 3, the operation module 144 includes four arithmetic units, and it takes one clock cycle to run every two microcodes, which significantly increases the operation speed. Moreover, the arithmetic unit 145 of the present invention uses a simple shifter 1450 instead of a complicated multiplier to implement the multiplication operation, which significantly reduces the complexity of the circuit and greatly reduces the cost.

For example, referring to the first butterfly operation BF1 shown in FIG. 4, the formula to be calculated can be expressed as R2=5C0+16C4 and R3=16C0-5C4, where C0 and C4 are the operation coefficients of DCT/IDCT, 5 and 16 are DCT/IDCT operation constants, R2 and R3 are the operation results of the first butterfly operation BF1, then the microcode can be written as: "Asl_rA_add_rA_rB_add_rB, rD0, RH, RL, 2" and "Asl_rA_add_DA_rB_sub_DB, rD1 , RL, RH, 4", wherein "Asl_rA_add_rA_rB_add_rB" and "Asl_rA_add_DA_rB_sub_DB" are operation instructions, rD0 and rD1 are the result storage places, RH and RL are data sources, and 2 and 4 are shift values. In the arithmetic instruction, Asl indicates that the shifter 1450 shifts the received data to the left, that is, multiplies the received data. rA and rB represent data obtained from data sources, and DA and DB represent the results of the previous clock cycle. rA_add_rA means that rA is shifted to the left by 2 bits, and the shift result is added to rA. rB_add_rB means that rB is shifted to the left by 2 bits, and the shift result is added to rB. The result of the operation is R0=(C0<<2)+C0=5C0, R1=(C4<<2)+C4=5C4. rA_add_DA means that rA is shifted to the left by 4 bits, and then the shift result is added to DA. rB_sub_DB means that rB is shifted to the left by 4 bits, and then the shift result is subtracted from DB, where DA and DB are the previous clock. The result of the cycle operation, here R0 and R1, results in an operation of R2=(C4<<4)+5C0=16C4+5C0, R3=(C0<<4)-5C4=16C0-5C4.

The second butterfly operation BF2 shown in Figure 4 is similar to the first butterfly operation BF1, where rB_isub_DB means that rB is shifted to the left and then the opposite is obtained, and then the result is added to the DB. The result of the operation is R5=-(C4<<4)+R1=-16C4+4C0.

Referring to FIG. 5, a flow chart of the controller 13 shown in FIG. 1 controlling the butterfly operation circuit 14 to perform a butterfly operation is shown. In the present embodiment, the butterfly operation is completed by the specific circuit shown in FIG. Wherein the shifter and the adder and subtracter in the first arithmetic unit are defined as a first shifter and a first adder-subtractor, and the shifter and adder-subtractor in the second arithmetic unit are defined as a second shift And the second adder-subtractor, where the arithmetic module 144 includes the two arithmetic units to illustrate how the butterfly operation circuit 14 performs the butterfly operation.

In step S500, the controller 13 finds the corresponding microcode group from the microcode memory 12 according to the type of DCT/IDCT to be performed, and sequentially reads a microcode in the microcode group. In the embodiment, the read microcode includes an operation instruction, a result storage place, a complex data source, and a shift value, and the operation instruction includes a shift direction, a first operation data, a second operation data, a third operation data, The fourth operational data, the first operational rule, and the second operational rule.

In step S502, the controller 13 controls the selection input module 142 to send the first operational data to the first shifter according to the read operation instruction of the microcode.

In step S504, the controller 13 controls the first shifter to perform a shift operation on the first operational data according to the shift value, and sends the operation result to the first input end of the first adder-subtracter.

In step S506, the controller 13 sends the second operational data to the second input of the first adder-subtracter according to the operation instruction in the microcode.

In step S508, the controller 13 controls the first adder-subtractor to calculate the data of the first input end and the second input end according to the first operation rule, and stores the operation result in the result storage place.

In step S510, the controller 13 controls the selection input module to send the third operation data to the second shifter according to the operation instruction of the microcode.

In step S512, the controller 13 controls the second shifter to perform a shift operation on the third operational data according to the shift value, and sends the operation result to the first input end of the second adder-subtracter.

In step S514, the controller 13 sends the fourth operational data to the second input of the second adder-subtracter according to the arithmetic instruction of the microcode.

In step S516, the controller 13 controls the second adder-subtractor to calculate the data of the first input end and the second input end according to the second operation rule, and stores the result in the result storage place.

Thus, when the controller 13 controls the butterfly operation circuit 14 to calculate all the microcodes in the microcode group, the DCT/IDCT operation corresponding to the group of microcodes is completed.

Since the operation module 144 includes at least two operation units 145, the two sets of operations S502-S508 and S510-S516 can be regarded as being synchronized, so that the operation performed according to one microcode can be regarded as being completed in one clock cycle. At this time, if the number of the operation units 145 can be doubled, the two microcodes can be synchronized, which further reduces the calculation time and improves the calculation efficiency.

In the present embodiment, according to the number of clock cycles required for the operation, the butterfly operations implemented by the embodiments of the present invention can be divided into three types according to the values of the operational constants of the DCT/IDCT. For details, refer to FIG. A schematic diagram of the type of butterfly operation described. The first type is a and b respectively or both, and such a butterfly operation corresponds to one microcode, and only two arithmetic units 145 are required to operate one clock cycle. The second category is 2 ⁿ or a 1/2 ^n, b is ^{2 n, 1/2 n,} 2 n ± 1 or 1/2 ⁿ ± 1, these corresponding to two butterfly microcode required two operations Unit 145 operates for two clock cycles. The other is the third class, corresponding to three microcodes, requiring two arithmetic units 145 to operate for three clock cycles. After statistics, if the required IDCT operation corresponds to the 8*8 IDCT operation specified by the WMV9 video protocol, then the number of butterfly operations in the first category accounts for 50% of the total, and the butterfly operation in the second category accounts for 28% of the total. Butterfly-like operations account for 22% of the total. If the IDCT operation to be performed corresponds to the 8*8 IDCT operation specified by the H.264 video protocol, the first type of butterfly operation accounts for 85% of the total, and the second type of butterfly operation accounts for 15% of the total. It can be seen that the DCT/IDCT circuit 10 can greatly improve the computational efficiency of the DCT/IDCT.

The DCT/IDCT circuit 10 provided by the embodiment of the present invention can realize all DCT/IDCT supporting all types of video protocols by converting different video protocols into different microcode groups and performing butterfly operations according to the microcode group. , greatly reducing the complexity of the hardware circuit required for DCT/IDCT. Moreover, since the shifting device is used in place of the multiplier in the conventional circuit to implement the multiplication operation, and the parallel operation is performed by the complex arithmetic unit, the circuit cost can be significantly reduced, and the operation speed can be greatly increased, and the operation can be greatly improved. efficacy.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims.

10‧‧‧Discrete cosine transform and its inverse conversion circuit

12‧‧‧ microcode memory

13‧‧‧ Controller

14‧‧‧Butter operation circuit

140‧‧‧ coefficient registration module

142‧‧‧Select input module

1420‧‧‧Multiplexer

1422‧‧‧D trigger

144‧‧‧ Computing Module

145‧‧‧ arithmetic unit

1450‧‧‧ shifter

1452‧‧‧Addition and Subtraction

146‧‧‧ Results Registration Module

1 is a block diagram of a DCT/IDCT circuit according to an embodiment of the present invention.

Figure 2 is a schematic diagram of the 8*8 IDCT of the WMV9 protocol converted to a complex butterfly operation.

3 is a detailed circuit diagram of an embodiment of the butterfly operation circuit shown in FIG. 1.

4 is a schematic diagram of a microcode based on a butterfly operation and a butterfly operation based on a microcode according to an embodiment of the present invention.

FIG. 5 is a flow chart of the controller shown in FIG. 1 controlling the butterfly operation circuit to perform a butterfly operation.

6 is a schematic diagram showing the types of butterfly operations performed in an embodiment of the present invention.

10‧‧‧Discrete cosine transform and its inverse conversion circuit

12‧‧‧ microcode memory

13‧‧‧ Controller

14‧‧‧Butter operation circuit

140‧‧‧ coefficient registration module

142‧‧‧Select input module

144‧‧‧ Computing Module

146‧‧‧ Results Registration Module

Claims (10)

A discrete cosine transform and inverse transform (DCT/IDCT) circuit for implementing multiple types of DCT/IDCT, each DCT/IDCT including a complex butterfly operation, each butterfly operation including a complex operation coefficient, the DCT/IDCT circuit including :
a microcode memory, configured to store a microcode list corresponding to the DCT/IDCT type, wherein the microcode list includes a complex array microcode, and each DCT/IDCT type corresponds to a set of microcodes;
a controller, configured to search for a microcode group corresponding to the DCT/IDCT to be implemented from the microcode memory, and sequentially read the microcode therein; and a butterfly operation circuit for reading the micro according to the controller The code performs a butterfly operation to implement the DCT/IDCT, wherein the butterfly operation circuit includes:
a coefficient registration module for storing an operation coefficient of the butterfly operation;
a result registration module, configured to store an operation result of the butterfly operation;
Selecting an input module, configured to select, according to the microcode read by the controller, the operation coefficient stored in the coefficient registration module or the operation result stored in the result registration module to output; and the operation module, The data output by the selection input module is calculated according to the microcode read by the controller, and the operation result is stored in the result registration module. The DCT/IDCT circuit of claim 1, wherein each microcode comprises:
An operation instruction for instructing the operation module to perform calculation on the data and an operation rule on the data;
a storage location for indicating a storage location of the operation result output by the computing module in the result registration module;
The plurality of data sources are used to indicate that the selection input module selects the data input to the operation module; and the shift value is used to indicate the number of bits that the operation module shifts the data input by the selection input module. The DCT/IDCT circuit of claim 2, wherein the operation instruction comprises:
a shifting direction, configured to indicate a direction in which the computing module shifts the data input by the selection input module;
The complex operation data is used to indicate the data that the operation module performs the operation; and the complex operation rule is used to instruct the operation performed by the operation module. The DCT/IDCT circuit of claim 3, wherein the operation rules include adding, subtracting, and finding opposite numbers. The DCT/IDCT circuit of claim 3, wherein the operational data includes data indicated by the data sources. The DCT/IDCT circuit according to claim 5, wherein the operation data further includes an operation result of the previous round operation of the operation module when the operation module performs a new round of operation. The DCT/IDCT circuit of claim 3, wherein the operation module is further configured to perform a shift operation on the operation data according to the shift value and the shift direction, and obtain a shift result according to the The operation rules operate the shift result with the operation data to obtain the operation result. The DCT/IDCT circuit of claim 1, wherein the operation module comprises at least two operation units, each operation unit comprising:
a shifter connected to the selection input module for performing a shift operation on the data input by the selection input module; and an addition and subtraction operator, the first input end of which is connected to the output end of the shifter, and the second The input end is connected to the selection input module, and is configured to perform addition and subtraction on the data input from the shifter and the data input by the selection input module according to the microcode selected by the controller, to obtain the operation result. The DCT/IDCT circuit of claim 1, wherein the selection input module comprises:
a complex multiplexer for selectively outputting the operation coefficient stored in the coefficient registration module or the operation result stored in the result registration module; and a complex D flip-flop for controlling output data of the multiplexer Clock cycle to synchronize the data it inputs into the computing module. The DCT/IDCT circuit according to claim 9, wherein the multiplexer is further configured to select an operation result of outputting the previous round operation of the operation module when the operation module performs a new round of calculation.