TWI412229B - Multi-channel integrator - Google Patents

Multi-channel integrator Download PDF

Info

Publication number
TWI412229B
TWI412229B TW98133829A TW98133829A TWI412229B TW I412229 B TWI412229 B TW I412229B TW 98133829 A TW98133829 A TW 98133829A TW 98133829 A TW98133829 A TW 98133829A TW I412229 B TWI412229 B TW I412229B
Authority
TW
Taiwan
Prior art keywords
input
channel
integrator
switch
coupled
Prior art date
Application number
TW98133829A
Other languages
Chinese (zh)
Other versions
TW201114180A (en
Inventor
Kai Lan Chuang
Guo Ming Lee
Ying Lieh Chen
Original Assignee
Himax Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Tech Ltd filed Critical Himax Tech Ltd
Priority to TW98133829A priority Critical patent/TWI412229B/en
Publication of TW201114180A publication Critical patent/TW201114180A/en
Application granted granted Critical
Publication of TWI412229B publication Critical patent/TWI412229B/en

Links

Landscapes

  • Electronic Switches (AREA)

Abstract

A multi-channel integrator is provided. The multi-channel integrator includes an integrator and a plurality of channels. Each of the channels includes an input selector and a unit-gain amplifier. The input selector has a common terminal, a first selecting terminal and a second selecting terminal. The input selector selectively electrically connects the common terminal to the first selecting terminal or the second selecting terminal. The first selecting terminal of the input selector is coupled to an input terminal of the integrator. The second selecting terminal of the input selector is coupled to an input terminal of the unit-gain amplifier.

Description

多通道積分器Multichannel integrator

本發明是有關於一種積分器,且特別是有關於一種多個通道的積分器。This invention relates to an integrator, and more particularly to an integrator for a plurality of channels.

隨著電子技術的蓬勃發展,以及無線通訊與網路的普及化,各式各樣的電子裝置逐漸成為生活不可或缺的工具。然而,一般常見的輸入與輸出(input/output,I/O)界面,像是鍵盤或是滑鼠,具有相當程度的操作困難。相形之下,觸控面板是一種直觀、簡單的輸入與輸出界面。因此,觸控面板常被應用作為人與電子裝置之間的人機界面,以執行控制。With the rapid development of electronic technology and the popularization of wireless communication and networks, various electronic devices have become an indispensable tool for life. However, common input/output (I/O) interfaces, such as keyboards or mice, have considerable operational difficulties. In contrast, the touch panel is an intuitive and simple input and output interface. Therefore, the touch panel is often applied as a human-machine interface between a person and an electronic device to perform control.

一般來說,觸控面板可以分為電阻式觸控面板、光學式觸控面板、電容式觸控面板等。若依讀取(readout)手段,則可分為電流式觸控面板(current type touch panel)與電荷式觸控面板(charge type touch panel)等。圖1說明電容式觸控面板(capacitor type touch panel)與傳統讀取電路(readout circuit)的示意圖。一般電容式觸控面板110的Y軸方向與X軸方向各自具有多條感測線(sensor line)。一條Y軸方向的感測線與一條X軸方向的感測線之間會形成一個耦合電容Cp。In general, the touch panel can be divided into a resistive touch panel, an optical touch panel, a capacitive touch panel, and the like. According to the readout means, it can be classified into a current type touch panel and a charge type touch panel. FIG. 1 illustrates a schematic diagram of a capacitive touch panel and a conventional readout circuit. Generally, the capacitive touch panel 110 has a plurality of sensor lines in the Y-axis direction and the X-axis direction. A coupling capacitor Cp is formed between a sensing line in the Y-axis direction and a sensing line in the X-axis direction.

每一條感測線均配置一個積分器120,而每一個積分器120均配置一個運算放大器122與一個回授電容Cfb。一開始所有運算放大器122的非反相輸入端接收0V的參考電壓Vref ,並且所有開關123均為導通(turn on),因此所有感測線均被充電至0V。接下來各個積分器120會將開關123截止(turn off),以便進行讀取操作。在開關123截止期間,假設沒有任何導電體(例如手指)接近觸控面板110,當參考電壓Vref 從0V轉態至5V時,Y軸方向與X軸方向的積分器120會使耦合電容Cp的二端電壓均為5V。由於不需對耦合電容Cp進行充放電,因此在參考電壓Vref 轉態至5V時,此變化會反應在積分器120的輸出上。在各個積分器120完成讀取操作後,所有開關123會再一次被導通,如此週而復始。Each of the sensing lines is provided with an integrator 120, and each integrator 120 is provided with an operational amplifier 122 and a feedback capacitor Cfb. Initially all non-inverting inputs of operational amplifier 122 receive a reference voltage Vref of 0V, and all switches 123 are turned on, so all sense lines are charged to 0V. Each of the integrators 120 then turns off the switch 123 for a read operation. During the off period of the switch 123, it is assumed that no conductor (for example, a finger) approaches the touch panel 110. When the reference voltage V ref is switched from 0 V to 5 V, the integrator 120 in the Y-axis direction and the X-axis direction causes the coupling capacitance Cp. Both terminals have a voltage of 5V. Since the coupling capacitor Cp is not required to be charged and discharged, this change is reflected at the output of the integrator 120 when the reference voltage Vref is shifted to 5V. After each integrator 120 completes the read operation, all of the switches 123 will be turned on again, so that they are repeated.

當導電體(例如手指)接近觸控面板110時,對應位置會形成額外的電容Cf(如圖1所示)。在開關123截止期間,當參考電壓Vref 從0V轉態至5V時,對應的積分器120需要經由感測線對額外電容Cf進行充放電。因此,在參考電壓Vref 轉態至5V時,額外電容Cf所對應積分器120的輸出OUT會發生變化,其公式為OUT=5+[(5V-0V)×Cfl/Cfb。積分器120將讀取(readout)結果交由後續電路(包含類比數位轉換器與影像處理電路,在此未繪示)判斷位置座標。藉由形成額外電容Cf的感測線所讀取信號與沒有額外電容Cf的感測線所讀取信號二者的不同,因此可以定位出被接觸的位置。When an electrical conductor (such as a finger) approaches the touch panel 110, an additional capacitance Cf (shown in FIG. 1) is formed at the corresponding position. During the off period of the switch 123, when the reference voltage V ref transitions from 0 V to 5 V, the corresponding integrator 120 needs to charge and discharge the additional capacitance Cf via the sensing line. Therefore, when the reference voltage V ref transitions to 5V, the output OUT of the integrator 120 corresponding to the additional capacitance Cf changes, and its formula is OUT=5+[(5V-0V)×Cfl/Cfb. The integrator 120 passes the readout result to a subsequent circuit (including an analog digital converter and an image processing circuit, not shown here) to determine the position coordinates. The difference between the signal read by the sensing line forming the additional capacitance Cf and the signal read by the sensing line without the additional capacitance Cf can thus locate the contacted position.

由上述公式可知,若是額外電容Cf越大則回授電容Cfb就得越大,否則很容易讓積分器120的輸出達到飽和(saturation)而判斷不出觸碰位置。然而,為了避免積分器120的輸出達到飽和,積分器120的回授電容Cfb也必須隨之增加電容量(即增加回授電容Cfb的面積)。由於每一條感測線需要一個積分器120,因此積分器120所佔的晶片面積將會很可觀。It can be seen from the above formula that if the extra capacitance Cf is larger, the feedback capacitance Cfb is larger, otherwise it is easy to make the output of the integrator 120 saturated and it is impossible to determine the touch position. However, in order to avoid saturation of the output of the integrator 120, the feedback capacitance Cfb of the integrator 120 must also increase the capacitance (i.e., increase the area of the feedback capacitance Cfb). Since each sense line requires an integrator 120, the area of the wafer occupied by the integrator 120 will be substantial.

本發明提供一種多通道積分器,以節省晶片面積。The present invention provides a multi-channel integrator to save wafer area.

本發明提出一種多通道積分器,包括一積分器以及多個通道。其中,每一個通道包括輸入選擇器以及單位增益放大器。輸入選擇器選擇性地將積分器的輸入端或參考電壓連接至輸入選擇器的共同端。The present invention provides a multi-channel integrator comprising an integrator and a plurality of channels. Each of the channels includes an input selector and a unity gain amplifier. An input selector selectively connects the input or reference voltage of the integrator to the common terminal of the input selector.

本發明提出一種多通道積分器,包括一積分器以及多個通道。每一個通道包括一輸入選擇器。輸入選擇器具有共同端、第一選擇端與第二選擇端,用以選擇性地將共同端電性連接至第一選擇端或第二選擇端。其中,輸入選擇器的第一選擇端耦接至積分器的輸入端,輸入選擇器的第二選擇端接收一參考電壓。The present invention provides a multi-channel integrator comprising an integrator and a plurality of channels. Each channel includes an input selector. The input selector has a common terminal, a first selection terminal and a second selection terminal for selectively connecting the common terminal to the first selection terminal or the second selection terminal. The first selection end of the input selector is coupled to the input end of the integrator, and the second selection end of the input selector receives a reference voltage.

在本發明之一實施例中,上述之積分器包括第一運算放大器、回授電容以及回授開關。第一運算放大器的第一輸入端做為該積分器的輸入端,第一運算放大器的第二輸入端接收該參考電壓,而第一運算放大器的輸出端做為該積分器的輸出端。回授電容的第一端與第二端分別耦接至第一運算放大器的第一輸入端與輸出端。回授開關的第一端與第二端分別耦接至第一運算放大器的第一輸入端與輸出端。In an embodiment of the invention, the integrator includes a first operational amplifier, a feedback capacitor, and a feedback switch. A first input of the first operational amplifier is used as an input of the integrator, a second input of the first operational amplifier receives the reference voltage, and an output of the first operational amplifier serves as an output of the integrator. The first end and the second end of the feedback capacitor are respectively coupled to the first input end and the output end of the first operational amplifier. The first end and the second end of the feedback switch are respectively coupled to the first input end and the output end of the first operational amplifier.

在本發明之一實施例中,當在第一通道期間時,上述回授開關為截止,該些通道中第一個通道的輸入選擇器選擇將其共同端電性連接至其第一選擇端,而該些通道中其餘通道的輸入選擇器選擇將其共同端電性連接至其第二選擇端。In an embodiment of the invention, when the feedback switch is turned off during the first channel, the input selector of the first channel of the channels selectively connects its common terminal to its first selection end. And the input selectors of the remaining channels in the channels select to electrically connect their common terminals to their second select terminals.

基於上述,藉由多個通道之間輪流共用一組積分器,因此可以大幅節省晶片面積,進而節省成本。Based on the above, by sharing a set of integrators in turn between a plurality of channels, the wafer area can be greatly saved, thereby saving costs.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

以下實施例將以電容式觸控面板(capacitor type touch panel)110為例,說明本發明之多通道積分器的應用方式。然而,本發明的應用範圍不應以此為限。任何電荷式觸控面板,甚至是任何需要多通道積分器的電路或是電子產品,均可以依據本說明書的教示而應用之。The following embodiment will illustrate the application of the multi-channel integrator of the present invention by taking a capacitive touch panel 110 as an example. However, the scope of application of the present invention should not be limited thereto. Any chargeable touch panel, even any circuit or electronic product that requires a multi-channel integrator, can be applied in accordance with the teachings of this specification.

圖2是依據本發明實施例說明一種多通道積分器的電路示意圖。此多通道積分器200具有n個通道210-1~210-n。圖中僅繪出第一個通道210-1與第n個通道210-n,其他通道可以參照第一個通道210-1的說明而類推之。除此之外,多通道積分器200尚具有積分器220。通道210-1~210-n之間輪流共用一組積分器220,因此可以大幅節省晶片面積,進而節省成本。以下將詳細說明通道210-1~210-n如何輪流使用這個積分器220。2 is a circuit diagram illustrating a multi-channel integrator in accordance with an embodiment of the present invention. This multi-channel integrator 200 has n channels 210-1~210-n. Only the first channel 210-1 and the nth channel 210-n are depicted in the figure, and other channels can be analogized with reference to the description of the first channel 210-1. In addition to this, the multi-channel integrator 200 still has an integrator 220. A set of integrators 220 is shared between the channels 210-1~210-n in turn, so that the wafer area can be greatly saved, thereby saving costs. The following will explain in detail how the channels 210-1~210-n use this integrator 220 in turn.

請參照圖2,於本實施例中,通道210-1~210-n的實現方式均相同。例如,通道210-1包括輸入選擇器211以及單位增益(unit-gain)放大器212。輸入選擇器211具有共同端、第一選擇端與第二選擇端,而單位增益放大器212的輸入端耦接至輸入選擇器211的第二選擇端。積分器220的輸入端耦接至所有通道210-1~210-n中輸入選擇器211的第一選擇端。在通道210-1中,輸入選擇器211的共同端耦接至觸控面板110的第一條感測線。在通道210-n中,輸入選擇器211的共同端耦接至觸控面板110的第n條感測線。通道210-1的輸入選擇器211受控於控制信號S1,而通道210-n的輸入選擇器211則受控於控制信號Sn。輸入選擇器211依據對應的控制信號而選擇將共同端電性連接至第一選擇端,或者是選擇將共同端電性連接至第二選擇端。Referring to FIG. 2, in the embodiment, the implementation manners of the channels 210-1~210-n are the same. For example, channel 210-1 includes an input selector 211 and a unit-gain amplifier 212. The input selector 211 has a common terminal, a first selection terminal and a second selection terminal, and an input terminal of the unity gain amplifier 212 is coupled to the second selection terminal of the input selector 211. The input of the integrator 220 is coupled to the first selection of the input selector 211 of all of the channels 210-1~210-n. In the channel 210-1, the common end of the input selector 211 is coupled to the first sensing line of the touch panel 110. In the channel 210-n, the common end of the input selector 211 is coupled to the nth sensing line of the touch panel 110. The input selector 211 of the channel 210-1 is controlled by the control signal S1, while the input selector 211 of the channel 210-n is controlled by the control signal Sn. The input selector 211 selectively connects the common terminal to the first selection terminal according to the corresponding control signal, or selectively connects the common terminal to the second selection terminal.

圖3是依據本發明實施例說明圖2中各控制信號S1~Sn的控制時序。請同時參照圖2與圖3,當系統於電源初通(power on)期間時,或是系統於重置(reset)期間,系統會將重置信號Reset設為致能(enable)狀態(例如為邏輯低準位)。當重置信號Reset為邏輯低準位時,所有通道210-1~210-n的輸入選擇器211選擇將該共同端電性連接至該第二選擇端,使得單位增益放大器212耦接至觸控面板110的感測線。FIG. 3 is a timing diagram showing control of each of the control signals S1 to Sn in FIG. 2 according to an embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time. When the system is in the power on period or during the system reset, the system resets the reset signal to the enable state (for example). It is a logic low level). When the reset signal Reset is at a logic low level, the input selectors 211 of all the channels 210-1~210-n select to electrically connect the common terminal to the second selection terminal, so that the unity gain amplifier 212 is coupled to the touch. The sensing line of the control panel 110.

當進入第一通道期間T1時,控制信號S1會轉態為邏輯高準位,而其他控制信號S2~Sn則維持在邏輯低準位。因此,在第一通道期間T1,第一個通道210-1的輸入選擇器211選擇將其共同端電性連接至其第一選擇端,而其餘通道(例如通道210-n)的輸入選擇器211選擇將其共同端電性連接至其第二選擇端。因此,在第一通道期間T1,通道210-1可以使用積分器220,而其餘通道便以其內部的單位增益放大器212的輸入端耦接至觸控面板110對應的感測線,以便擬替積分器的輸入端。When entering the first channel period T1, the control signal S1 will transition to the logic high level, while the other control signals S2~Sn remain at the logic low level. Thus, during the first channel period T1, the input selector 211 of the first channel 210-1 selects an input selector that electrically connects its common terminal to its first select terminal, while the remaining channels (eg, channel 210-n) 211 selects to electrically connect its common terminal to its second selection terminal. Therefore, during the first channel period T1, the channel 210-1 can use the integrator 220, and the remaining channels are coupled to the corresponding sensing lines of the touch panel 110 with the input ends of the internal unity gain amplifiers 212 to prepare the integrals. The input of the device.

當目前通道期間(例如第一通道期間T1)結束但尚未進入下一個通道期間(例如第二通道期間T2)時(相當於重置期間),系統會將重置信號Reset設為邏輯低準位,如圖3所示,此時控制信號S1會轉態為邏輯低準位。在此期間,所有通道210-1~210-n的輸入選擇器211選擇將該共同端電性連接至該第二選擇端,使得單位增益放大器212的輸入端耦接至觸控面板110的感測線。When the current channel period (for example, the first channel period T1) ends but has not yet entered the next channel period (for example, the second channel period T2) (equivalent to the reset period), the system sets the reset signal Reset to a logic low level. As shown in FIG. 3, at this time, the control signal S1 will transition to a logic low level. During this time, the input selectors 211 of all the channels 210-1~210-n select to electrically connect the common terminal to the second selection end, so that the input end of the unity gain amplifier 212 is coupled to the touch panel 110. Line measurement.

接著進入第二通道期間T2。在第二通道期間T2,控制信號S2會轉態為邏輯高準位,而其他控制信號S1、S3~Sn則維持在邏輯低準位。因此,第二個通道(圖2未繪示,可以通道210-1的相關說明而類推之)可以在第二通道期間T2使用積分器220,而其餘通道便以其內部的單位增益放大器212的輸入端耦接至觸控面板110對應的感測線,以便擬替積分器的輸入端。以此類推,在進入第n通道期間Tn時,第n個通道210-n可以使用積分器220,而其餘通道便以其內部的單位增益放大器212的輸入端耦接至觸控面板110對應的感測線。第二通道期間T2、第三通道期間T3、...、第n通道期間Tn的詳細操作可以參照第一通道期間T1的相關說明,故不再贅述。Then enter the second channel period T2. During the second channel period T2, the control signal S2 will transition to a logic high level, while the other control signals S1, S3~Sn remain at a logic low level. Therefore, the second channel (not shown in FIG. 2, which can be analogized by the description of channel 210-1) can use integrator 220 during the second channel period T2, while the remaining channels are united by its internal unity gain amplifier 212. The input end is coupled to the sensing line corresponding to the touch panel 110 to fit the input end of the integrator. By the way, when the nth channel period Tn is entered, the nth channel 210-n can use the integrator 220, and the remaining channels are coupled to the touch panel 110 with the input end of the internal unity gain amplifier 212. Sensing line. The detailed operation of the second channel period T2, the third channel period T3, ..., the nth channel period Tn can be referred to the related description of the first channel period T1, and therefore will not be described again.

後級電路(未繪示,其可以是類比數位轉換器與/或影像處理電路)耦接至積分器220的輸出端。因此,後級電路可以依序接收觸控面板110多條感測線的讀取信號,進而定位出觸控面板110中被接觸的位置。A subsequent stage circuit (not shown, which may be an analog digital converter and/or an image processing circuit) is coupled to the output of the integrator 220. Therefore, the subsequent stage circuit can sequentially receive the read signals of the plurality of sensing lines of the touch panel 110, thereby positioning the touched position of the touch panel 110.

圖4是依據本發明實施例說明另一種多通道積分器的電路示意圖。此多通道積分器400具有n個通道410-1~410-n。圖中僅繪出第一個通道410-1與第n個通道410-n,其他通道可以參照通道410-1說明而類推之。此實施例與圖2相似,故部分內容便不再贅述。圖4與圖2不同的地方在於通道內更配置了取樣開關413與取樣電容414。4 is a circuit diagram illustrating another multi-channel integrator in accordance with an embodiment of the present invention. This multi-channel integrator 400 has n channels 410-1~410-n. Only the first channel 410-1 and the nth channel 410-n are depicted in the figure, and other channels can be analogized with reference to channel 410-1. This embodiment is similar to FIG. 2, so some of the contents will not be described again. 4 is different from FIG. 2 in that the sampling switch 413 and the sampling capacitor 414 are further disposed in the channel.

請參照圖4,通道410-1至410-n的實現方式均相同。以下將以通道410-1作為說明範例。在通道410-1中,取樣開關413的第一端耦接至積分器220的輸出端。通道410-1至410-n的取樣開關413分別受控於控制信號SS1、SS2、SS3、...、SSn(請參照圖3)。取樣電容414的第一端耦接至取樣開關413的第二端,而取樣電容414的第二端接收第二參考電壓(例如為接地電壓)。Referring to FIG. 4, the implementations of the channels 410-1 to 410-n are the same. Channel 410-1 will be taken as an illustrative example below. In channel 410-1, the first end of sampling switch 413 is coupled to the output of integrator 220. The sampling switches 413 of the channels 410-1 to 410-n are respectively controlled by the control signals SS1, SS2, SS3, ..., SSn (please refer to FIG. 3). The first end of the sampling capacitor 414 is coupled to the second end of the sampling switch 413, and the second end of the sampling capacitor 414 receives the second reference voltage (eg, a ground voltage).

請同時參照圖3與圖4,當進入第一通道期間T1時,控制信號S1與SS1會轉態為邏輯高準位,而其他控制信號S2~Sn與SS2~SSn則維持在邏輯低準位。因此,在第一通道期間T1,第一個通道410-1的輸入選擇器211選擇將其共同端電性連接至其第一選擇端,而第一個通道410-1的取樣開關413為導通,因此積分器220的輸出會被儲存在取樣電容414。在第一通道期間T1,其餘通道(例如通道410-n)的輸入選擇器211選擇將其共同端電性連接至其第二選擇端,而取樣開關413為截止。以此類推,在進入第n通道期間Tn時,第n個通道410-n可以使用積分器220,並將積分器220的輸出儲存在通道410-n的取樣電容414。第二通道期間T2、第三通道期間T3、...、第n通道期間Tn的詳細操作可以參照第一通道期間T1的相關說明,故不再贅述。Please refer to FIG. 3 and FIG. 4 simultaneously. When entering the first channel period T1, the control signals S1 and SS1 will transition to the logic high level, while the other control signals S2~Sn and SS2~SSn remain at the logic low level. . Therefore, during the first channel period T1, the input selector 211 of the first channel 410-1 selects to electrically connect its common terminal to its first selection terminal, and the sampling switch 413 of the first channel 410-1 is turned on. Therefore, the output of the integrator 220 is stored in the sampling capacitor 414. During the first channel period T1, the input selector 211 of the remaining channels (e.g., channel 410-n) selects to electrically connect its common terminal to its second select terminal, while the sampling switch 413 is off. By analogy, when entering the nth channel period Tn, the nth channel 410-n can use the integrator 220 and store the output of the integrator 220 in the sampling capacitor 414 of the channel 410-n. The detailed operation of the second channel period T2, the third channel period T3, ..., the nth channel period Tn can be referred to the related description of the first channel period T1, and therefore will not be described again.

由於各通道410-1~410-n的取樣電容414已經存有觸控面板110多條感測線的讀取信號,因此後級電路(未繪示,其可以是類比數位轉換器與/或影像處理電路)可以讀取各個取樣電容414的信號,進而定位出觸控面板110中被接觸的位置。Since the sampling capacitor 414 of each channel 410-1~410-n already stores the read signals of the plurality of sensing lines of the touch panel 110, the subsequent circuit (not shown, which may be an analog digital converter and/or image) The processing circuit can read the signals of the respective sampling capacitors 414 to locate the contacts in the touch panel 110.

圖5是依據本發明實施例說明圖4中多通道積分器400的電路示意圖。請參照圖5,單位增益放大器212包括第二運算放大器OP2。運算放大器OP2的第一輸入端耦接至輸入選擇器211的第二選擇端,運算放大器OP2的第二輸入端接收參考電壓Vref ,而運算放大器OP2的輸出端耦接至運算放大器OP2的第一輸入端。在本實施例中,運算放大器OP2的第一輸入端為反相輸入端(inverting input),而運算放大器OP2的第二輸入端為非反相輸入端(non-inverting input)。FIG. 5 is a circuit diagram showing the multi-channel integrator 400 of FIG. 4 in accordance with an embodiment of the present invention. Referring to FIG. 5, the unity gain amplifier 212 includes a second operational amplifier OP2. The first input terminal of the operational amplifier OP2 is coupled to the second selection terminal of the input selector 211, the second input terminal of the operational amplifier OP2 receives the reference voltage V ref , and the output terminal of the operational amplifier OP2 is coupled to the operational amplifier OP2 An input. In this embodiment, the first input of the operational amplifier OP2 is an inverting input, and the second input of the operational amplifier OP2 is a non-inverting input.

另外,應用本實施例者可以視其設計需求而決定參考電壓Vref 的準位。例如,將參考電壓Vref 設定為系統電壓VDDA準位的一半(即VDDA/2),或是設定為能帶隙電壓(band-gap voltage),或是設定為+5V,或是設定為其他固定電壓。本實施例將參考電壓Vref 設定為響應於重置信號Reset的時變電壓。當重置信號Reset為邏輯低準位時,參考電壓Vref 為接地電壓(即0V)。在重置信號Reset轉態為邏輯高準位後,參考電壓Vref 會響應於重置信號Reset而轉態為系統電壓VDDA的一半(即VDDA/2,例如+5V)。In addition, the application of this embodiment can determine the level of the reference voltage V ref depending on its design requirements. For example, set the reference voltage V ref to half of the system voltage VDDA level (ie VDDA/2), or set to the band-gap voltage, or set to +5V, or set to other Fixed voltage. This embodiment sets the reference voltage V ref to a time varying voltage in response to the reset signal Reset. When the reset signal Reset is at a logic low level, the reference voltage V ref is a ground voltage (ie, 0V). After the reset signal Reset transitions to a logic high level, the reference voltage V ref transitions to half of the system voltage VDDA (ie, VDDA/2, eg, +5V) in response to the reset signal Reset.

請參照圖5,積分器220包括第一運算放大器OP1、回授電容Cfb以及回授開關SWfb。運算放大器OP1的第一輸入端耦接至所有通道410-1~410-n中輸入選擇器211的第一選擇端,而運算放大器OP1的第二輸入端接收參考電壓Vref 。在本實施例中,運算放大器OP1的第一輸入端為反相輸入端,而運算放大器OP1的第二輸入端為非反相輸入端。回授電容Cfb的第一端與第二端分別耦接至運算放大器OP1的第一輸入端與輸出端。回授開關SWfb的第一端與第二端亦分別耦接至運算放大器OP1的第一輸入端與輸出端。回授開關SWfb受控於信號ResetB,其中信號ResetB是重置信號Reset的反相信號。Referring to FIG. 5, the integrator 220 includes a first operational amplifier OP1, a feedback capacitor Cfb, and a feedback switch SWfb. The first input terminal of the operational amplifier OP1 is coupled to the first selection terminal of the input selector 211 of all the channels 410-1~410-n, and the second input terminal of the operational amplifier OP1 receives the reference voltage Vref . In this embodiment, the first input of the operational amplifier OP1 is an inverting input, and the second input of the operational amplifier OP1 is a non-inverting input. The first end and the second end of the feedback capacitor Cfb are respectively coupled to the first input end and the output end of the operational amplifier OP1. The first end and the second end of the feedback switch SWfb are also coupled to the first input end and the output end of the operational amplifier OP1, respectively. The feedback switch SWfb is controlled by a signal ResetB, wherein the signal ResetB is an inverted signal of the reset signal Reset.

請同時參照圖3與圖5,當系統於電源初通期間時,或是系統於重置期間,系統會將重置信號Reset設為邏輯低準位(即信號ResetB被設為邏輯高準位),使得回授開關SWfb為導通而重置回授電容Cfb。另外,由於控制信號S1~Sn均為邏輯低準位,使得全部通道410-1~410-n的輸入選擇器211選擇將觸控面板110的感測線電性連接至單位增益放大器212。Please refer to FIG. 3 and FIG. 5 simultaneously. When the system is in the initial state of the power supply, or during the reset period, the system will set the reset signal Reset to a logic low level (ie, the signal ResetB is set to a logic high level). ), the feedback switch SWfb is turned on to reset the feedback capacitor Cfb. In addition, since the control signals S1 SSn are all logic low levels, the input selectors 211 of all the channels 410-1~410-n select to electrically connect the sensing lines of the touch panel 110 to the unity gain amplifier 212.

當進入第一通道期間T1時,系統會將重置信號Reset設為邏輯高準位(即信號ResetB被設為邏輯低準位)以截止回授開關SWfb,使得積分器220可以進行積分操作。在此期間,控制信號S1會響應重置信號Reset而轉態為邏輯高準位,而其他控制信號S2~Sn則維持在邏輯低準位。因此,在第一通道期間T1,運算放大器OP1的反相輸入端電性連接至觸控面板110中第一個通道410-1所對應的感測線,而運算放大器OP1的輸出會被儲存在第一個通道410-1的取樣電容414。其餘通道(例如通道410-n)的單位增益放大器212電性連接至觸控面板110的其他感測線。When entering the first channel period T1, the system sets the reset signal Reset to a logic high level (ie, the signal ResetB is set to a logic low level) to turn off the feedback switch SWfb, so that the integrator 220 can perform an integration operation. During this period, the control signal S1 will transition to a logic high level in response to the reset signal Reset, while the other control signals S2~Sn remain at a logic low level. Therefore, during the first channel period T1, the inverting input terminal of the operational amplifier OP1 is electrically connected to the sensing line corresponding to the first channel 410-1 of the touch panel 110, and the output of the operational amplifier OP1 is stored in the first A sampling capacitor 414 of a channel 410-1. The unity gain amplifiers 212 of the remaining channels (eg, channels 410-n) are electrically coupled to other sense lines of the touch panel 110.

當目前通道期間(例如第一通道期間T1)結束但尚未進入下一個通道期間(例如第二通道期間T2)時(相當於重置期間),系統會將重置信號Reset設為邏輯低準位,如圖3所示,此時控制信號S1會轉態為邏輯低準位。在此期間,所有通道410-1~410-n的輸入選擇器211選擇將該共同端電性連接至該第二選擇端,使得單位增益放大器212耦接至觸控面板110的感測線。在積分器220中,信號ResetB控制回授開關SWfb為導通而重置回授電容Cfb。以此類推,在進入第n通道期間Tn時,第n個通道410-n可以使用積分器220,並將積分器220的輸出儲存在通道410-n的取樣電容414。第二通道期間T2、第三通道期間T3、...、第n通道期間Tn的詳細操作可以參照第一通道期間T1的相關說明,故不再贅述。When the current channel period (for example, the first channel period T1) ends but has not yet entered the next channel period (for example, the second channel period T2) (equivalent to the reset period), the system sets the reset signal Reset to a logic low level. As shown in FIG. 3, at this time, the control signal S1 will transition to a logic low level. During this period, the input selectors 211 of all the channels 410-1~410-n select to electrically connect the common terminal to the second selection terminal, so that the unity gain amplifier 212 is coupled to the sensing line of the touch panel 110. In the integrator 220, the signal ResetB controls the feedback switch SWfb to be turned on to reset the feedback capacitor Cfb. By analogy, when entering the nth channel period Tn, the nth channel 410-n can use the integrator 220 and store the output of the integrator 220 in the sampling capacitor 414 of the channel 410-n. The detailed operation of the second channel period T2, the third channel period T3, ..., the nth channel period Tn can be referred to the related description of the first channel period T1, and therefore will not be described again.

圖6是依據本發明另一實施例說明一種多通道積分器的電路示意圖。此實施例與圖5相似,故相同部分內容便不再贅述。圖6與圖5不同的地方在於各個通道內省去了單位增益放大器212。請參照圖6,多通道積分器600包括積分器220以及多個通道610-1~610-n。圖中僅繪出第一個通道610-1與第n個通道610-n,其他通道可以參照第一個通道610-1的說明而類推之。於本實施例中,通道610-1~610-n的實現方式均相同。以下將以通道610-1作為說明範例。通道610-1包括輸入選擇器211、取樣開關413與取樣電容414。在其他實施例中,取樣開關413與取樣電容414可能會被省略(類似於圖2所示)。6 is a circuit diagram illustrating a multi-channel integrator in accordance with another embodiment of the present invention. This embodiment is similar to FIG. 5, so the same portions will not be described again. The difference between FIG. 6 and FIG. 5 is that the unity gain amplifier 212 is omitted in each channel. Referring to FIG. 6, the multi-channel integrator 600 includes an integrator 220 and a plurality of channels 610-1~610-n. Only the first channel 610-1 and the nth channel 610-n are depicted in the figure, and other channels can be analogized with reference to the description of the first channel 610-1. In this embodiment, the implementations of the channels 610-1~610-n are the same. Channel 610-1 will be taken as an illustrative example below. Channel 610-1 includes an input selector 211, a sampling switch 413, and a sampling capacitor 414. In other embodiments, sampling switch 413 and sampling capacitor 414 may be omitted (similar to that shown in FIG. 2).

請參照圖6,輸入選擇器211的第一選擇端耦接至積分器220的輸入端,輸入選擇器211的第二選擇端接收參考電壓Vref 。依據控制信號S1的控制,通道610-1的輸入選擇器211選擇將共同端電性連接至第一選擇端,或者選擇將共同端電性連接至第二選擇端。因此,當控制信號S1為邏輯高準位時,通道610-1的輸入選擇器211選擇將觸控面板110的感測線電性連接至積分器220的輸入端。然後,當控制信號SS1為邏輯高準位時,通道610-1的取樣開關413將積分器220的輸出傳輸至取樣電容414。當控制信號S1為邏輯低準位時,通道610-1的輸入選擇器211選擇將觸控面板110的感測線電性連接至參考電壓Vref 。然後,控制信號SS1為邏輯低準位,而通道610-1的取樣開關413則會斷開。Referring to FIG. 6 , the first selection end of the input selector 211 is coupled to the input end of the integrator 220 , and the second selection end of the input selector 211 receives the reference voltage V ref . According to the control of the control signal S1, the input selector 211 of the channel 610-1 selectively connects the common terminal to the first selection terminal, or selectively connects the common terminal to the second selection terminal. Therefore, when the control signal S1 is at a logic high level, the input selector 211 of the channel 610-1 selects to electrically connect the sensing line of the touch panel 110 to the input of the integrator 220. Then, when the control signal SS1 is at a logic high level, the sampling switch 413 of the channel 610-1 transmits the output of the integrator 220 to the sampling capacitor 414. When the control signal S1 is at a logic low level, the input selector 211 of the channel 610-1 selects to electrically connect the sensing line of the touch panel 110 to the reference voltage V ref . Then, the control signal SS1 is at a logic low level, and the sampling switch 413 of the channel 610-1 is turned off.

圖7是依據本發明另一實施例說明圖6中輸入選擇器211的電路示意圖。於本實施例中,通道610-1~610-n的輸入選擇器211可以相同方式實現之。請參照圖7,通道610-1的輸入選擇器211包含第一反閘710、第二反閘720、第一及閘730、第二及閘740、第一開關750、第二開關760以及第三開關770。開關750~770的第一端耦接至觸控面板110中相對應的感測線。第三開關770的第二端耦接至積分器220。參考電壓Vref 包含高電壓Vref+ 與低電壓Vref- 。第二開關760的第二端耦接至高電壓Vref+ ,其中高電壓Vref+ 被設定為參考電壓Vref 的邏輯高準位(即VDDA/2)。第一開關750的第二端耦接至低電壓Vref- ,其中低電壓Vref- 被設定為參考電壓Vref 的邏輯低準位(即0V)。開關750~770分別受控於反閘710、及閘730與及閘740。FIG. 7 is a circuit diagram showing the input selector 211 of FIG. 6 according to another embodiment of the present invention. In this embodiment, the input selectors 211 of the channels 610-1~610-n can be implemented in the same manner. Referring to FIG. 7, the input selector 211 of the channel 610-1 includes a first reverse gate 710, a second reverse gate 720, a first AND gate 730, a second AND gate 740, a first switch 750, a second switch 760, and a Three switches 770. The first ends of the switches 750-770 are coupled to the corresponding sensing lines in the touch panel 110. The second end of the third switch 770 is coupled to the integrator 220. The reference voltage V ref includes a high voltage V ref+ and a low voltage V ref− . The second end of the second switch 760 is coupled to the high voltage V ref+ , wherein the high voltage V ref+ is set to a logic high level of the reference voltage V ref (ie, VDDA/2). The second end of the first switch 750 is coupled to the low voltage V ref− , wherein the low voltage V ref− is set to a logic low level (ie, 0V) of the reference voltage V ref . Switches 750-770 are controlled by reverse gate 710, and gate 730 and gate 740, respectively.

第一反閘710的輸入端接收重置信號Reset。第一反閘710的輸出端耦接至第一開關750的控制端。及閘730與及閘740的第一輸入端接收重置信號Reset。第二反閘720的輸出端耦接至第一及閘730的第二輸入端。第一及閘730的輸出端耦接至第二開關760的控制端。第二及閘740的輸出端耦接至第三開關770的控制端。在通道610-1中,第二反閘720的輸入端以及第二及閘740的第二輸入端接收控制信號S1。相似地,在通道610-n中第二反閘720的輸入端以及第二及閘740的第二輸入端接收控制信號Sn。The input of the first reverse gate 710 receives the reset signal Reset. The output end of the first reverse gate 710 is coupled to the control end of the first switch 750. The first input of the AND gate 730 and the AND gate 740 receives the reset signal Reset. The output of the second reverse gate 720 is coupled to the second input of the first AND gate 730. The output end of the first AND gate 730 is coupled to the control end of the second switch 760. The output end of the second AND gate 740 is coupled to the control end of the third switch 770. In channel 610-1, the input of the second reverse gate 720 and the second input of the second AND gate 740 receive the control signal S1. Similarly, the input of the second reverse gate 720 and the second input of the second AND gate 740 in the channel 610-n receive the control signal Sn.

請參照圖3與圖7,當系統將重置信號Reset設置為邏輯低準位時,第一開關750會導通而開關760與770會截止。當系統將重置信號Reset設置為邏輯高準位,且控制信號S1被設置為邏輯高準位時,第三開關770會導通而開關750與760會截止。當系統將重置信號Reset設置為邏輯高準位,且控制信號S1被設置為邏輯低準位時,第二開關760會導通而開關750與770會截止。Referring to FIG. 3 and FIG. 7, when the system sets the reset signal Reset to a logic low level, the first switch 750 is turned on and the switches 760 and 770 are turned off. When the system sets the reset signal Reset to a logic high level and the control signal S1 is set to a logic high level, the third switch 770 is turned on and the switches 750 and 760 are turned off. When the system sets the reset signal Reset to a logic high level and the control signal S1 is set to a logic low level, the second switch 760 is turned on and the switches 750 and 770 are turned off.

綜上所述,上述實施例藉由多個通道之間輪流共用一組積分器220。若多通道積分器的通道數n越大,節省晶片面積的效果越顯著,因此可以大幅節省晶片面積,進而節省成本。In summary, the above embodiment shares a set of integrators 220 by alternately between a plurality of channels. If the channel number n of the multi-channel integrator is larger, the effect of saving the wafer area is more remarkable, so that the wafer area can be greatly saved, thereby saving costs.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

110...觸控面板110. . . Touch panel

120、220...積分器120, 220. . . Integrator

Cfb...回授電容Cfb. . . Feedback capacitor

122、OP1、OP2...運算放大器122, OP1, OP2. . . Operational Amplifier

123...開關123. . . switch

200、400、600...多通道積分器200, 400, 600. . . Multichannel integrator

210-1、210-n、410-1、410-n、610-1、610-n...通道210-1, 210-n, 410-1, 410-n, 610-1, 610-n. . . aisle

211...輸入選擇器211. . . Input selector

212...單位增益放大器212. . . Unity gain amplifier

413...取樣開關413. . . Sampling switch

414...取樣電容414. . . Sampling capacitor

Cf...額外的電容Cf. . . Extra capacitor

Cp...耦合電容Cp. . . Coupling capacitor

Reset...重置信號Reset. . . Reset signal

S1~Sn...控制信號S1~Sn. . . control signal

SWfb...回授開關SWfb. . . Feedback switch

T1~Tn...通道期間T1~Tn. . . Channel period

Vref ...參考電壓V ref . . . Reference voltage

圖1說明電容式觸控面板與傳統讀取電路的示意圖。FIG. 1 illustrates a schematic diagram of a capacitive touch panel and a conventional read circuit.

圖2是依據本發明實施例說明一種多通道積分器的電路示意圖。2 is a circuit diagram illustrating a multi-channel integrator in accordance with an embodiment of the present invention.

圖3是依據本發明實施例說明圖2中各控制信號的控制時序。FIG. 3 is a timing diagram showing the control of each control signal in FIG. 2 according to an embodiment of the present invention.

圖4是依據本發明實施例說明另一種多通道積分器的電路示意圖。4 is a circuit diagram illustrating another multi-channel integrator in accordance with an embodiment of the present invention.

圖5是依據本發明實施例說明圖4中多通道積分器的電路示意圖。FIG. 5 is a circuit diagram showing the multi-channel integrator of FIG. 4 according to an embodiment of the invention.

圖6是依據本發明另一實施例說明一種多通道積分器的電路示意圖。6 is a circuit diagram illustrating a multi-channel integrator in accordance with another embodiment of the present invention.

圖7是依據本發明另一實施例說明圖6中輸入選擇器的電路示意圖。FIG. 7 is a circuit diagram showing the input selector of FIG. 6 according to another embodiment of the present invention.

110...觸控面板110. . . Touch panel

211...輸入選擇器211. . . Input selector

212...單位增益放大器212. . . Unity gain amplifier

220...積分器220. . . Integrator

400...多通道積分器400. . . Multichannel integrator

410-1、410-n...通道410-1, 410-n. . . aisle

413...取樣開關413. . . Sampling switch

414...取樣電容414. . . Sampling capacitor

Cp...耦合電容Cp. . . Coupling capacitor

S1~Sn...控制信號S1~Sn. . . control signal

Claims (23)

一種多通道積分器,包括:一積分器;以及多個通道,至少包括一第一通道與一第二通道,其中該第一通道包括一第一輸入選擇器以及一第一單位增益放大器;該第二通道包括一第二輸入選擇器以及一第二單位增益放大器;該第一輸入選擇器具有一共同端、一第一選擇端與一第二選擇端,用以選擇性地將該共同端電性連接至該第一選擇端或該第二選擇端;該第一輸入選擇器的共同端耦接至一觸控面板的一第一感測線;該第一單位增益放大器的輸入端耦接至該第一輸入選擇器的第二選擇端;該第二輸入選擇器具有一共同端、一第一選擇端與一第二選擇端,用以選擇性地將該共同端電性連接至該第一選擇端或該第二選擇端;該第二輸入選擇器的共同端耦接至該觸控面板的一第二感測線;該第二單位增益放大器的輸入端耦接至該第二輸入選擇器的第二選擇端;以及該第一輸入選擇器的第一選擇端與該第二輸入選擇器的第一選擇端共同耦接至該積分器的輸入端。 A multi-channel integrator comprising: an integrator; and a plurality of channels including at least a first channel and a second channel, wherein the first channel comprises a first input selector and a first unity gain amplifier; The second channel includes a second input selector and a second unity gain amplifier; the first input selector has a common terminal, a first selection terminal and a second selection terminal for selectively electrically connecting the common terminal The first input selector is coupled to a first sensing line of the touch panel; the input end of the first unity gain amplifier is coupled to the first terminal or the second terminal; a second selection end of the first input selector; the second input selector has a common end, a first selection end and a second selection end for selectively connecting the common end to the first a common terminal of the second input selector is coupled to a second sensing line of the touch panel; an input end of the second unity gain amplifier is coupled to the second input selector Second choice End; and the first input selector to select a first end and a second end of the first selection input selector coupled to the common input of the integrator. 如申請專利範圍第1項所述之多通道積分器,其中該積分器包括:一第一運算放大器,其中該第一運算放大器的第一輸入端做為該積分器的輸入端,該第一運算放大器的第二輸入端接收一參考電壓,而該第一運算放大器的輸出端做為該積分器的輸出端; 一回授電容,其第一端與第二端分別耦接至該第一運算放大器的第一輸入端與輸出端;以及一回授開關,其第一端與第二端分別耦接至該第一運算放大器的第一輸入端與輸出端。 The multi-channel integrator of claim 1, wherein the integrator comprises: a first operational amplifier, wherein a first input end of the first operational amplifier serves as an input of the integrator, the first The second input of the operational amplifier receives a reference voltage, and the output of the first operational amplifier serves as an output of the integrator; a feedback capacitor, the first end and the second end are respectively coupled to the first input end and the output end of the first operational amplifier; and a feedback switch, the first end and the second end are respectively coupled to the A first input and an output of the first operational amplifier. 如申請專利範圍第2項所述之多通道積分器,其中當在一電源初通期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該第二選擇端。 The multi-channel integrator of claim 2, wherein the feedback switch is turned on during a power-on initial period, and the input selectors of the channels selectively connect the common terminal to the Second choice. 如申請專利範圍第2項所述之多通道積分器,其中當在一重置期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該第二選擇端。 The multi-channel integrator of claim 2, wherein the feedback switch is turned on during a reset period, and the input selectors of the channels selectively connect the common terminal to the first Two selection ends. 如申請專利範圍第2項所述之多通道積分器,其中當在多個通道期間中的一通道期間時,該回授開關為截止,該些通道中一對應通道的輸入選擇器選擇將其共同端電性連接至其第一選擇端,而該些通道中其餘通道的輸入選擇器選擇將其共同端電性連接至其第二選擇端。 The multi-channel integrator of claim 2, wherein the feedback switch is turned off during one of the plurality of channel periods, and the input selector of a corresponding one of the channels selects The common terminal is electrically connected to its first selection terminal, and the input selectors of the remaining channels of the channels selectively connect their common terminals to their second selection terminals. 如申請專利範圍第1項所述之多通道積分器,其中當一目前通道期間結束但尚未進入下一個通道期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該第二選擇端。 The multi-channel integrator of claim 1, wherein the feedback switch is turned on when a current channel period ends but has not yet entered the next channel, and the input selectors of the channels select the common The terminal is electrically connected to the second selection end. 如申請專利範圍第2項所述之多通道積分器,其中該第一運算放大器的第一輸入端為反相輸入端,而該第一運算放大器的第二輸入端為非反相輸入端。 The multi-channel integrator of claim 2, wherein the first input of the first operational amplifier is an inverting input, and the second input of the first operational amplifier is a non-inverting input. 如申請專利範圍第1項所述之多通道積分器,其中該第一單位增益放大器包括一第二運算放大器,其中該第 二運算放大器的第一輸入端耦接至該第一輸入選擇器的第二選擇端,該第二運算放大器的第二輸入端接收一參考電壓,而該第二運算放大器的輸出端耦接至該第二運算放大器的第一輸入端。 The multi-channel integrator of claim 1, wherein the first unity gain amplifier comprises a second operational amplifier, wherein the The first input end of the second operational amplifier is coupled to the second selection end of the first input selector, the second input end of the second operational amplifier receives a reference voltage, and the output end of the second operational amplifier is coupled to a first input of the second operational amplifier. 如申請專利範圍第8項所述之多通道積分器,其中該第二運算放大器的第一輸入端為反相輸入端,而該第二運算放大器的第二輸入端為非反相輸入端。 The multi-channel integrator of claim 8, wherein the first input of the second operational amplifier is an inverting input, and the second input of the second operational amplifier is a non-inverting input. 如申請專利範圍第1項所述之多通道積分器,其中每一個通道更包括:一取樣開關,其第一端耦接至該積分器的輸出端;以及一取樣電容,其第一端耦接至該取樣開關的第二端,而該取樣電容的第二端接收一第二參考電壓。 The multi-channel integrator of claim 1, wherein each of the channels further comprises: a sampling switch having a first end coupled to the output of the integrator; and a sampling capacitor having a first end coupled Connected to the second end of the sampling switch, and the second end of the sampling capacitor receives a second reference voltage. 如申請專利範圍第10項所述之多通道積分器,其中當在多個通道期間中的一通道期間時,該些通道中一對應通道的取樣開關為導通,而該些通道中其餘通道的取樣開關為截止。 The multi-channel integrator of claim 10, wherein, during one of the plurality of channel periods, the sampling switches of a corresponding one of the channels are turned on, and the remaining channels of the channels are The sampling switch is cut off. 如申請專利範圍第1項所述之多通道積分器,其中該些通道中輸入選擇器的共同端分別耦接至一觸控面板中相對應的感測線。 The multi-channel integrator of claim 1, wherein the common ends of the input selectors of the channels are respectively coupled to corresponding sensing lines in a touch panel. 一種多通道積分器,包括:一積分器;以及多個通道,至少包括一第一通道與一第二通道,其中該第一通道包括一第一輸入選擇器;該第二通道包括一第 二輸入選擇器;該第一輸入選擇器選擇性地將該積分器的輸入端或一參考電壓透過該第一輸入選擇器的共同端耦接至一觸控面板的一第一感測線;以及該第二輸入選擇器選擇性地將該積分器的輸入端或該參考電壓透過該第二輸入選擇器的共同端耦接至該觸控面板的一第二感測線。 A multi-channel integrator includes: an integrator; and a plurality of channels including at least a first channel and a second channel, wherein the first channel includes a first input selector; the second channel includes a first a first input selector, the first input selector selectively coupling the input end of the integrator or a reference voltage to a first sensing line of a touch panel through a common end of the first input selector; The second input selector selectively couples the input end of the integrator or the reference voltage through a common end of the second input selector to a second sensing line of the touch panel. 如申請專利範圍第13項所述之多通道積分器,其中該積分器包括:一第一運算放大器,其中該第一運算放大器的第一輸入端做為該積分器的輸入端,該第一運算放大器的第二輸入端接收該參考電壓,而該第一運算放大器的輸出端做為該積分器的輸出端;一回授電容,其第一端與第二端分別耦接至該第一運算放大器的第一輸入端與輸出端;以及一回授開關,其第一端與第二端分別耦接至該第一運算放大器的第一輸入端與輸出端。 The multi-channel integrator of claim 13, wherein the integrator comprises: a first operational amplifier, wherein a first input end of the first operational amplifier is an input of the integrator, the first The second input end of the operational amplifier receives the reference voltage, and the output end of the first operational amplifier serves as an output end of the integrator; and a feedback capacitor, the first end and the second end are respectively coupled to the first end a first input end and an output end of the operational amplifier; and a feedback switch, wherein the first end and the second end are respectively coupled to the first input end and the output end of the first operational amplifier. 如申請專利範圍第14項所述之多通道積分器,其中當在一電源初通期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該參考電壓。 The multi-channel integrator of claim 14, wherein the feedback switch is turned on during a power-on initial period, and the input selectors of the channels selectively connect the common terminal to the Reference voltage. 如申請專利範圍第14項所述之多通道積分器,其中當在一重置期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該參考電壓。 The multi-channel integrator of claim 14, wherein the feedback switch is conductive when a reset period is selected, and the input selectors of the channels selectively connect the common terminal to the reference Voltage. 如申請專利範圍第14項所述之多通道積分器,其中當在多個通道期間中的一通道期間時,該回授開關為截止,該些通道中一對應通道的輸入選擇器選擇將其共同端 電性連接至該積分器的輸入端,而該些通道中其餘通道的輸入選擇器選擇將其共同端電性連接至該參考電壓。 The multi-channel integrator of claim 14, wherein the feedback switch is turned off during one of the plurality of channel periods, and the input selector of a corresponding one of the channels selects Common end Electrically connected to the input of the integrator, and the input selectors of the remaining channels of the channels selectively connect their common terminals to the reference voltage. 如申請專利範圍第14項所述之多通道積分器,其中當一目前通道期間結束但尚未進入下一個通道期間時,該回授開關為導通,而該些通道的輸入選擇器選擇將該共同端電性連接至該參考電壓。 The multi-channel integrator of claim 14, wherein the feedback switch is turned on when a current channel period ends but has not yet entered the next channel, and the input selectors of the channels select the common The terminal is electrically connected to the reference voltage. 如申請專利範圍第14項所述之多通道積分器,其中該第一運算放大器的第一輸入端為反相輸入端,而該第一運算放大器的第二輸入端為非反相輸入端。 The multi-channel integrator of claim 14, wherein the first input of the first operational amplifier is an inverting input, and the second input of the first operational amplifier is a non-inverting input. 如申請專利範圍第13項所述之多通道積分器,其中每一個通道更包括:一取樣開關,其第一端耦接至該積分器的輸出端;以及一取樣電容,其第一端耦接至該取樣開關的第二端,而該取樣電容的第二端接收一第二參考電壓。 The multi-channel integrator of claim 13, wherein each of the channels further comprises: a sampling switch having a first end coupled to the output of the integrator; and a sampling capacitor coupled to the first end Connected to the second end of the sampling switch, and the second end of the sampling capacitor receives a second reference voltage. 如申請專利範圍第20項所述之多通道積分器,其中當在多個通道期間中的一通道期間時,該些通道中一對應通道的取樣開關為導通,而該些通道中其餘通道的取樣開關為截止。 The multi-channel integrator of claim 20, wherein when one of the plurality of channel periods is in a period of time, a sampling switch of a corresponding one of the channels is turned on, and the remaining channels of the channels are The sampling switch is cut off. 如申請專利範圍第13項所述之多通道積分器,其中該參考電壓包含一高電壓與一低電壓,而每一個通道的輸入選擇器各自包括: 一第一開關,具有一控制端、一第一端與一第二端,該第一開關的第一端作為該輸入選擇器的共同端,而該第一開關的第二端耦接至該低電壓;一第二開關,具有一控制端、一第一端與一第二端,該第二開關的第一端耦接至該第一開關的第一端,而該第二開關的第二端耦接至該高電壓;一第三開關,具有一控制端、一第一端與一第二端,該第三開關的第一端耦接至該第一開關的第一端,而該第三開關的第二端耦接至該積分器;一第一反閘,其輸入端接收一重置信號,而該第一反閘的輸出端耦接至該第一開關的控制端;一第二反閘,其輸入端接收一控制信號;一第一及閘,其第一輸入端接收該重置信號,該第一及閘的第二輸入端耦接至該第二反閘的輸出端,而該第一及閘的輸出端耦接至該第二開關的控制端;以及一第二及閘,其第一輸入端接收該重置信號,該第二及閘的第二輸入端接收該控制信號,而該第二及閘的輸出端耦接至該第三開關的控制端。 The multi-channel integrator of claim 13, wherein the reference voltage comprises a high voltage and a low voltage, and each of the channel input selectors comprises: a first switch having a control end, a first end and a second end, the first end of the first switch being a common end of the input selector, and the second end of the first switch being coupled to the a second switch having a control end, a first end and a second end, the first end of the second switch being coupled to the first end of the first switch, and the second switch The second end is coupled to the high voltage; the third switch has a control end, a first end and a second end, and the first end of the third switch is coupled to the first end of the first switch, and The second end of the third switch is coupled to the integrator; a first reverse gate, the input end of which receives a reset signal, and the output end of the first reverse gate is coupled to the control end of the first switch; a second reverse gate, the input end receives a control signal; a first AND gate, the first input terminal receives the reset signal, and the second input end of the first AND gate is coupled to the second reverse gate An output end, wherein the output end of the first AND gate is coupled to the control end of the second switch; and a second AND gate, the first input end receives the weight Signal, a second input terminal of the second AND gate receives the control signal, and the output of the second AND gate is coupled to the control terminal of the third switch. 如申請專利範圍第13項所述之多通道積分器,其中該些通道中輸入選擇器的共同端分別耦接至一觸控面板中相對應的感測線。 The multi-channel integrator of claim 13, wherein the common ends of the input selectors of the channels are respectively coupled to corresponding sensing lines in a touch panel.
TW98133829A 2009-10-06 2009-10-06 Multi-channel integrator TWI412229B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW98133829A TWI412229B (en) 2009-10-06 2009-10-06 Multi-channel integrator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW98133829A TWI412229B (en) 2009-10-06 2009-10-06 Multi-channel integrator

Publications (2)

Publication Number Publication Date
TW201114180A TW201114180A (en) 2011-04-16
TWI412229B true TWI412229B (en) 2013-10-11

Family

ID=44909942

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98133829A TWI412229B (en) 2009-10-06 2009-10-06 Multi-channel integrator

Country Status (1)

Country Link
TW (1) TWI412229B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI692716B (en) * 2019-01-04 2020-05-01 瑞鼎科技股份有限公司 Capacitive touch sensing circuit

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200707922A (en) * 2005-04-14 2007-02-16 Micron Technology Inc Multi-point correlated sampling for image sensors
US20070187609A1 (en) * 2003-08-12 2007-08-16 Simon Fraser University Multi-mode digital imaging apparatus and system
US7286180B2 (en) * 2002-02-01 2007-10-23 Micron Technology, Inc. CMOS image sensor with a low-power architecture
TW200913465A (en) * 2007-07-19 2009-03-16 Univ Sussex Sensor system and method
US20090091648A1 (en) * 2007-10-09 2009-04-09 Shengmin Lin Multi-resolution Image Sensor Array with High Image Quality Pixel Readout Circuitry
TW200941932A (en) * 2007-11-16 2009-10-01 Omnivision Tech Inc Switched-capacitor amplifier with improved reset phase

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7286180B2 (en) * 2002-02-01 2007-10-23 Micron Technology, Inc. CMOS image sensor with a low-power architecture
US20070187609A1 (en) * 2003-08-12 2007-08-16 Simon Fraser University Multi-mode digital imaging apparatus and system
TW200707922A (en) * 2005-04-14 2007-02-16 Micron Technology Inc Multi-point correlated sampling for image sensors
TW200913465A (en) * 2007-07-19 2009-03-16 Univ Sussex Sensor system and method
US20090091648A1 (en) * 2007-10-09 2009-04-09 Shengmin Lin Multi-resolution Image Sensor Array with High Image Quality Pixel Readout Circuitry
TW200941932A (en) * 2007-11-16 2009-10-01 Omnivision Tech Inc Switched-capacitor amplifier with improved reset phase

Also Published As

Publication number Publication date
TW201114180A (en) 2011-04-16

Similar Documents

Publication Publication Date Title
US9367184B2 (en) Method of reducing offset in a capacitive touch panel capable of switching between a differential-input sensor circuit and single-ended sensor circuit
US8618818B2 (en) Electrostatic capacity type touch sensor
US10949032B2 (en) Circuit, touch chip, and electronic device for capacitance detection
KR101178731B1 (en) Circuit for processing touch line signal of touch screen
US8575947B1 (en) Receive demodulator for capacitive sensing
US7884662B1 (en) Multi-channel integrator
CN107449810B (en) Capacitance measuring circuit, input device using the same, and electronic apparatus
US8836669B1 (en) High resolution capacitance to code converter
US8274489B2 (en) Readout apparatus and multi-channel readout apparatus for touch panel
JP2010182290A (en) Signal processing device of touch panel
KR101591293B1 (en) Capacitive type touch input device with compensation circuit for stray capacitance
KR102632067B1 (en) Noise detection circuit, self-capacitance detection method, touch chip and electronic devices
CN104571734A (en) Self-mutual capacitance detection circuit and capacitive touch panel
US9904426B2 (en) Capacitive type touch input device with compensation circuit for stray capacitance
US8035439B2 (en) Multi-channel integrator
JP2011113186A (en) Signal processing circuit for electrostatic capacity type touch panel
TWI412229B (en) Multi-channel integrator
KR102248984B1 (en) High sensitivity touch sensor
TWI406032B (en) Readout apparatus and multi-channel readout apparatus for touch panel
WO2021016992A1 (en) Capacitance measurement method
WO2021016991A1 (en) Capacitance detection circuit, touch chip, and electronic device
KR20190039015A (en) Touch circuit
CN102045059B (en) Muti-channel integrator
CN102043504B (en) Reading circuit for touch-control panel
CN102045053A (en) Multi-channel integrator

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees