TWI412220B - Control circuit and method thereof for constant on time converter - Google Patents

Abstract

The present invention provides a control circuit and method thereof for constant on-time converter. The improved constant on time control direct current conversion circuit based on the control method makes system stable without dependence of the equivalent series impedance ESR, and improves dynamic response property of the system.

Description

Control circuit for constant on-time conversion circuit and method thereof

The present invention relates to a DC conversion circuit, and more particularly to a constant on-time DC conversion circuit.

The constant on-time DC conversion circuit has been well applied in the field of power conversion due to its superior load transient response, simple internal structure and smooth working mode switching.
The circuit as shown in Fig. 1 is a conventional constant on-time DC conversion circuit 50. As shown, a constant time of the timer circuit U ₁ receives input V _IN and V _OUT output circuit 50 of the first 50 of FIG. Circuit output V _OUT 50, while the composition through the resistor R ₁ and a resistor R ₂ to obtain a feedback loop feedback signal V _FB, and is conveyed to the inverting input of comparator U _2; noninverting input of the comparator receives the reference U ₂ level V _REF, the output terminal is connected to one input of aND gate U _4; U gate ₄ and an output terminal connected to the RS flip-flop the set terminal S of the U _5; U reset terminal R of RS flip-flop ₅ receives a constant The output signal of the time counter circuit U ₁ ; the output Q of the RS flip-flop U ₅ is supplied on the one hand to the input of the driver U ₆ and on the other hand to the constant time timer U ₁ and the minimum off-time circuit U ₃ ; The turn-off time circuit U ₃ receives the output signal of the RS flip-flop U ₅ and generates a low-level signal of a minimum off time to the other input terminal of the gate U ₄ ; the two output signals of the driver U ₆ are respectively used The drive circuit 50 outputs the switch tube M ₁ and the lower switch tube M ₂ (in the present specification and its drawings, some places are simply described, and the two are simply referred to as the upper tube M ₁ and the lower tube M _{2 , respectively} ). The signal from the output stage is passed through the inductor L and the ideal capacitor Co to obtain the circuit output signal V _OUT . Where ESR is the actual equivalent series impedance of the ideal capacitor Co.
When the circuit is running, when the feedback signal V _{FB of the} circuit 50 output V _OUT is lower than the reference level V _REF , the output of the comparator U ₂ is positive, and if the output of the minimum off-time circuit U ₃ is also positive at this time, then the gate is U ₄ will deliver a high level signal to RS flip flop U ₅ , thereby triggering RS flip flop U ₅ to make its output signal Q positive. This positive signal Q U ₆ through the driver circuit 50 of the switch M ₁ is turned on, the switch M ₂ is turned off, the output V _OUT increases. When the output V _OUT rises such that its feedback signal V _{FB is} higher than the reference level V _REF after passing through the voltage divider, the output of the comparator U ₂ is negative, and thus the set terminal S of the RS flip-flop U ₅ is zero. Its output Q remains in its original state. The positive signal Q simultaneously causes the constant time timer U _{1 to} start timing. When the constant time timer U ₁ reaches the preset value, its output O goes high, and then the RS flip-flop U ₅ is reset, so that the output Q of the RS flip-flop U ₅ goes low; this low signal Q passes through the driver. U ₆ turns off the upper switch M _{1 of the} circuit 50 and the lower switch M ₂ turns on, causing the output V _{OUT to} decrease. It should be noted that when the upper switching transistor M _{1 is} turned off and the lower switching transistor M ₂ is turned on, the inductor current linearly drops under the action of the output voltage. When the load current is small, the inductor current may drop to zero and flow in the opposite direction. To prevent reverse flow of the inductor current, it is common practice to turn off the lower switch M ₂ or operate it as an equivalent microcurrent source when the inductor current drops to zero. It is not specifically shown here. At the same time, the low signal Q is sent to the minimum off time circuit U ₃ , so that U ₃ outputs a low level signal with a minimum off time to the gate U ₄ , thereby invalidating and gate U during the minimum off time. The other input of ₄ , that is, regardless of whether the output of comparator U ₂ is positive or negative at this time, and the output of gate U ₄ is negative. When the feedback signal V _{FB of the} output V _OUT drops below V _REF , the output of the comparator U ₂ is positive and the minimum off time has elapsed, so the output of the gate U ₄ is positive, thereby setting the RS flip-flop U ₅ The circuit work begins a new cycle.
Those skilled in the art can appreciate that the function of the minimum off-time circuit U ₃ here is that when the circuit is in normal operation, after the constant on-time expires, the output Q of the RS flip-flop U ₅ is low, and the upper switch M of the circuit 50 ₁ is turned off, the lower switch M ₂ is turned on, and the output V _OUT starts to fall. In order to avoid other reasons such as noise interference, the comparator U ₂ immediately enters the next cycle after a constant on-time, and outputs a high-level signal, thereby setting the meta-RS flip-flop, the minimum off-time circuit U. _{3 At} this moment, a low-level signal Q is detected, and a low-level signal with a minimum off-time is output to the gate U ₄ to disable the high-level signal output by the comparator U ₂ at this time to ensure that the circuit operates normally. So that the gate drive signal of the upper switch M ₁ has a low state of minimum off time.
2(a) and 2(b) are the gate drive signal of the switch M1 on the circuit 50 shown in Fig. ₁ , the voltage ripple across the impedance ESR, the voltage ripple across the ideal capacitor Co, and the circuit 50. The waveform of the output voltage ripple. As shown in the figure, when the circuit is in steady state operation, since the impedance value of the ESR is very small compared with the load, it can be considered that the ripple portion of the inductor current flows through the equivalent series impedance ESR and the ideal capacitance Co, thus ESR A ripple voltage is generated in the same phase as the inductor current ripple portion and the amplitude is proportional thereto; at the same time, the ideal capacitor Co integrates the ripple current to generate a capacitor ripple voltage. It should be noted that due to the integral action of the capacitance, there is a 90 degree delay between the resulting capacitor ripple voltage and the inductor ripple current. When the impedance value of the ESR is relatively large, the voltage ripple across the ESR is dominant compared to the voltage ripple across the ideal capacitor Co. The ripple of the output V _OUT of the circuit 50 is mainly determined by the voltage ripple of the ESR at both ends. As shown in Figure 2(a), the output voltage is relatively stable at this time; and when the impedance value of the ESR is relatively small, the voltage ripple across the ideal capacitor Co is dominant compared to the voltage ripple across the ideal capacitor Co. The ripple of the output voltage V _OUT of the circuit 50 is mainly determined by the voltage ripple of the ideal capacitor Co. At this time, the system is likely to generate subharmonic oscillation, and the system loses stability, as shown in Fig. 2(b).
In summary, the conventional constant on-time DC conversion circuit 50 shown in FIG. 1 requires an equivalent series impedance ESR having a large impedance value to stabilize the system. Therefore, in a special application such as a notebook computer, the conventional constant on-time DC conversion circuit cannot use a small-capacity and low-cost ceramic capacitor as an output capacitor, and a relatively expensive polymer organic semiconductor solid capacitor (sp-cap) is required. ).
Therefore, there is a need to provide a constant on-time DC conversion circuit that can stabilize the system even in the case of low equivalent series impedance (ie, when a low-cost ceramic capacitor is selected).

It is therefore an object of the present invention to provide an improved constant on-time control method and circuit. The improved constant on-time controlled DC conversion circuit based on this method does not rely on the equivalent series impedance ESR of the output capacitor to stabilize the system. Even with zero-ESR output capacitance, the improved converter circuit can achieve stable operation of the system during steady-state operation and load current jump, and further improve the dynamic response performance of the system.
To achieve the above object, the present invention discloses a control circuit for a constant on-time conversion circuit including a constant time timer for providing a constant time timing signal and a minimum off time circuit for providing a minimum off time. a time-breaking signal; a feedback loop for feeding back the output signal of the conversion circuit and providing a feedback signal; a comparator for comparing the feedback signal with a reference signal and providing a comparison signal; a logic circuit Receiving the constant time timing signal, the minimum off time signal, the comparison signal, and providing a logic output signal; a driver for receiving the logic output signal and providing a driving signal to the a conversion circuit output stage; and a compensation circuit for providing a compensation signal to the comparator.
The invention also discloses a control method for a constant on-time conversion circuit, comprising receiving an input signal of the conversion circuit, an output signal of the conversion circuit, and a logic output signal of a logic circuit by using a constant time timer, And outputting a constant time timing signal to the third input of the logic circuit; receiving a logic output signal of the logic circuit with a minimum off time circuit, and outputting a minimum off time signal to the logic circuit a second input terminal; receiving, by a feedback loop, an output signal of the conversion circuit, and outputting a feedback signal to one end of a comparator; the terminal of the comparator simultaneously receiving a compensation signal; Comparing the feedback signal and the compensation signal with a reference signal, and outputting a comparison signal to the first input of the logic circuit; receiving, by the logic circuit, the constant time timing signal, the minimum turn-off a time signal, and the comparison signal, and outputting the logic output signal to the constant time timer, and the most Turning off the time circuit, a driver and a compensation circuit; receiving the logic output signal by the driver, and outputting two driving signals for controlling the opening and closing of the switching tube and the lower switching tube on the output stage of the conversion circuit An off state; receiving, by the compensation circuit, the logic output signal, and outputting the compensation signal to the comparator.
The invention further discloses a control method for a constant on-time conversion circuit, comprising comparing a feedback signal, an algebra of a compensation signal and a size of a reference signal; and controlling a switching tube of the output stage of the conversion circuit based on the comparison result a state; wherein when the feedback signal, the algebraic sum of the compensation signal is greater than the reference signal, maintaining the state of the output stage switch tube; when the feedback signal, the algebraic sum of the compensation signal is smaller than the reference signal When the switch is turned on and the lower switch is turned off at the output stage, and the compensation signal is cleared to zero, the increase is started until the constant on time arrives; the feedback signal and the algebra of the compensation signal are compared again. And a size of the reference signal; when the feedback signal, the algebraic sum of the compensation signal is smaller than the reference signal, keeping the switch on the output stage open, the compensation signal continues to increase; When the feedback signal, the algebraic sum of the compensation signal is greater than the reference level, the switching tube on the output stage is turned off, and the lower switching tube is turned on While the compensation signal is reduced, and detects the inductor current conversion circuit, until the minimum off time is reached.
The invention also discloses a control method for a constant on-time conversion circuit, which comprises comparing a reference signal, an algebraic difference of a compensation signal and a magnitude of a feedback signal; and controlling a state of the switching tube of the output stage of the conversion circuit based on the comparison result Wherein when the algebraic difference of the reference signal and the compensation signal is less than the feedback signal, maintaining the state of the output stage switch tube unchanged; when the reference signal and the compensation signal have an algebraic difference greater than the feedback When the signal is turned on, the switch tube is turned on and the lower switch tube is turned off, and the compensation signal is started to be increased after the compensation signal is cleared, until the constant conduction time arrives; the reference signal and the compensation are compared again. An algebraic difference of the signal and the feedback signal size; when the algebraic difference of the reference signal and the compensation signal is greater than the feedback signal, maintaining the switch on the output stage is turned on, and the compensation signal continues to increase; When the algebraic difference between the reference signal and the compensation signal is smaller than the feedback signal, the switch tube on the output stage is turned off, and the lower switch tube is turned on. While the compensation signal is reduced, and detects the inductor current conversion circuit, until the minimum off time is reached.
The invention adopts the circuit and the control method of the above structure, and the compensation circuit provided by the compensation circuit with the constant change of the input signal and the output signal of the constant on-time conversion circuit follows the change of the inductor current, which is equivalent to the prior art (eg Figure 1) The output capacitor equivalent series impedance ESR, and through the design of the compensation circuit, the conversion circuit overcomes the shortcomings of system output instability under zero ESR; and, through the introduction of the compensation circuit design, When the load current is changing, it provides a good load response to the load, which solves the shortcomings in the prior art. Thus, the present invention is applicable to a constant on-time DC conversion circuit to improve its performance.

As shown in Fig. 3, there is shown a flow chart of an improved constant on-time DC conversion method in accordance with the present invention. When the circuit starts operating, the algebraic sum of a feedback signal V _FB and a compensation signal V _slope is compared with a reference signal V _R . When the algebraic sum of the feedback signal V _FB and the compensation signal V _slope is greater than the reference signal V _R , that is, V _FB +V _slope >V _R , the current switching state of the output stage of the circuit is maintained; when the feedback signal V _FB and the compensation signal V _slope When the algebraic sum is less than the reference signal V _REF , that is, V _FB +V _slope <V _R , the upper switch M _{1 of the} circuit output stage is turned on, the lower switch tube M _{2 is} turned off, and the compensation signal V _{slope is} cleared. To increase it, the upper switching transistor M ₁ is maintained in a conducting state for a constant _ON time period T _ON . When T _ON ends, if V _FB +V _slope <V _R , the upper switch M ₁ is continuously turned on, and the compensation signal V _slope continues to increase. Then the output V _OUT continues to increase, ie the feedback signal V _FB continues to increase. When the feedback signal V _FB and the compensation signal V _slope increase to V _FB +V _slope >V _R , the upper switch M ₁ is turned off and the lower switch M ₂ is turned on, and the inductor current I _L starts to decrease. At the same time, the compensation signal V _slope also begins to decrease. If the inductor current I _{L is} reduced to zero, the circuit turns off the lower switch M ₂ or controls the lower switch M ₂ to operate in the equivalent micro current source mode; if the inductor current I _L does not decrease to zero, maintain The lower switch M _{2 is} turned on until the minimum off time T _OFF ends. After the end of T _OFF , return to the state when the circuit starts running, and judge the magnitude of V _FB +V _slope and V _R . If V _FB +V _slope >V _R , keep the current switching state, that is, the upper switching tube M ₁ is turned off, and the lower switching tube M ₂ is turned on; if V _FB +V _slope <V _R , the upper switching tube M ₁ The open and lower switch M _{2 are} turned off, and the circuit operation starts a new cycle. Those skilled in the art will recognize that the algebraic difference between the reference signal V _R and the compensation signal V _slope can also be compared to the feedback signal V _FB , i.e., the magnitude of V _FB and (V _R -V _slope ). If V _FB >(V _R -V _slope ), keep the current switching state of the output stage of the circuit; when V _FB <V _R -V _slope , turn on the upper switch M _{1 of the} circuit output stage, and turn off the lower switch M ₂ Break and increase the compensation signal V _slope after zeroing.
It can be seen that the compensation signal V _slope is such a signal that when the upper switching tube M ₁ is turned on and the lower switching tube M ₂ is turned off, the compensation signal V _slope is cleared, and then starts to increase; when the upper switching tube When M ₁ is turned off and the lower switch M ₂ is turned on, the compensation signal V _{slope is} decreased. That is, the compensation signal acts as an equivalent series impedance ESR with a large impedance value of the output capacitor in the prior art, and is a ripple voltage which is in phase with the inductor current ripple portion and whose amplitude is proportional thereto. Therefore, when the compensation signal V _{slope is} increased, the slope is proportional to (V _IN - V _O ); and when the compensation signal V _{slope is} decreased, the slope is proportional to

V _O , where V _IN is the input signal of the constant on-time conversion circuit, and V _{O is} its output signal.

Figure 4 shows the compensation circuit that produces the compensation signal V _slope . As shown in FIG. 4, the compensation circuit includes a first current source U ₁₁ , a second current source U ₁₂ , a first switch S ₁ , a second switch S ₂ , a capacitor C _slope , and a pulse generator . The output current I _{1 of the} first current source U ₁₁ is proportional to the input V _IN , and the output current I _{2 of the} second current source U ₁₂ is proportional to the output V _O . A first current flowing terminal of the current source U ₁₁ is connected to an end of the first switch S _1, the first switch S ₁ and the other end connected to one end of the capacitor C _slope. The end point of the capacitor C _{slope is} used as the output end of the compensation circuit. The signal of the end point is used as the output signal of the compensation circuit, that is, the compensation signal V _slope is added to the feedback signal V _{FB of the} conversion circuit; and the end of the capacitor C _slope is connected. a current flowing to the second current source U ₁₂ to discharge the capacitor C _slope when the second switch S ₂ is turned off; connected to the second switch S ₂ , so that the voltage across the capacitor C _slope is turned on when S ₂ is turned on V _slope is reset. The other end of the capacitor C _slope , the current outflow terminal of the second current source U ₁₂ , and the other end of the second switch S ₂ are grounded. The control end of the first switch S ₁ serves as an input end of the compensation circuit, and receives a logic output signal Q of the conversion circuit, which is synchronized with the control signal of the switch M ₁ on the output stage of the DC conversion circuit; the pulse generator also receives the signal. and generating a short pulse high-level signal at the rising of this signal, controls the opening of the second switch S ₂ and the off-state.
When the signal Q is high, the pulse generator outputs a short pulse high level signal. Then, the first switch S ₁ and the second switch S ₂ are both turned on, and the second switch S ₂ resets the voltage across the capacitor C _slope , that is, the compensation signal V _slope is reset to zero at this time. After the short pulse, the second switch S ₂ is turned off, the first current source U ₁₁ and the second current source U _{12 work} together to start charging the capacitor C _slope , and the charging slope is . When the signal Q goes low, the first switch S ₁ is turned off, and the second current source U ₁₂ starts to discharge the capacitor C _slope , and the discharge slope is . A first control terminal of the switching signal S _1, the voltage across the capacitor and charge and discharge current C _slope control terminal of the second switching signal S, the capacitance C _{slope 2} as shown in FIG. 5. As can be seen from Figure 5, the voltage across the capacitor C _slope is the desired compensation signal. Since the capacitor C and the _slope before the beginning of the first charging current source U _11, the second switch S _{2 slope} voltage across capacitor C is reset, it will not introduce additional errors, without introducing a bias voltage output. While the current I _{1 is} proportional to the input V _IN and the current I _{2 is} proportional to the output V _O , the charging slope of the capacitor C _slope is proportional to V _IN -V _O , and the discharge slope of the capacitor C _slope is proportional to V _O . That is, the increasing slope of the compensation signal V _slope is proportional to V _IN -V _O , and the decreasing slope is proportional to V _O . The effect of the compensation signal V _slope is the equivalent series impedance ESR of the prior art ideal capacitor impedance value. The role of the wave voltage. Therefore, the control method provided by the present invention overcomes the disadvantage that the system output is unstable in the case of zero ESR.
Briefly stated, the present invention provides a control method for a constant on-time conversion circuit, the method comprising: comparing an algebraic sum of a feedback signal V _FB with a compensation signal V _slope and a magnitude of a reference signal V _R ; The state of the switch tube of the output stage of the constant on-time conversion circuit: when the algebraic sum of the feedback signal V _FB and the compensation signal V _slope is greater than the reference signal V _R , that is, V _FB +V _slope >V _R , maintaining the state of the output stage switch tube When the algebraic sum of the feedback signal V _FB and the compensation signal V _slope is smaller than the reference signal V _R , that is, V _FB +V _slope <V _R , the switching transistor M _{1 is} turned on and the lower switching transistor M _{2 is} turned off at the output stage. At the same time, the compensation signal V _{slope is} cleared and then started to increase. The slope of the increase is proportional to the difference between the input V _IN and the output V _O until the constant on-time T _ON arrives. At this time, the algebra sum of the feedback signal V _FB and the compensation signal V _slope and the magnitude of the reference signal V _R are compared again: when the algebraic sum of the feedback signal V _FB and the compensation signal V _slope is smaller than the reference signal V _R , that is, V _FB +V _slope <V _R , keeping the switch M ₁ turned on at the output stage, the compensation signal V _slope continues to increase proportional to V _IN −V _O ; when the algebraic sum of the feedback signal V _FB and the compensation signal V _slope is greater than the reference signal V _R That is, V _FB +V _slope >V _R , the switching tube M _{1 is} turned off at the output stage, and the lower switching tube M _{2 is} turned on, the compensation signal V _{slope is} reduced, and the decreasing slope is proportional to the output V _O ; Transforming the inductor current I _L until the minimum off time T _OFF arrives; if the detected inductor current is reduced to zero before the minimum off time arrives, the lower switch M _{2 is} turned off, or its operation is controlled, etc. Effective micro current source mode.
Or comparing the algebraic difference between the reference signal V _R and the compensation signal V _slope and the magnitude of the feedback signal V _FB , and controlling the state of the switching transistor of the output stage of the constant on-time conversion circuit based on the comparison result: when the reference signal V _R and the compensation signal V _slope When the algebraic difference is smaller than the feedback signal V _FB , that is, V _R -V _slope <V _FB , the state of the output stage switching tube is kept unchanged; when the algebraic difference between the reference signal V _R and the compensation signal V _slope is greater than the feedback signal V _FB , V _R -V _slope > V _FB , the switch M _{1 is} turned on and the lower switch M _{2 is} turned off at the output stage, and the compensation signal V _{slope is} cleared and then increased, and the slope of the increase is proportional to Enter the difference between V _IN and output V _O until the constant on-time T _ON arrives. At this time, the algebraic difference between the reference signal V _R and the compensation signal V _slope and the magnitude of the feedback signal V _FB are compared again: when the algebraic difference between the reference signal V _R and the compensation signal V _slope is greater than the feedback signal V _FB , that is, V _R -V _slope >V _FB , keep the switch M ₁ open on the output stage, the compensation signal V _slope continues to increase proportional to the slope of V _IN -V _O ; when the difference between the reference signal V _REF and the compensation signal V _slope is smaller than the feedback signal V _FB When V _R -V _slope > V _FB , the switch M _{1 is} turned off and the lower switch M _{2 is} turned on at the output stage, and the compensation signal V _{slope is} decreased, and the decreasing slope is proportional to the output V _O ; Detecting the inductor current I _L until the minimum off time T _OFF arrives; if the detected inductor current is reduced to zero before the minimum off time arrives, the lower switch M _{2 is} turned off, or the control is operated at the equivalent micro Current source mode.
Figure 6 shows an improved constant on-time DC conversion circuit 100 in accordance with one embodiment of the present invention. As shown in Fig. 6, the circuit 100 employs the compensation circuit 10 shown in Fig. 4, and the logic circuit 20 is modified to improve the stability performance during load jump. In this embodiment, the circuit 100 includes a constant time timer U ₁ for providing a constant time timing signal, a minimum off time circuit U ₃ for providing a minimum off time signal, and a resistor R ₁ and A feedback loop composed of a resistor R _{2 is} used to feed back the output signal of the circuit 100 and provide a feedback signal. A comparator U _{2 is} used to compare the feedback with a reference signal and provide a comparison signal. The circuit 100 further includes a logic circuit 20 for receiving a constant time timing signal, a minimum off time signal and a comparison signal, and providing a logic output signal; a driver U ₇ for receiving the logic output signal and providing the driving signal to the circuit output stage 100; and a compensation circuit 10, for providing a compensation signal to the comparator V _slope U _2; and an output stage of the switch circuit M ₁ and M ₂ the switch 100 is composed of, from the inductor L and capacitor A filter composed of C _O. The compensation circuit 10, the logic circuit 20, the feedback loop, the constant time timer U ₁ , the comparator U ₂ , the minimum off time circuit U _{3 ,} and the driver U ₇ constitute a control circuit of the circuit 100.
After the output voltage V _{O of} the circuit 100 is divided, the obtained feedback signal V _{FB is} added to the compensation signal V _slope outputted by the compensation circuit 10, and the result of the addition is sent to the inverting input terminal of the comparator U ₂ . The non-inverting input of comparator U ₂ receives a reference signal V _R . In this embodiment, the reference signal is a reference level V _REF . An input end of the first AND gate U ₄ serves as a first input end of the logic circuit 20, and receives an output signal of the comparator U ₂ ; a second input end of the first AND gate U ₄ serves as a second input end of the logic circuit 20, receives the minimum off time off circuit output signal U _3; an output terminal of the first aND _{gate. 4} U U RS flip-flop is connected to the set terminal S of the inverter ₇ and the input terminal of the _{U. 5;} the output of the _{inverter. 5} U terminal is connected to a second input of aND gate U _6, and the other input of the second aND gate U ₆ as a third input of the logic circuit 20 receives a constant timer output signal U _1; a second aND gate The output of U ₆ is connected to RS flip-flop U ₇ reset terminal R, the output of RS flip-flop U ₇ is connected to the input of driver U ₈ , the input of minimum off-time circuit U ₃ and the constant time timer U ₁ a third input terminal; a first input terminal of a constant time before the timer U ₁ through a feedback resistor R _feedforward circuit receives input V _iN 100, the second input terminal receives the output V _O circuit 100. The two output signals of the driver U ₈ are respectively used to drive the switch M ₁ and the lower switch M ₂ on the output stage of the circuit 100 to obtain a square wave signal at the node SW. This square wave signal passes through the inductor L and the output capacitor C to obtain the desired output voltage V _O .
When the circuit is in operation, the input V _{IN of the} circuit 100 is supplied on the one hand to the output stage via the upper switching tube M ₁ connected thereto and on the other hand to the constant time timer U ₁ . The second input of the constant time timer U ₁ receives the output V _{O of the} circuit 100 and the third input receives the output signal Q of the RS flip-flop U ₇ . When the signal Q is high, the constant time timer U ₁ starts counting. When the timing T _ON = n × V _O / V _IN , the constant time timer U ₁ outputs a high level signal to the second AND gate U ₆ Where n is a set constant.
In addition, the circuit output V _O is supplied on the one hand to the second input of the constant time timer U ₁ and on the other hand to a feedback signal V _FB via a voltage divider consisting of resistors R ₁ and R ₂ . The feedback signal V _{FB is added} to the compensation signal V _slope and its algebraic sum is supplied to the inverting input of the comparator U ₂ . When V _FB +V _slope <V _R , the comparator U ₂ outputs a high level signal. At this time, the output Q of the RS flip-flop U ₇ is still at a high level, so the output of the minimum off-time circuit U ₃ is still high, so that the output of the first and gate U ₄ is high. The high level signal output by the first gate U ₄ goes low after passing through the inverter U ₅ , thereby invalidating the high level signal of the other input terminal of the second gate U ₆ at this time (from the constant on time circuit U ₁ The output of O). Therefore, the output Q of the RS flip-flop U ₇ remains unchanged, the upper switch M _{1 of the} output stage of the circuit 100 continues to be turned on, and the lower switch M ₂ continues to be turned off, and the compensation signal V _slope continues to increase. The upper switch M ₁ maintains a long pass, which provides a good load response to the load when the load current is changing.
When the load current has a positive transition (the load current increases rapidly), the output voltage decreases rapidly, so that the feedback signal V _{FB of the} output V _O decreases rapidly. After the constant on-time T _ON , the feedback signal V _FB and the compensation The algebraic sum of the signal V _slope is still smaller than the reference signal V _R , that is, V _FB +V _slope <V _R , then the upper switch M ₁ remains long-passed and the lower switch M ₂ continues to be turned off. Until the output V _O and the compensation signal V _slope increase such that V _FB +V _slope >V _R , the comparator U ₂ outputs a low level, and the inverter U ₅ outputs a high level, thereby resetting the RS flip-flop U ₇ , so that the output signal Q goes low. The minimum off time circuit U ₃ detects the signal Q of the low level, and outputs a low level signal to the first gate U ₄ , so that the first gate and the gate U ₄ are invalid during the next minimum off time. the other input, the output stage circuit 100 so that there is at least a minimum off time of the switch M ₁ is turned off, the switch M ₂ is turned state. Circuit 100 then proceeds to the next cycle until the load jump ends and enters the normal operating mode. It can be seen that the load current of the circuit 100 is very stable. When the load current exhibits a negative transition, the conventional constant on-time DC conversion circuit and the inventive circuit 100 have very good load response.
As described above, in the circuit 100, the compensation signal V _slope is such a signal that when the upper switching transistor M ₁ is turned on, the compensation signal V _slope is reset to zero, and then starts to be proportional to V _IN -V _O . the slope is increased; when the upper switch M ₁ is turned off, V _slope compensation signal proportional to the slope of the V _O decreases. That is, the compensation signal _Vslope follows the change of the inductor current I _L , which is equivalent to the equivalent series impedance ESR of the output capacitor in FIG. 1 . Therefore, after the compensation circuit 10 is added, the circuit 100 overcomes the disadvantage that the system output is unstable in the case of zero ESR.
Figure 7 shows an improved constant on-time DC conversion circuit 200 in accordance with another embodiment of the present invention. The circuit 200 differs from the circuit 100 shown in FIG. 6 in that the reference level V _{REF of the non-} inverting input of the comparator U ₂ is replaced with a reference level V _REF and an operational amplifier U ₉ . The non-inverting input terminal of the operational amplifier U ₉ receives the reference level V _REF , the inverting input terminal receives the feedback signal V _FB , and the output thereof is added to the reference level V _{REF and} then sent to the non-inverting input terminal of the comparator U ₂ . That is, in the present embodiment, the reference signal V _R received by the non-inverting input of the comparator U ₂ is the algebraic sum of the output of the operational amplifier U ₉ and the reference level V _REF . This is because in some applications, the equivalent series impedance ESR of the output capacitor and the compensation signal may introduce a certain DC error, which results in a certain DC error between V _O and the set value. In order to solve this problem, the circuit 200 shown in Fig. 7 adds an error compensation link to eliminate a certain DC error between V _O and the set value. For example, assuming that the output voltage V _O ratio is set slightly higher, then the operational amplifier U output ₉ is negative, so that the operational amplifier U ₉ is less than the reference level V _REF with the voltage input terminal, thereby adjusting the output V _O, output V _O becomes Low, closer to the set value of the output voltage. In summary, the added compensation link in the circuit 200 shown in FIG. 7 is to suppress the DC error of the output voltage by adjusting the non-inverting input terminal voltage V _{R of the} comparator U ₂ ; those skilled in the art will appreciate that by adjusting the comparator U The inverting input voltage of ₂ can also achieve the same error suppression effect, which will not be elaborated here.
The other parts of the circuit 200 are the same as the circuit 100 shown in Fig. 6, and the same parts are given the same reference numerals. At the same time the same principle of the other parts of the circuit 200 and circuit 100, circuit 200 and the output V _O in addition to more precise, the smaller the ripple, the circuit 100 circuit 200 to achieve the technical effect can be achieved, not specifically set forth herein.
It is to be understood that the above summary of the invention and the specific embodiments thereof are intended to illustrate the practical application of the technical solutions provided by the present invention and should not be construed as limiting the scope of the invention. Those skilled in the art can make various modifications, equivalent substitutions, or improvements within the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

V _FB ‧‧‧ feedback signal

V _slope ‧‧‧compensation signal

V _R ‧‧‧ reference signal

M ₁ ‧‧‧Upper switch

M ₂ ‧‧‧ lower switch

T _ON ‧‧‧maintain constant on time

T _OFF ‧‧‧Minimum turn-off time

R _feedforward ‧‧‧ feedforward resistor

ESR‧‧‧ equivalent series impedance

V _OUT ‧‧‧ circuit output signal

SW‧‧‧ node

U ₁ ‧‧‧ Constant time timer

U ₂ ‧‧‧ comparator

U ₃ ‧‧‧Minute off time circuit

U ₄ ‧‧‧First Gate

U ₅ ‧‧‧RS trigger

U ₆ ‧‧‧Second Gate

U ₇ /U ₈ ‧‧‧ drive

U ₉ ‧‧‧Operational Amplifier

U ₁₁ ‧‧‧First current source

U ₁₂ ‧‧‧second current source

I _L ‧‧‧Inductor current

V _IN ‧‧‧ input signal

V ₀ ‧‧‧Output signal

S ₁ ‧‧‧first switch

S ₂ ‧‧‧second switch

C _slope /C ₀ ‧‧‧ capacitor

Q‧‧‧ logic output signal

I ₁ /I ₂ ‧‧‧ Current

10‧‧‧Compensation circuit

20‧‧‧Logical circuits

50/200‧‧‧DC conversion circuit

100‧‧‧ circuits

R ₁ /R ₂ ‧‧‧resistance

L‧‧‧Inductance

V _REF ‧‧‧ reference level

S‧‧‧Setting end

R‧‧‧Reset end

Figure 1 is a conventional constant on-time DC conversion circuit.
Fig. 2(a) is a waveform diagram of each signal when the ESR impedance value of the capacitor equivalent series impedance is large in the circuit shown in Fig. 1.
Figure 2(b) is a waveform diagram of each signal when the ESR impedance value of the capacitor equivalent series impedance is small in the circuit shown in Figure 1.
Figure 3 is a diagram of an improved constant on-time DC conversion circuit in accordance with the present invention.
Fig. 4 is a detailed circuit configuration diagram of the compensation circuit of the circuit shown in Fig. 3.
Figure 5 is a diagram showing the control signals of the two switches of the circuit shown in Figure 4, the charge and discharge current of the capacitor, and the voltage waveforms across the capacitor.
Figure 6 is a diagram of an improved constant on-time DC conversion circuit in accordance with one embodiment of the present invention.
Figure 7 is a diagram showing an improved constant on-time DC conversion circuit in accordance with another embodiment of the present invention.

V _FB ‧‧‧ feedback signal

V _slope ‧‧‧compensation signal

V _R ‧‧‧ reference signal

M ₁ ‧‧‧Upper switch

M ₂ ‧‧‧ lower switch

T _ON ‧‧‧maintain constant on time

T _OFF ‧‧‧Minimum turn-off time

Claims (19)

A control circuit for a constant on-time conversion circuit includes a constant time timer for providing a constant time timing signal;
a minimum off time circuit for providing a minimum off time signal;
a feedback loop for feeding back the output signal of the conversion circuit and providing a feedback signal;
a comparator for comparing the feedback signal with a reference signal and providing a comparison signal;
a logic circuit for receiving the constant time timing signal, the minimum off time signal, the comparison signal, and providing a logic output signal;
a driver for receiving the logic output signal and providing a driving signal to the conversion circuit output stage;
The conversion circuit further includes a compensation circuit for providing a compensation signal to the comparator. The control circuit of claim 1, wherein the constant time timer comprises at least three inputs, a first input thereof receiving an input signal of the conversion circuit; and a second input receiving the transformation An output signal of the circuit; the third input thereof receives the logic output signal;
The minimum off time circuit receives the logic output signal;
An input of the comparator receives the feedback signal and a compensation signal output by the compensation circuit; another input of the comparator receives the reference signal;
The logic circuit includes at least three inputs, a first input thereof receiving the comparison signal, a second input receiving the minimum off time signal, and a third input receiving the constant time timing signal;
The driver receives the logic output signal;
The two output signals of the driver are respectively used to drive the upper switch tube and the lower switch tube of the output stage of the conversion circuit;
The compensation circuit receives the logic output signal and outputs the compensation signal to the comparator. The control circuit of claim 2, wherein the reference signal is a reference level. The control circuit of claim 2, wherein the control circuit further comprises an operational amplifier; wherein an input of the operational amplifier receives the feedback signal and the other input receives a reference Level
The reference signal is an algebraic sum of the operational amplifier output signal and the reference level. The control circuit of claim 2, wherein the logic circuit comprises a first gate, a second gate, an inverter, and an RS flip-flop; wherein the first gate and the gate Inputs as the first and second inputs of the logic circuit, respectively receiving the comparison signal and the minimum off time signal;
An input end of the second AND gate receives an output signal of the inverter, and another input end thereof serves as a third input end of the logic circuit, and receives the constant time timing signal;
An input end of the inverter receives an output signal of the first AND gate;
a set terminal of the RS flip-flop receives an output signal of the first AND gate; a reset terminal thereof receives an output signal of a second AND gate; an output signal thereof is sent to the constant time timer as the logic output signal a third input, an input of the minimum off time circuit, and an input of the driver. The control circuit of claim 2, wherein the compensation circuit comprises a first current source, a second current source, a first switch, a second switch, a capacitor, and a pulse generator, wherein One end of the first switch is connected to an outflow end of the first current source; the other end of the first switch is connected to one end of the capacitor and one end of the second switch, and the second current source Inflow end, the common connection end of the four is used as an output end of the compensation circuit, and is connected to one end of the comparator;
The other end of the capacitor, the outflow end of the second current source, and the other ground of the second switch;
The control terminal of the first switch receives the logic output signal; the pulse generator receives the logic output signal to generate a control signal for controlling the second switch. The control circuit of claim 6, wherein an output current of the first current source is proportional to an input voltage of the conversion circuit;
The output current of the second current source is proportional to the output voltage of the conversion circuit. A control method for a constant on-time conversion circuit includes receiving, by a constant time timer, an input signal of the conversion circuit, an output signal of the conversion circuit, and a logic output signal of a logic circuit, and outputting a constant time a timing signal to a third input of the logic circuit;
Receiving a logic output signal of the logic circuit with a minimum off time circuit, and outputting a minimum off time signal to a second input end of the logic circuit;
Receiving, by a feedback loop, an output signal of the conversion circuit, and outputting a feedback signal to one end of a comparator; the terminal of the comparator simultaneously receiving a compensation signal;
Comparing the sum of the feedback signal and the compensation signal with a reference signal by the comparator, and outputting a comparison signal to the first input end of the logic circuit;
Receiving, by the logic circuit, the constant time timing signal, the minimum off time signal, and the comparison signal, and outputting the logic output signal to the constant time timer, and the minimum off time circuit a driver, and a compensation circuit;
Receiving, by the driver, the logic output signal, and outputting two driving signals for controlling an on and off state of the switch tube and the lower switch tube on the output stage of the conversion circuit;
The logic output signal is received by the compensation circuit and the compensation signal is output to the comparator. The control method of claim 8, wherein the reference signal is a reference level. The control method of claim 8, wherein one input terminal of an operational amplifier receives a reference level, and the other input terminal receives the feedback signal,
The reference signal is an algebraic sum of an output signal of the operational amplifier and the reference level. The control method of claim 8, wherein the logic circuit comprises a first gate, a second gate, an inverter, and an RS flip-flop, wherein the first gate And outputting, as the first and second input ends of the logic circuit, respectively receiving the comparison signal and the minimum off time signal;
An input end of the second AND gate receives an output signal of the inverter, and another input end thereof serves as a third input end of the logic circuit, and receives the constant time timing signal;
An input end of the inverter receives an output signal of the first AND gate;
a set terminal of the RS flip-flop receives an output signal of the first AND gate; a reset terminal thereof receives an output signal of a second AND gate; an output signal thereof is sent to the constant time timer as the logic output signal a third input, an input of the minimum off time circuit, and an input of the driver. The control method of claim 8, wherein the compensation circuit comprises a first current source, a second current source, a first switch, a second switch, a capacitor, and a pulse generator, wherein One end of the first switch is connected to an outflow end of the first current source; the other end of the first switch is connected to one end of the capacitor, and one end of the second switch, and the second current The inflow end of the source, the common connection end of the four is used as an output end of the slope compensation circuit, and is connected to one end of the comparator;
The other end of the capacitor, the outflow end of the second current source, and the other ground of the second switch;
The control end of the first switch receives the logic output signal as an input end of the compensation circuit; the pulse generator receives the logic output signal to generate a control signal for controlling the second switch. The control method of claim 12, wherein an output current of the first current source is proportional to an input voltage of the conversion circuit;
The output current of the second current source is proportional to the output voltage of the conversion circuit. A control method for a constant on-time conversion circuit includes comparing a feedback signal, an algebra of a compensation signal, and a size of a reference signal;
Controlling, according to the comparison result, a state of the switch tube of the output stage of the conversion circuit; wherein when the algebraic sum of the feedback signal and the compensation signal is greater than the reference signal, maintaining the state of the output stage switch tube is unchanged;
When the algebraic sum of the feedback signal and the compensation signal is smaller than the reference signal, the switch tube is turned on and the lower switch tube is turned off at the output stage, and the compensation signal is cleared and then increased, until the compensation signal is turned on. Constant on-time arrival;
Comparing the feedback signal, the algebra of the compensation signal, and the size of the reference signal again;
When the algebraic sum of the feedback signal and the compensation signal is smaller than the reference signal, keeping the switch tube on the output stage turned on, the compensation signal continues to increase;
When the algebraic sum of the feedback signal and the compensation signal is greater than the reference level, turn off the switch tube on the output stage, turn on the lower switch tube, reduce the compensation signal, and detect the change The inductor current of the circuit reaches until the minimum off time. The control method of claim 14, wherein before the minimum off time is reached, if the inductor current is reduced to zero, the lower switch is turned off or controlled to operate at an equivalent Micro current source mode. The control method of claim 14, wherein the slope of the increase of the compensation signal is proportional to a difference between an input voltage and an output voltage of the conversion circuit;
The slope of the compensation signal reduction is proportional to the output voltage of the conversion circuit. A control method for a constant on-time conversion circuit includes comparing a reference signal, an algebraic difference of a compensation signal, and a magnitude of a feedback signal;
Controlling, according to the comparison result, a state of the switch tube of the output stage of the conversion circuit; wherein when the algebraic difference of the reference signal and the compensation signal is less than the feedback signal, maintaining the state of the output stage switch tube is unchanged;
When the algebraic difference between the reference signal and the compensation signal is greater than the feedback signal, turn on the switch tube on the output stage, turn off the lower switch tube, and start to increase the compensation signal after clearing the compensation signal. Until the constant conduction time arrives;
Comparing the reference signal, the algebraic difference of the compensation signal, and the feedback signal size again;
When the algebraic difference between the reference signal and the compensation signal is greater than the feedback signal, maintaining the switch on the output stage is turned on, and the compensation signal continues to increase;
When the algebraic difference between the reference signal and the compensation signal is less than the feedback signal, turning off the switch on the output stage and turning on the lower switch, simultaneously reducing the compensation signal, and detecting the transformation The inductor current of the circuit reaches until the minimum off time. The control method of claim 17, wherein before the minimum off time is reached, if the inductor current is reduced to zero, the lower switch is turned off or controlled to operate at an equivalent Micro current source mode. The control method of claim 17, wherein the slope of the increase of the compensation signal is proportional to a difference between an input voltage and an output voltage of the conversion circuit;
The slope of the compensation signal reduction is proportional to the output voltage of the conversion circuit.