TWI409880B - Method for manufacturing a semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is disclosed. A semiconductor substrate such as bare silicon is provided, and a dielectric layer is formed over the semiconductor substrate. An opening is provided within the dielectric layer by removing a portion of the dielectric layer. A conformal first conductive layer is formed over the dielectric layer and the opening. A conformal second conductive layer is formed over the first conductive layer. A conformal barrier is formed over the second conductive layer.

Description

Method for manufacturing a semiconductor device

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a contact window barrier layer of a semiconductor device.

In the semiconductor industry, the past trend has been in the increase in wafer packing density, and the highly integrated semiconductor integrated circuit has been achieved by reducing the size of the device. As with other aspects of the integrated circuit process, the technology for making contact windows also needs to be continuously improved to keep up with the development of the process.

The contact window in the semiconductor integrated circuit provides an electrical connection between the metal conductor and the circuit component. In a general integrated circuit process, a dielectric layer is formed on a semiconductor substrate. The contact opening can be formed by etching the dielectric layer to the semiconductor substrate. Thereafter, the contact opening is filled with a conductive material such as titanium to provide an electrical connection between the metal conductor and the circuit component. In order to prevent a chemical reaction between the metal conductor and the substrate or between the metal conductors, a barrier layer (such as a titanium nitride layer) is usually deposited on the conductive layer as a barrier.

A known method for depositing a metal thin film is chemical vapor deposition (CVD). A common method of forming contact windows is to deposit titanium (Ti) by chemical vapor deposition and then deposit titanium nitride (TiN) by chemical vapor deposition. Since the CVD titanium deposition process is performed at a high temperature (e.g., about 500 ° C to 650 ° C), titanium oxide (TiSi ₂ ) is formed immediately after titanium deposition. FIGS. 1A and 1B illustrate a method of fabricating a contact window. As shown in FIG. 1A, a semiconductor substrate 102 having a dielectric layer 104 and an opening 106 is provided first. Thereafter, as shown in FIG. 1B, the titanium layer 110 is deposited by plasma assisted chemical vapor deposition (PECVD). Next, a titanium nitride barrier layer 114 is deposited by chemical vapor deposition prior to depositing a certain metal conductor 116 composed of aluminum or tungsten. The titanium telluride region 112 can be formed by the reaction of titanium with niobium.

An embodiment of the invention discloses a method of fabricating a semiconductor device. A semiconductor substrate (such as bare bristles) is first provided and a dielectric layer is formed over the semiconductor substrate. An opening can be provided in the dielectric layer by removing a portion of the dielectric layer. The conformal first conductive layer is formed on the dielectric layer and the opening, the conformal second conductive layer is formed on the first conductive layer, and the conformal barrier layer is formed on the second conductive layer.

In another embodiment of the invention, a semiconductor substrate (e.g., bare) is provided and a dielectric layer is formed over the semiconductor substrate. An opening can be provided in the dielectric layer by removing a portion of the dielectric layer. The conformal first conductive layer is formed on the dielectric layer and the opening, the selective barrier layer is formed on the first conductive layer, and the conformal second conductive layer is formed on the selective barrier layer, conformal The barrier layer is formed on the second conductive layer.

In another embodiment of the invention, a semiconductor substrate (e.g., bare) is provided and a dielectric layer is formed over the semiconductor substrate. An opening can be provided in the dielectric layer by removing a portion of the dielectric layer. The conformal first conductive layer is formed on the dielectric layer and the opening, the selective barrier layer is formed on the first conductive layer, and the conformal barrier layer is formed on the selective barrier layer.

Representative embodiments of the present invention are described in the following, and the same or similar elements are represented by the same reference numerals. 2A-2C is a first embodiment for explaining the method of manufacturing a contact window of the present invention, which first uses physical vapor deposition (PVD) to form a first titanium layer, and then uses plasma to assist the chemical vapor phase. A second titanium layer is deposited by deposition (PECVD) and a titanium nitride (TiN) layer is formed by chemical vapor deposition (CVD) to achieve a contact window with good conformal step coverage and no overhang formation. Barrier layer. The following is a detailed description of the manufacturing method of such a contact window.

Referring to FIG. 2A, the semiconductor substrate 202 can be ion implanted first to form highly doped regions (not shown), such as P ⁺ wells. Dielectric layer 204 is deposited or formed on semiconductor substrate 202. Semiconductor substrate 202 is typically bare, but it can also be germanium (SiGe) or other semiconductor materials. A portion of the dielectric layer 204 can be selectively removed to provide openings 206 in the dielectric layer 204, and the openings 206 can be patterned on the dielectric layer 204 using various lithography processes.

After the opening 206 is provided, the semiconductor device is placed in a chamber of a physical vapor deposition (PVD) process. In some embodiments, the chamber of the PVD process can be a chamber of an ionized metal plasma (IMP) PVD process or a chamber of a self-ionizing plasma (SIP) PVD process. As shown in FIG. 2A, a first conductive layer 208 (for example, a first titanium layer 208) is formed and may have a thickness of, for example, about 5 to 30 angstroms. In other embodiments, the first titanium layer 208 may have a thickness between 5 and 20 angstroms or between 10 and 15 angstroms. The first titanium layer 208 is formed on the dielectric layer 204 and the opening 206 by an IMP PVD process (i.e., a titanium process of IMP PVD). The formation of the first titanium layer 208 is performed in an environment such as 0 ° C to 400 ° C or in an environment such as 25 ° C to 300 ° C. Depending on the application, to achieve a conformal conductive layer 208, the process temperature can vary with the thickness of the conductive layer 208.

Compared to the deposition of a titanium layer by a CVD process (i.e., a CVD titanium process), a titanium telluride (TiSi ₂ ) layer is not formed simultaneously with the titanium layer in the PVD process. In other words, at the temperature of the PVD process, the reaction between titanium and tantalum does not necessarily be as strong as the corresponding reaction in the titanium process of CVD. Thus, a conformal first titanium layer 208 will be formed over dielectric layer 204. Compared to the CVD titanium process, the IMP PVD titanium process achieves a consistent contact resistance with a relatively simple controlled deposition process.

As the size of the semiconductor device continues to decrease to the sub-micron level, the aspect ratio of the contact window (ie, the ratio of the depth of the contact window to the width of the contact window) increases, and the step coverage properties (ie, the thickness of the film at the bottom of the contact window) The problem associated with the ratio of the thickness of the film on the side of the contact window will also become a bottleneck. In order to improve the step coverage and reduce the overhang phenomenon (ie the amount of material deposited in the contact window apex, it will limit the material that can be deposited in the contact window). The second conductive layer 210 (for example, the second titanium layer 210) is formed on the first conductive layer 208 as shown in FIG. To form the second titanium layer 210, the semiconductor device is moved from the PVD chamber to a chemical vapor deposition (CVD) chamber (such as a plasma assisted chemical vapor deposition (PECVD) chamber). Since the vacuum state is no longer present, the surface of the first titanium layer 208 will be exposed to the air, and the result of the oxidation will increase the surface resistance of the first titanium layer 208. Therefore, the RC value of the integrated circuit device will increase. However, in this embodiment, the titanium in the second titanium layer 210 formed after the CVD process absorbs oxygen in the air, thereby making the second titanium layer 210 have more stable properties (such as sheet resistance, better thickness). And conformality).

During the formation of the second titanium layer 210, a gas source (such as TiCl ₄ ) is introduced into the CVD chamber, and the second titanium layer 210 may be formed to a thickness of between about 5 and 400 angstroms, and preferably between Between 5 and 200 angstroms or between 50 and 100 angstroms. During the formation of the second titanium layer 210, the temperature can be controlled between about 350 ° C and 650 ° C, and preferably between 500 ° C and 650 ° C. In certain representative embodiments, the temperature can be between 600 ° C and 650 ° C depending on the application. Since the CVD process for forming the second titanium layer 210 is performed at a high temperature, a portion of the first titanium layer 208 can react with the material of the substrate to form a low resistance deuteration at the semiconductor substrate 202 exposed by the opening 206. Titanium (TiSi ₂ ) layer 212. Thus, by inert reaction of titanium (from the first titanium layer 208) and germanium (from the semiconductor substrate 202), the formation of the titanium telluride layer 212 will have a greater process margin, thereby increasing the heat of the titanium telluride layer 212. stability.

In order to prevent a chemical reaction between the metal conductor and the substrate or between the metal conductors, the barrier layer 214 may be formed on the second titanium layer 210 by a CVD process as a barrier, as shown in FIG. 2C. In one embodiment, the titanium source gas, the titanium chloride (TiCl ₄₎ and (NH ₃₎ are based on a flow rate of ammonia supplied as a reaction gas, thereby forming (TiN) layer, titanium nitride barrier layer 214. Thereby, titanium nitride is formed by the reaction of titanium chloride with ammonia. In another embodiment, if TaCl _{5 is} used as the titanium source, the resulting tantalum nitride (TaN) layer can also function as the barrier layer 214. In other embodiments, a tungsten nitride (WN) layer or a titanium tungsten (TiW) layer may also serve as the barrier layer 214. In one embodiment, the barrier layer 214 has a thickness between about 5 and 500 angstroms. In other embodiments, the barrier layer 214 may have a thickness between 50 and 200 angstroms or between 70 and 150 angstroms. In one embodiment, the CVD process can be performed at a temperature of from 350 ° C to 700 ° C. In other embodiments, the CVD process can be carried out at a temperature of from 400 ° C to 650 ° C, and preferably from 600 ° C to 650 ° C. It should be noted that the thickness of the barrier layer 214 and the formation temperature may be adjusted or optimized depending on its application.

As shown in FIGS. 2A-2C, the first titanium layer 208 is formed on the dielectric layer 204 and the opening 206 by a PVD process, and the second titanium layer 210 is formed on the first titanium layer 208 by a CVD process. Thereafter, a barrier layer 214 such as a titanium nitride or tantalum nitride layer is formed on the second titanium layer 210 by a CVD process. This combination of material layers provides better bottom coverage and conformal titanium nitride/tantalten nitride layer coverage. Referring to FIG. 2C, a metal layer 216 is formed on the barrier layer 214 to fill the opening 206.

After the barrier layer 214 is formed, a heat treatment (such as rapid thermal process (RTP)) may be selectively performed. The semiconductor device can be placed in a chamber filled with nitrogen and having a temperature between 500 ° C and 700 ° C. In various embodiments, the temperature within the chamber can be between 550 ° C and 650 ° C or between 600 ° C and 650 ° C. In one embodiment, the heat treatment is performed for a time of about 20 to 180 seconds. In other embodiments, the heat treatment is carried out for a period of 30 to 120 seconds or 40 to 60 seconds.

To enhance the performance of the barrier layer 214, an additional selective barrier layer 218 can be formed between the first conductive layer 208 and the second conductive layer 210, such as the second embodiment of the present invention shown in FIG. In one embodiment, the precursors such as tetrakis(diethylamine)titanate (TDEAT) and tetrakis are used by metal organic chemical vapor deposition (MOCVD) at a temperature of 350 ° C to 550 ° C. Titanium nitride (TDMAT), tetrakis(ethylmethylamine)titanium (TEMAT) or a mixture thereof is reacted with ammonia to deposit titanium nitride. The plasma is selectively applied to the chamber by introducing helium into the chamber at a rate and applying about 500 to 1000 watts of RF energy. The selective barrier layer 218 can also be treated with nitrogen plasma (see http://www. Patentstorm.us/patents6514850-description.html) or helium plasma treatment. Alternatively, the titanium nitride deposition may be sputtered by using a self-ionizing plasma method at a temperature of 400 ° C using titanium and nitrogen as gas sources and reaction sources, respectively. 3A is a scanning electron micrograph of a contact window barrier layer of a semiconductor device according to an embodiment of the present invention, wherein the contact window barrier layer comprises a titanium layer of IMP PVD having a thickness of about 80 angstroms and a thickness of about 25 angstroms. The titanium nitride layer of MOCVD and the titanium nitride layer of TiCl ₄ CVD having a thickness of about 160 angstroms, and the titanium nitride layer of TiCl ₄ CVD further comprises a columnar structure. In addition, the contact window barrier layer described above can be selectively subjected to a rapid thermal process at a temperature of 650 °C.

In a third embodiment of the present invention, as shown in FIG. 4, a first conductive layer 208 may be formed on the dielectric layer 204 and the opening 206 by a PVD process to form a thickness of about 10 to 400 angstroms. A conformal barrier layer 214 of between about 200 and 300 angstroms is preferred.

Therefore, a thickness of 5 to 100 angstroms is formed on the first conductive layer 208 by a self-ionizing plasma sputtering process or a metal organic chemical vapor deposition process before forming the barrier layer 214 (preferably 10 A selective barrier layer 218 of up to 50 angstroms.

After the selective barrier layer 218 is formed, a heat treatment (such as rapid thermal process (RTP)) may be selectively performed. The semiconductor device can be placed in a chamber filled with nitrogen and having a temperature between 500 ° C and 700 ° C. In various embodiments, the temperature within the chamber can be between 550 ° C and 650 ° C or between 600 ° C and 650 ° C.

Next, a barrier layer 214 (such as a titanium nitride or tantalum nitride layer) is formed on the selective barrier layer 218 by a CVD process. The barrier layer 214 may have a thickness between 20 and 200 angstroms or between 40 and 100 angstroms. The combination of such material layers produces a smooth bottom coverage, thus providing a conformal barrier layer. Next, a metal layer 216 is formed over the barrier layer 214 to fill the opening 206.

Figure 5 is a diagram showing the contact resistance distribution of an embodiment of the present invention, wherein the x-axis represents contact resistance (in ohms) and the y-axis represents distribution (expressed as a percentage).

As shown in FIG. 5, the curve in region 520 represents an increase in P+/N resistance to form a relatively long tail shape as compared to region 510. Curve 512 represents a resistor obtained in accordance with an embodiment of the present invention, wherein an IMP PVD process is used to form a first titanium layer 208 having a thickness of 5 to 30 angstroms, and a thickness 5 is formed on the first titanium layer 208 by a PECVD process. A second titanium layer 210 of 400 angstroms is formed, and a titanium nitride barrier layer 214 having a thickness of 5 to 500 angstroms is formed on the second titanium layer 210.

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

104, 204. . . Dielectric layer

102, 202. . . Semiconductor substrate

512. . . curve

112. . . Titanium telluride region

212. . . Titanium telluride layer

216. . . Metal layer

116. . . Metal conductor

214. . . Barrier layer

218. . . Selective barrier layer

510, 520. . . region

208. . . First conductive layer

210. . . Second conductive layer

114. . . Titanium nitride barrier layer

106, 206. . . Opening

110. . . Titanium layer

The foregoing summary and embodiments of the invention may be understood by reference to the embodiments of the invention.

1A and 1B are cross-sectional views for explaining a method of manufacturing a contact window in the prior art.

2A-2C is a cross-sectional view for explaining a method of manufacturing a contact barrier layer of a semiconductor device in the first embodiment of the present invention.

Figure 3 is a cross-sectional view for explaining a method of manufacturing a contact barrier layer of a semiconductor device in a second embodiment of the present invention.

3A is a scanning electron micrograph of a contact window barrier layer of a semiconductor device in accordance with an embodiment of the present invention.

Fig. 4 is a cross-sectional view for explaining a method of manufacturing a contact barrier layer of a semiconductor device in a third embodiment of the present invention.

Fig. 5 is a diagram showing the distribution of contact resistance according to an embodiment of the present invention.

202. . . Semiconductor substrate

204. . . Dielectric layer

208. . . First conductive layer

210. . . Second conductive layer

212. . . Titanium telluride layer

214. . . Barrier layer

216. . . Metal layer

218. . . Selective barrier layer

Claims (32)

A method of fabricating a semiconductor device, the method comprising: providing a substrate; forming a dielectric layer on the substrate; providing an opening in the dielectric layer; forming a first layer on the dielectric layer and the opening a conductive titanium layer; forming a second conductive titanium layer on the first conductive titanium layer; and forming a barrier layer on the second conductive titanium layer. The method of claim 1, wherein the step of forming the first conductive titanium layer comprises using a physical vapor deposition, an ionized metal plasma physical vapor deposition, and a self-ionizing physical vapor deposition. At least one. The method of claim 1, wherein the first conductive titanium layer has a thickness of between about 5 and 30 angstroms. The method of claim 1, wherein the step of providing the opening in the dielectric layer comprises removing a portion of the dielectric layer. The method of claim 1, wherein the barrier layer comprises at least one of titanium nitride, tantalum nitride, tungsten nitride, and titanium tungsten or a combination thereof. The method of claim 1, wherein the step of forming the barrier layer comprises forming the barrier layer with titanium chloride and ammonia. The method of claim 1, further comprising tempering the barrier layer in a chamber containing nitrogen. The method of claim 1, further comprising the first conductive A selective barrier layer is formed between the titanium layer and the second conductive titanium layer. The method of claim 8, wherein the step of forming the selective barrier layer comprises forming a thickness of about 5 to 100 angstroms using one of a self-ionizing plasma method and a metal organic chemical vapor deposition method. The selective barrier layer. The method of claim 8, wherein the selective barrier layer comprises titanium nitride. The method of claim 9, wherein the self-ionizing plasma method is carried out in an environment having a titanium target at a temperature of about 50 ° C to 400 ° C. The method of claim 9, wherein the self-ionizing plasma method uses titanium as a gas source and nitrogen as a reaction source. The method of claim 9, wherein the metal organic chemical vapor deposition method comprises using titanium tetrakis(diethylamine), titanium tetrakis(dimethylamine), and tetrakis(ethylmethyl). At least one of the precursors of titanium and a mixture thereof. The method of claim 9, wherein the metal organic chemical vapor deposition is carried out at a temperature of from about 350 ° C to about 550 ° C. The method of claim 9, wherein the metal organic chemical vapor deposition is carried out in an environment having helium or neon and nitrogen. The method of claim 9, wherein the selective barrier layer formed by the metal organic chemical vapor deposition method is subjected to a nitrogen plasma treatment or a helium gas with a radio frequency energy of about 500 to about 1000 watts. Slurry treatment. The method of claim 1, further comprising forming a metal layer on the barrier layer to fill the opening. The method of claim 1, wherein the step of forming a second conductive titanium layer on the first conductive titanium layer comprises using a plasma assisted chemical vapor deposition. The method of claim 1, wherein the step of forming a barrier layer on the second conductive titanium layer comprises performing a chemical vapor deposition process. The method of claim 1, wherein the barrier layer has a thickness of about 5 to 500 angstroms. The method of claim 1, wherein the barrier layer comprises at least one of titanium nitride, tantalum nitride, tungsten nitride or titanium tungsten, and combinations thereof. The method of claim 1, wherein the step of forming the barrier layer comprises using titanium chloride and ammonia. A semiconductor device comprising: a substrate; a dielectric layer on the substrate, the dielectric layer having an opening; a first conductive titanium layer on the substrate and the opening; a second a conductive titanium layer on the first conductive titanium layer; and a barrier layer on the second conductive titanium layer. The semiconductor device of claim 23, wherein the barrier layer comprises a columnar structure. The semiconductor device according to claim 23, further comprising an attached And a barrier layer is disposed between the second conductive titanium layer and the barrier layer. The semiconductor device according to claim 25, wherein the barrier layer comprises a titanium nitride layer formed by self-ionized plasma physical vapor deposition or a nitrogen formed by metal organic chemical vapor deposition. Titanium layer. The semiconductor device of claim 23, wherein the first conductive titanium layer comprises a titanium layer formed by ionized metal plasma physical vapor deposition. The semiconductor device of claim 23, wherein the second conductive titanium layer comprises a titanium layer formed of titanium chloride. The semiconductor device of claim 23, wherein the barrier layer comprises a titanium nitride layer formed of titanium chloride. The semiconductor device of claim 23, wherein the first conductive titanium layer has a thickness of between about 10 and 400 angstroms. The semiconductor device of claim 23, wherein the second conductive titanium layer has a thickness of between about 5 and 100 angstroms. The semiconductor device of claim 23, wherein the barrier layer has a thickness of between about 20 and 200 angstroms.