TWI409644B - Data encryption / decryption control method and its circuit - Google Patents

Abstract

The present invention is related to a method of data encryption and decryption and the circuit thereof. An encryption and decryption circuit is used to connect the micro processor and a advanced encryption standard algorithms module. The advanced encryption standard algorithms module is used by the micro processor to process the data encryption and decryption. Besides, the micro processor is connected to encryption and decryption circuit through 1-127 pins to save the micro processor pin numbers for data encryption and decryption.

Description

Data encryption/decryption control method and circuit thereof

The invention relates to a data encryption/decryption control method and a circuit thereof, in particular to a data encryption/decryption control method and a circuit thereof suitable for an advanced encryption standard algorithm module.

AES encryption technology is an encryption standard completed by the National Institute of Standards and Technology (NIST), which supports 128, 192, and 256-bit encryption lengths. AES encryption technology provides a long-lasting data security and security, so it is widely used in various government units and private companies to make the transmission of personal data and financial transactions through the use of ATMs, online shopping or e-mail. Sex is increased.

AES algorithm chips that implement AES encryption technology are generally designed to provide data and keys to be added/decrypted, respectively, via an input buffer and a key generation module to obtain the data necessary for performing the encryption/decryption calculation. However, as the encryption length supported by AES encryption technology increases, the number of pins required for its input and output buffers also increases. For example, an AES 128 chip implementing the AES 128 standard requires 128 pins. However, because the number of pins provided by the general microprocessor is limited, the large number of AES algorithm chip docking pins will limit the opportunity for the microprocessor to use AES encryption technology to ensure data transmission security. Therefore, the microprocessor data transmission cannot be performed. One of the biggest risks is the use of AES encryption technology to increase its risk.

One object of the present invention is to provide a data encryption/decryption control method and a circuit thereof, which can use an advanced encryption standard algorithm module for data encryption or data decryption.

Another object of the present invention is to provide a data encryption/decryption control method and circuit thereof, which can save the number of pins used by a microprocessor for data encryption or data decryption.

To achieve the above object, the present invention provides a data encryption/decryption control method, comprising the steps of: (A) electrically connecting a data encryption/decryption control circuit to at least one output of an advanced encryption standard algorithm module and at least Between an input port and a microprocessor, the data encryption/decryption control circuit is electrically connected to the microprocessor by 1 to 127 pins; and (B) receives a command written from the pin; (C) Receiving a clear text from the pin and providing it to the advanced encryption standard algorithm module; and (D) receiving an execution encryption command from the pin and controlling the advanced encryption standard algorithm module with the data encryption/decryption control circuit to perform the plaintext data Encryption calculation.

In order to achieve the above object, the present invention further provides a data encryption/decryption control circuit, comprising: a first demultiplexing unit, a control temporary storage unit, an advanced encryption standard algorithm control unit, a receiving shift temporary storage unit, A second demultiplexing unit, a multiplexing unit, and a transceiving shift register unit. The first demultiplexing unit receives a plaintext data and a key data, and controls the temporary storage unit to electrically connect to the first demultiplexing unit. The advanced encryption standard algorithm control unit is electrically connected to the control temporary storage unit and the advanced encryption standard algorithm module to control the operation of the advanced encryption standard algorithm module. The receiving shift temporary storage unit is electrically connected to the first demultiplexing unit and the control temporary storage unit, and the second demultiplexing unit is electrically connected to the control temporary storage unit, the receiving shift temporary storage unit and the advanced encryption standard algorithm module. The multiplex unit is electrically connected to the control temporary storage unit and the advanced encryption standard algorithm module, and the transceiving and shifting temporary storage unit is electrically connected to the control temporary storage unit and the multiplex unit. The control temporary storage unit controls the operations of the first demultiplexing unit, the receiving shift temporary storage unit, the receiving shift temporary storage unit, the second demultiplexing unit, the multiplexing unit, and the transceiving and shifting temporary storage unit to clear the plaintext The data and key data are provided to the advanced encryption standard algorithm module via the second demultiplexing unit for encryption calculation to generate a ciphertext data.

In the present invention, the following steps may be further included to output the encrypted ciphertext data: (E) transmitting a completion signal from the pins when the advanced encryption standard algorithm module performs the encryption calculation; (F) The pins receive a read command and control the advanced encryption standard algorithm module with a data encryption/decryption control circuit to read a ciphertext data; and (G) output ciphertext data from the pins.

In addition, the present invention may further include the following steps for decrypting a piece of ciphertext data: (H) receiving a ciphertext data from the pins and providing the advanced cryptographic standard algorithm module; and (I) The pins receive an execution decryption command and control the advanced encryption standard algorithm module to decrypt the ciphertext data by using the data encryption/decryption control circuit.

After the decryption is completed, the present invention may further perform the following steps to output the decrypted plaintext data: (J) transmitting a completion signal from the pins when the advanced encryption standard algorithm module completes the decryption calculation; (K) Receiving a read command from the pins and controlling the advanced encryption standard algorithm module to read a plaintext data by the data encryption/decryption control circuit; and (L) outputting the plaintext data from the pins. Therefore, via the method and circuit of the present invention, the microprocessor can use the optical encryption standard algorithm module for data encryption or data decryption.

The above step (D) or step (I) may further comprise receiving a write key instruction from the pins and receiving a key data, and in step (D), the key material may be provided to an advanced encryption standard. The algorithm module performs encryption calculation via the key material. In step (I), the key material can be provided to the advanced encryption standard algorithm module for decryption calculation via the key material.

The amount of data written in the above instruction, executing the encryption instruction or executing the decryption instruction corresponds to the number of pins electrically connected to the data encryption/decryption control circuit and the microprocessor, and the first demultiplexing unit and the transceiving shift temporary storage Preferably, the unit is electrically connected to the microprocessor by 1 to 127 pins, respectively, so the amount of data may be between 1 and 127, but preferably a byte. The general advanced encryption standard algorithm module needs to use more than 128 pins, so the second solution multiplex unit is electrically connected with the advanced encryption standard algorithm module with 128~256 pins. However, for microprocessors, the present invention does save the number of pins that the microprocessor uses for data encryption or data decryption. Therefore, the data transmission/decryption control circuit and the microprocessor can transfer 1~127 bits at a time, so that the data can be received/outputd once in step (C), step (G) or step (L). The ~127 bit mode receives/outputs plaintext/ciphertext data.

On the other hand, the format of writing the instruction, executing the encryption instruction, executing the decryption instruction, writing the key instruction or the reading instruction is not limited, and the instruction written in the present invention preferably represents the instruction by a first bit, The value of the second bit represents the text and the write is represented by a third bit. The execution of the encrypted instruction preferably represents the data in a first bit, the execution in a second bit, and a third bit. The element represents encryption, and the execution of the decryption instruction preferably represents the data by a first bit, the execution by a second bit, and the decryption by a third bit. The write key command is preferably a first bit. The meta indicates an instruction, the key is represented by a second bit value, and the write is represented by a third bit. The read command preferably represents the instruction by a first bit and the read by a second bit. Out.

In the present invention, the first demultiplexing unit, the control temporary storage unit, the advanced encryption standard algorithm control unit, the receiving shift temporary storage unit, the second demultiplexing unit, the multiplexing unit, and the transceiving and shifting temporary storage unit may be A clock signal and a reset signal are respectively received to operate according to the signals. The receiving shift register unit and the transceiving shift register unit can further receive a synchronous clock signal to synchronize the operation thereof.

Therefore, the present invention connects a data encryption/decryption control circuit between the microprocessor and the advanced encryption standard algorithm module, so that the microprocessor can use the advanced encryption standard algorithm module for data encryption or data decryption. In addition, the microprocessor is connected to the data encryption/decryption control circuit with 1~127 pins to save the number of pins used by the microprocessor for data encryption or data decryption.

Please refer to FIG. 1 , which is a structural diagram of a data encryption/decryption control circuit system according to a preferred embodiment of the present invention. As shown in the figure, the data encryption/decryption control circuit 1 includes a first demultiplexing unit 11, a control temporary storage unit 12, an advanced encryption standard algorithm control unit 13, a receiving shift temporary storage unit 14, and a The second demultiplexing unit 15, a multiplexing unit 16, and a transceiving shift register unit 17 are provided.

The first demultiplexing unit 11 and the transceiving shift register unit 17 are electrically connected to an input/output port 31 of the microprocessor 3 to receive/transmit instructions or data with the microprocessor 3, and the first demultiplexing unit 11 and The electrical connection between the transceiving shift register unit 17 and the input port 31 can be transmitted through less than 128 pins, for example, 1~127 pins to save the microprocessor 3 for data encryption or data decryption. The number of pins is eight pins in this embodiment. Therefore, the size of the data of the command or data sent by the microprocessor 3 is exemplified by one byte. The advanced encryption standard algorithm control unit 13 is electrically connected to the control temporary storage unit 12 and an advanced encryption standard algorithm module 2. The control temporary storage unit 12 controls the operation of the advanced encryption standard algorithm module 2 to perform encryption or decryption calculation by the advanced encryption standard algorithm control unit 13 according to the instruction from the microprocessor 3. The advanced encryption standard algorithm control unit 13 and the advanced The number of pins that are electrically connected between the encryption standard algorithm module 2 depends on the requirements of the advanced encryption standard algorithm module 2. For example, the AES 128 standard requires 128 pins, and the AES 192 standard requires 192 connections. The foot, in this embodiment, is through 128 pins. The receiving shift temporary storage unit 14 is electrically connected to the first demultiplexing unit 11 and the control temporary storage unit 12, and the second demultiplexing unit 15 is electrically connected to the control temporary storage unit 12, the receiving shift temporary storage unit 14 and the advanced encryption. Standard algorithm module 2. The multiplex unit 15 is electrically connected to the control temporary storage unit 12 and the advanced encryption standard algorithm module 2. The transceiver shift register unit 17 is electrically connected to the control temporary storage unit 12 and the multiplex unit 15.

Please refer to FIG. 2 , which is a schematic diagram of a clock signal of a data encryption/decryption control circuit according to a preferred embodiment of the present invention. As shown in the figure, when an instruction or a piece of data is input from the microprocessor 3 to the first demultiplexing unit 11, the first demultiplexing unit 11 transmits its input instruction or data to the control temporary storage unit 12. The control temporary storage unit 12 generates eight clock signals S100, S101, S102, S103, S104, S105, S106, S107 according to the eight bit values of the instruction or the data, wherein the S100 captures the instruction or the data bit 0 The value, S101 captures the value of the first bit of the instruction or data, and so on other S102~S107. The first demultiplexing unit 11, the control temporary storage unit 12, the advanced encryption standard algorithm control unit 13, the receiving shift temporary storage unit 14, the second demultiplexing unit 15, the multiplexing unit 16, and the transceiving shift temporary storage unit 17 respectively receives a clock signal S100/S101/S102/S103/S104/S105/S106/S107 and a reset signal (not shown) to operate according to the signals. In this embodiment, the control temporary storage unit 12 controls the operation of the first demultiplexing unit 11 by the clock signal S107, and controls the operation of the second demultiplexing unit 15 by the clock signal S106, which is a clock signal. S105 controls the operation of receiving the shift register unit 14, and controls the operation of the transceiving shift register unit 17 by the clock signal S104, and controls the operation of the advanced encryption standard algorithm control unit 13 by the clock signal S103. The pulse signal S102 controls the operation of the multiplex unit 16 and the advanced encryption standard algorithm control unit 13, and the clock signal S100 and the time pulse signal S101 are not used. In addition, the receiving shift register unit 14 and the transceiving shift register unit 17 further receive a synchronous clock signal (SCK) to synchronize their operations.

Please also refer to FIG. 3, which is an instruction list input by the microprocessor 3 in the embodiment. As shown in the figure, the data encryption/decryption control circuit 1 can receive a write key instruction from the eight pins between the first demultiplexing unit 11 and the transceiving shift register unit 17 and the input/output buffer 31, An input to the instruction herein, a read command, an execution of the encrypted instruction, or an execution of the decrypted instruction. In this embodiment, when the value of the 7th bit of the instruction is 0, the input is an instruction, and 1 is a piece of data. When the value of the 6th bit is 0, the input is a key data, 1 is the data in this paper. When the value of the 5th bit is 1, the input is written. When the value of the 4th bit is 1, the input is read. When the value of the third bit is 1, Indicates that this input needs to perform the encryption/decryption calculation. When the value of the second bit is 0, it indicates the encryption calculation, and the value of 1 indicates the decryption calculation.

Further, in addition to the instruction transmitted from the microprocessor 3, after the data encryption/decryption control circuit 1 is activated, the control temporary storage unit 12 automatically executes an initial instruction, which is 0X00 in the present embodiment. The control temporary storage unit 12 generates the clock signals S100~S107 according to the initial command to control all other circuit blocks to perform the initial actions.

Please also refer to FIG. 4, which is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention. When the data encryption/decryption control circuit 1 inputs the write key command, since the 7th bit is 1, the control temporary storage unit 12 determines that the data is input after the subsequent write key command, so the temporary storage unit 12 is controlled. The clock signal S107 controls the data transfer direction of the first demultiplexing unit 11 to be transmitted to the receive shift register unit 14 (step 410). Next, the data encryption/decryption control circuit 1 inputs a key data through a pin electrically connected to the microprocessor 3 (step 420), where it is input by receiving an 8-bit at a time. Because the value of the fifth bit of the write key command is 1, the control temporary storage unit 12 controls the receive shift temporary storage unit 14 to start with the clock signal S105, and shifts the input key data to the first The second solution multiplex unit 15. In this embodiment, the receiving shift temporary storage unit 14 performs shift processing on the key data according to the synchronous clock signal SCK to generate a 128-bit size data output to the second demultiplexing unit 15. Because the sixth bit value of the write key command is 0, the second demultiplexing unit 15 provides the key data according to the control of the clock signal S106 and stores the corresponding storage in the advanced encryption standard algorithm module 2. region.

Please refer to FIG. 5, which is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention. In this figure, an encryption calculation is performed. When the data encryption/decryption control circuit 1 inputs the instruction written in this document, since the 7th bit is 1, the control temporary storage unit 12 determines that the connection is input from the pin electrically connected to the microprocessor 3, so that the control is performed. The first demultiplexing unit 11 transmits the data to the reception shift register unit 14 (step 510). Next, a plaintext material is input from the microprocessor 3 (step 520), where it is input in such a manner that one bit is transmitted at a time. Because the value of the fifth bit of the instruction is 1, the control temporary storage unit 12 controls the receiving shift register unit 14 with the clock signal S105 to start the displacement processing of the input plaintext data and then transmit it to the second unmultiplexed operation. Unit 15. Because the sixth bit value of the instruction is 1, the second demultiplexing unit 15 provides and stores the plaintext data to the corresponding storage area in the advanced encryption standard algorithm module 2 according to the control of the clock signal S106. . In the present embodiment, when the key material or the data herein is completely input to the data encryption/decryption control circuit 1, it executes the initial instruction again to wait for the next instruction input. Thereafter, an encryption instruction is input from the microprocessor 3 (step 530). Since the 7th bit of the encryption instruction is 0, the control temporary storage unit 12 determines that the input is an instruction, and starts the advanced encryption standard algorithm control unit 13 with the clock signal S103, and controls the multiplex unit 16 with the clock signal S102. . The advanced encryption standard algorithm control unit 13 controls the advanced encryption standard algorithm module 2 to perform encryption calculation according to the clock signal S102. The multiplex unit 16 sets the output data identity received after the encryption calculation is completed according to the clock signal S102 to be ciphertext data. When the advanced encryption standard algorithm module 2 performs the encryption calculation, its output a completion signal (done) informs the microprocessor 3 that the microprocessor 3 can know whether the encryption calculation is completed (step 540). Thereafter, a read command is input from the microprocessor 3 (step 550). Since the 7th bit of the read command is 0, the control temporary storage unit 12 judges that the input is an instruction. Since the 4th bit of the read command is 1, the control temporary storage unit 12 controls the transceiving and shifting temporary storage unit 17 to perform the displacement processing by the clock signal S104, and shifts the encrypted ciphertext data stored in the multiplex unit 16 by the encryption. The processing is to generate 16 octet-sized ciphertext data, and output to the output port 31 (step 560).

Please refer to FIG. 6 , which is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention, and FIG. 6 is a decryption calculation. The difference between this figure and the above figure is that after the input command is written (step 610), a ciphertext data is input from the microprocessor 3 (step 620), where the input is performed by one bit at a time. . Thereafter, a decryption command is input from the microprocessor 3 (step 630). Since the 7th bit of the decryption instruction is 0, the control temporary storage unit 12 determines that the input is an instruction, and starts the advanced encryption standard algorithm control unit 13 with the clock signal S103, and controls the multiplex unit 16 with the clock signal S102. . The advanced encryption standard algorithm control unit 13 controls the advanced encryption standard algorithm module 2 to perform decryption calculation according to the clock signal S102. The multiplex unit 16 sets the output data identity received after the encryption calculation is completed according to the clock signal S102 to be plaintext data. When the advanced encryption standard algorithm module 2 performs the decryption calculation, its output a completion signal (done) informs the microprocessor 3 that the microprocessor 3 can know whether the decryption calculation is completed (step 640). Thereafter, a read command is input from the microprocessor 3 (step 650). Since the 4th bit of the read command is 1, the control temporary storage unit 12 controls the transceiving and shifting temporary storage unit 17 to perform the shift processing by the clock signal S104, and shifts the plaintext data stored in the multiplex unit 16 by the decrypted calculation. The plaintext data of 16 8-bit size is generated and output to the output port 31 (step 660).

Therefore, as can be seen from the above, the present invention connects a data encryption/decryption control circuit between the microprocessor and the advanced encryption standard algorithm module, so that the microprocessor can use the advanced encryption standard algorithm module. Data encryption or data decryption. In addition, the microprocessor is connected to the data encryption/decryption control circuit with 1~127 pins to save the number of pins used by the microprocessor for data encryption or data decryption.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

Data encryption/decryption control circuit. . . 1

Advanced encryption standard algorithm module. . . 2

microprocessor. . . 3

The first solution multiplex unit. . . 11

Control the temporary storage unit. . . 12

Advanced encryption standard algorithm control unit. . . 13

Receive shift register unit. . . 14

The second solution multiplex unit. . . 15

Multiplex unit. . . 16

Send and receive shift register unit. . . 17

Output into the 埠. . . 31

step. . . 410,420,510,520,530,540,550,560,610,620,630,640,650,660

1 is a structural diagram of a data encryption/decryption control circuit system according to a preferred embodiment of the present invention.

2 is a schematic diagram of a clock signal of a data encryption/decryption control circuit according to a preferred embodiment of the present invention.

3 is a list of instructions that can be input by a microprocessor in accordance with a preferred embodiment of the present invention.

4 is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention.

FIG. 5 is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention.

6 is a schematic diagram of a data encryption/decryption control method according to a preferred embodiment of the present invention.

Data encryption/decryption control circuit. . . 1

Advanced encryption standard algorithm module. . . 2

microprocessor. . . 3

The first solution multiplex unit. . . 11

Control the temporary storage unit. . . 12

Advanced encryption standard algorithm control unit. . . 13

Receive shift register unit. . . 14

The second solution multiplex unit. . . 15

Multiplex unit. . . 16

Send and receive shift register unit. . . 17

Claims (22)

A data encryption/decryption control method includes the following steps: (A) electrically connecting a data encryption/decryption control circuit to at least one output port of an advanced encryption standard algorithm module and at least one input port and a microprocessor Between the data encryption/decryption control circuit is electrically connected to the microprocessor by 1~127 pins; (B) receiving a write command from the pins; (C) from the pins Receiving a plaintext data and providing the advanced encryption standard algorithm module; (D) receiving an execution encryption instruction from the pins and controlling the advanced encryption standard algorithm module with the data encryption/decryption control circuit The plaintext data is encrypted and calculated; (E) when the advanced encryption standard algorithm module completes the encryption calculation, a completion signal is transmitted from the pins; (F) receiving a read command from the pins and using the data The encryption/decryption control circuit controls the advanced encryption standard algorithm module to read a piece of ciphertext data; and (G) outputs the ciphertext data from the pins. The data encryption/decryption control method according to claim 1, wherein the size of the instruction written in the instruction and the execution of the encryption instruction is one byte. The data encryption/decryption control method according to claim 1, wherein the instruction is written by a first bit, the second bit is represented by a second bit, and the third bit is The meta indicates the write. The data encryption/decryption control method according to claim 1, wherein the execution encryption instruction indicates data by a first bit, execution by a second bit, and a third bit. Indicates encryption. The data encryption/decryption control method according to claim 1, wherein the step (C) receives the plaintext data in a manner of receiving 1 to 127 bits at a time. The data encryption/decryption control method according to claim 1, wherein the step (D) further comprises receiving a write key instruction from the pins and receiving a key data. The data encryption/decryption control method according to claim 6, wherein the write key instruction is a first bit representation instruction, a second bit value representation key, and a first Three bits represent writes. The data encryption/decryption control method according to claim 6, wherein the key data is provided to the advanced encryption standard algorithm module to perform encryption calculation via the key data. The data encryption/decryption control method according to claim 1, wherein the read command is a first bit representation instruction and a second bit value representation. The data encryption/decryption control method according to claim 1, wherein the step (G) outputs the ciphertext data in a manner of outputting 1 to 127 bits at a time. For example, the data encryption/decryption control method described in claim 1 further includes the following steps: (H) receiving a ciphertext data from the pins and providing the advanced cryptographic standard algorithm module; and (1) receiving an execution decryption command from the pins and controlling the data by the data encryption/decryption control circuit The advanced encryption standard algorithm module decrypts the ciphertext data. The data encryption/decryption control method according to claim 11, wherein the size of the execution decryption instruction is one byte. The data encryption/decryption control method according to claim 11, wherein the execution decryption instruction represents the data by a first bit, the execution by a second bit, and a third bit. Indicates decryption. The data encryption/decryption control method according to claim 11, wherein the step (I) further comprises receiving a write key instruction from the pins and receiving a key data. The data encryption/decryption control method according to claim 14, wherein the key data is provided to the advanced encryption standard algorithm module to perform decryption calculation via the key data. For example, the data encryption/decryption control method described in claim 11 further includes the following steps: (J) transmitting a completion signal from the pins when the advanced encryption standard algorithm module completes the decryption calculation; (K) receiving a read command from the pins and controlling the advanced encryption standard algorithm module with the data encryption/decryption control circuit to read a plaintext data; (L) output the plaintext data from the pins. For example, the data encryption/decryption control method described in claim 16 is characterized in that the step (L) outputs the plaintext data in a manner of outputting 1 to 127 bits at a time. A data encryption/decryption control circuit comprises: a first demultiplexing unit, receiving a plaintext data and a key data; a control temporary storage unit electrically connected to the first demultiplexing unit; and an advanced encryption standard calculation The control unit is electrically connected to the control temporary storage unit and the advanced encryption standard algorithm module to control the operation of the advanced encryption standard algorithm module; and the receiving shift temporary storage unit electrically connects the first solution a unit and the control temporary storage unit; a second demultiplexing unit electrically connected to the control temporary storage unit, the receiving shift temporary storage unit and the advanced encryption standard algorithm module; a multiplex unit, electrical Connecting the control temporary storage unit and the advanced encryption standard algorithm module; and a transceiver shift temporary storage unit electrically connected to the control temporary storage unit and the multiplexing unit; wherein the control temporary storage unit controls the first Decomposing the multiplex unit, the receiving shift register unit, the receiving shift register unit, the second demultiplexing unit, the multiplexing unit, and the transceiving shift register unit to read the plaintext data and The key data is provided to the advanced encryption standard algorithm module via the second demultiplexing unit for encryption calculation to generate a secret document The receiving shift register unit and the transceiving shift register unit receive a synchronous clock signal. The data encryption/decryption control circuit according to claim 18, wherein the first demultiplexing unit and the transceiving and shifting storage unit are respectively electrically connected with 1 to 127 pins and a microprocessor. connection. The data encryption/decryption control circuit of claim 19, wherein the ciphertext data is transmitted to the microprocessor via the pins. The data encryption/decryption control circuit of claim 18, wherein the second demultiplexing unit is electrically connected to the advanced encryption standard algorithm module by 128 to 256 pins. The data encryption/decryption control circuit according to claim 18, wherein the first demultiplexing unit, the control temporary storage unit, the advanced encryption standard algorithm control unit, the receiving shift temporary storage unit, The second demultiplexing unit, the multiplex unit, and the transceiving shift register unit receive a clock signal and a reset signal.