TWI408553B - A memory management system and a memory management method - Google Patents

Abstract

A memory management system and a memory management method are disclosed. The memory management system includes a main memory, a least one secondary memory and a memory management device. The main memory includes a normal access memory bank and a least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device read/write the normal access memory bank or the secondary access memory bank.

Description

Memory management system and method

The present invention relates to a memory access technology, and more particularly to a memory management system and management method.

The range of address points that a typical microprocessor system can address is limited by the number of address lines in the address bus. In the case of today's digital systems, the processor addresses the number of address lines of two, for example, 16 address lines, which can be addressed in the range of two to the 16th power, that is, 65,536 addresses. However, in most octet microprocessor systems, due to architecture and cost considerations, the number of address lines is minimized. Therefore, the application is often limited by the addressing capability of the microprocessor system, and it is impossible to add more memory. In the micro-processing system, the function of the micro-processing system is limited.

Memory is a critical resource in microprocessor systems. The size of the memory is limited by the addressing range of the microprocessor and the cost of the overall system. Therefore, how to provide the largest memory resources for system use under the appropriate consideration of various factors is a very important issue.

In view of the above problems, one of the objects of the present invention is to provide a memory management system and method, which can achieve the effects of reducing the pin of the physical address line, improving the flexibility of memory expansion, and reducing the production cost.

An embodiment of the present invention provides a memory management system. The memory management system includes a main memory, at least one level memory, and a memory management device. The main memory includes a normal access block and at least one switch access block. Secondary memory contains corresponding switch access At least one data block of the block. The memory management device reads and writes the normal access block or the secondary data block according to the at least one request signal; wherein, when the request signal requires reading and writing the secondary data block, the memory management device reads the data of the data block Move to the switch access block, or write a data to be written to the secondary data block through the mapping of the switch access block.

Another embodiment of the present invention provides a memory management system. The memory management system includes a memory switching controller, a main memory, at least one level memory, and a direct memory access controller. The memory switching controller generates a control signal according to at least one request signal. The main memory includes a normal access block and at least one switching access block, and determines how to switch the access blocks according to the control signal, and how to read and write the normal access block or switch the access block. The secondary memory includes at least one data block corresponding to the switched access block. The direct memory access controller moves the data of the secondary data block to the switching access block according to the control signal, or writes the data to be written into the secondary data block through the mapping of the switching access block.

Another embodiment of the present invention provides a memory management system. The memory management system includes a main memory, at least one data block, and a memory management device. The main memory includes a normal access block and at least one switch access block. The secondary data block corresponds to the switching access block. The memory management device is used to read and write a normal access block or a secondary data block. Wherein, when the memory management device reads and writes the secondary data block, the memory management device moves the data of the secondary data block to the switching access block, or passes the data to be written through the switching access block. The map is written to the secondary data block.

Another embodiment of the present invention provides a memory management method. The method includes the following steps. First, a normal access block and at least one switch access block are provided. The data block is provided at least once, and the secondary data block corresponds to a switch access block. Then, receiving a request signal, the request signal includes at least one address, at least one of the information to be written, or both. After that, according to the request signal, the normal access block or the secondary data block is read and written; when the address requested by the signal is located in the address range of the normal access block, the normal access block is read to correspond to the address. Data, or write the data to be written into the normal access block; when the address requested by the signal is located in the address range of the secondary data block, the data corresponding to the address of the data block is moved to the switch The block is accessed, and the data is read in the switch access block, or the data to be written is written into the secondary data block through the mapping of the switch access block.

The memory management system and the management method of the embodiment of the present invention are configured to map a normal access block and at least one switch access block in the main memory, and cooperate with the mapping of the switch access block to read and write times. The secondary data block of the level memory. In this way, the memory management system and the management method of the embodiment of the present invention can reduce the number of addresses and the memory space without limitation by the user or the designer under a limited memory address range, thereby achieving a reduction in memory. The number of pins required for addressing, the flexibility to expand memory space, and the overall system cost.

Fig. 1A is a view showing a memory management system according to an embodiment of the present invention. The memory management system 100 includes a processor 101, a main memory 102, a primary memory 103, and a memory management device 104.

The processor 101 can be a central processing unit (Central processing unit, CPU), Microprocessor unit (MPU), Microprocessor control unit (MCU), and other existing or future development of various processing devices. The processor 101 is configured to issue a request signal Rq for accessing data of the memory.

The main memory 102 can be a static random access memory (SRAM), a variety of memory currently available or developed in the future. The main memory 102 includes a normal access block and at least one switch access block. In one embodiment, as shown in FIG. 1B, the memory space of the main memory 102 includes a normal access block Nab and a switch access block Sab. It should be noted that, in this embodiment, the main memory 102 includes only one switching access block Sab; in another embodiment, the main memory 102 may also include a plurality of switching access blocks Sab.

The secondary memory 103 can be one of a flash memory, a hard disc (disk), an optical disc (disk), or a combination thereof, or other storage devices that are currently or in the future. . The secondary memory 103 includes at least one secondary data block corresponding to the switched access block. In one embodiment, as shown in FIG. 1B, the secondary memory 103 includes N (N is a positive integer, and is less than infinite) secondary data blocks Sub1 to SubN. The sub-data block Sub1~SubN corresponds to the switching access block Sab, that is, the switching access block Sab stores the address of the sub-data block Sub1~SubN, and the address can be utilized when the system performs data replacement. Data mapping is performed to move the data of any of the data blocks Sub1~SubN to the switching access block. Of course, the data may be written into any of the data blocks Sub1~SubN according to the mapping of the addresses by switching the access block Sab. In addition, the size of the secondary data blocks Sub1~SubN is equal to the size of the switching access block Sab, and the secondary data blocks Sub1~SubN can store the codes (Codes) used by the processor 101.

The memory management device 104 reads (accesses) or according to at least one request signal Rq or The data is written into the normal access block Nab of the main memory 102 or the data blocks Sub1~SubN of the corresponding switching access block Sab. When the request signal Rq is required to read (access) any of the data blocks Sub1~SubN, the memory management device 104 moves the data of the designated data block Sub1~SubN according to the address provided by the request signal Rq. Up to the switching access block Sab, or according to the data and address provided by the request signal Rq, the data to be written by the microprocessor 101 is written into the data specified by the address through the mapping of the switching access block Sab. Blocks Sub1~SubN. It should be noted that if the data required to be read by the request signal Rq has been stored in the switching access block Sab, the memory management device 104 directly accesses the data. In addition, the data read by the memory management device 104 determines where to transmit according to the instruction of the request signal Rq. In this embodiment, the request signal Rq is required to transmit data to the microprocessor 101; another embodiment The request signal Rq may also request that the data be transmitted to other devices inside or outside the system (not shown).

In one embodiment, as shown in FIG. 1A, the memory management device 104 includes a memory switching controller 104a and a direct memory access controller (DMA) 104b. The memory switching controller 104a generates a control signal C based on the request signal Rq. The direct memory access controller 104b determines how to access the secondary data blocks Sub1~SubN according to the control signal C, to move the data of the secondary data blocks Sub1~SubN to the switching access block Sab, or to process the micro processing. The data to be written by the device 101 is written into the secondary data blocks Sub1 to SubN through the mapping of the switching access block Sab.

The operation of the memory management system of the embodiment of the present invention will be described in detail below with reference to FIGS. 1A and 1B.

First, when the processor 101 has to access a data (code) D, it will transmit a The request signal Rq is supplied to the memory switching controller 104a. At this time, the memory switching controller 104a generates a control signal C according to the address information provided by the request signal Rq. Thereafter, the main memory 102 and the direct memory access controller 104b receive the control signal C.

Next, assuming that the address provided by the request signal Rq is located in the normal access block Nba in the address range of the main memory 102, the direct memory access controller 104b does not operate; and the main memory 102 is paired according to the control signal C. The code D of the address should be transmitted to the processor 101 via the memory switching controller 104a.

Furthermore, assuming that the address provided by the request signal Rq is located in the secondary data blocks Sub1~SubN outside the address range of the main memory 102, the memory switching controller 104a will determine the switching access block sab of the main memory 102. Is there a code D corresponding to the address, if any, the code D stored in the switching access block sab is transmitted to the central unit 101 through the memory switching controller 104a; if not, The memory switching controller 104a will drive the direct memory access controller 104b with the control signal C. Next, the direct memory access controller 104b stores the code D stored in the secondary data blocks Sub1 to SubN corresponding to the address to the switching access block Sab. Thereafter, the memory switching controller 104a transmits the code D stored in the switching access block Sab to the processor 101. In this manner, the memory management system 100 of the embodiment of the present invention can additionally increase the memory address range beyond the originally limited memory address range, without increasing the number of physical address pins required for memory addressing.

It should be noted that the foregoing only describes the operation mode of the memory management system of the embodiment of the present invention when reading data; however, those skilled in the art should be able to learn from the above description that the memory management system of the embodiment of the present invention is writing. How it works when entering data, so the way in which data is written is not repeated. In addition, the memory management of the present invention The device 104, and the memory switching controller 104a and the direct memory access controller 104b of the embodiments thereof may be implemented by one or a combination of software, firmware, or hardware.

As shown in FIG. 2, in another embodiment, the memory management system 100' of the present invention can also utilize a busbar Bus and a plurality of direct memory access controllers 104b, 104b'...a plurality of secondary memories. 103, 103' for data communication and reading and writing. Thereby the effect of memory expansion can be achieved.

3A and 3B are diagrams showing a memory management method according to an embodiment of the present invention, which includes the following steps: Step S302: Start.

Step S304: providing a normal access block and at least one switch access block.

Step S306: Provide at least one data block, and the data block corresponds to one of the switch access blocks.

Step S308: Receive a request signal, the request signal includes at least one address, at least one of the information to be written, or both.

Step S310: determining whether the address provided by the request signal is located in the address range of the normal access block, and if yes, skipping to step S312; if not, skipping to step S314.

Step S312: Read the data of the normal access block corresponding to the address, or write the data to be written into the normal access block.

Step S314: It is judged whether the address provided by the request signal is located in the address range of the secondary data block, and if yes, the process goes to step S316; if not, the process goes to step S322.

Step S316: It is judged whether the data corresponding to the address is already stored in the switching access block, and if so, the process goes to step S318, and if no, the process goes to step S320.

Step S318: Read the data of the switching access block.

Step S320: Move the data corresponding to the address of the secondary data block to the switching access block, and read the data in the switching access block, or write the data to be written through the mapping of the switching access block. Enter the data block.

Step S322: End.

The memory management system and the management method of the embodiment of the present invention are configured to map a normal access block and at least one switch access block in the main memory, and cooperate with the mapping of the switch access block to read and write times. The secondary data block of the level memory. In this way, the memory management system and the management method of the embodiment of the present invention can expand the number of addresses and the memory space without limitation by the user or the designer under a limited memory address range. That is, instead of requiring more main memory space, the existing memory of the main memory is used as an exchange block to exchange data with the secondary memory. Therefore, the number of pins required to reduce the memory address, the flexibility to expand the memory space, and the overall system cost are achieved.

100, 100’‧‧‧ Memory Management System

101‧‧‧ processor

102‧‧‧ main memory

103, 103’‧‧‧ secondary memory

104‧‧‧Memory management device

104a‧‧‧Memory Switching Controller

104b, 104b'‧‧‧ Direct Memory Access Controller

Fig. 1A is a view showing a memory management system according to an embodiment of the present invention.

Fig. 1B is a diagram showing the memory space configuration of the main memory and the secondary memory in Fig. 1A.

Fig. 2 is a view showing a memory management system according to another embodiment of the present invention.

3A and 3B are flowcharts showing a memory management method according to an embodiment of the present invention.

100‧‧‧Memory Management System

101‧‧‧ processor

102‧‧‧ main memory

103‧‧‧ secondary memory

104‧‧‧Memory management device

104a‧‧‧Memory Switching Controller

104b‧‧‧Direct Memory Access Controller

Claims (14)

A memory management system includes: a memory switching controller, generating a control signal according to at least one request signal; a main memory comprising a normal access block and at least one switching access block, and according to The control signal determines how to switch the access blocks, and how to read and write the normal access block or the switch access block; at least one level of memory, including at least one data corresponding to the switch access block a direct memory access controller that moves data of a secondary data block to the switched access block or maps a data to be written through the switched access block according to the control signal Writing to the data block; and a processor for issuing the request signal, wherein the request signal includes at least one address information and at least one of the information to be written; wherein the address of the request signal When the data switching block is located in the data block, the memory switching controller moves the data corresponding to the address stored in the data block to the switching access block through the direct memory access controller, and stores the data in the switching access block. The exchange of data output block access. The memory management system of claim 1, wherein when the address of the request signal is located in the normal access block, the memory switching controller reads and writes the normal access according to the address Block. The memory management system of claim 1, wherein when the address of the request signal is located in the data block, the memory switching controller transmits the desire through the direct memory access controller The data written is stored in the cut The access block is exchanged, and the data stored in the switch access block is written into the data block. The memory management system of claim 1, wherein the memory switching controller accesses the data of the normal access block when the request signal specifies access to the data of the normal access block. The memory management system of claim 1, wherein the main memory system determines to read or write the normal access block or the data block according to the address information. The memory management system of claim 1, wherein the secondary memory is one of a flash memory, a hard disk, a compact disk, or a combination thereof. The memory management system according to claim 1, wherein the memory management device is implemented by one or a combination of a soft body, a firmware, or a hardware. A memory management system includes: a memory switching controller, generating a control signal according to at least one request signal; a main memory comprising a normal access block and at least one switching access block, and according to The control signal determines how to switch the access blocks, and how to read and write the normal access block or the switch access block; at least one level of memory, including at least one data corresponding to the switch access block And a direct memory access controller, wherein the data of the secondary data block is moved to the switching access block according to the control signal, or a data to be written is transmitted through the switching access block. The mapping is written to the data block; The memory switching controller moves the data stored in the data block to the switching access area through the direct memory access controller when the request signal specifies access to the data of the data block. And the memory switching controller outputs the data stored in the switching access block. The memory management system of claim 8, wherein the memory switching controller performs the direct memory access control when the request signal specifies that the data to be written is written into the data block. The device stores the data in the switching access block, and then writes the data stored in the switching access block to the secondary data block. The memory management system of claim 8, wherein the memory switching controller transmits the data stored in the normal access block or the data block to a processor. The memory management system of claim 8, wherein the memory management device is implemented by one or a combination of a soft body, a firmware, or a hardware. The memory management system of claim 8, wherein the secondary memory is one of a flash memory, a hard disk, a compact disk, or a combination thereof. The memory management system of claim 8, wherein the memory switching controller accesses the data of the normal access block when the request signal specifies access to the data of the normal access block. The memory management system of claim 8, wherein the main memory system determines to read and write the normal access block or the data block according to the address information.