TWI407676B - Control circuit for detecting the output current of the power converter circuit - Google Patents
Control circuit for detecting the output current of the power converter circuit Download PDFInfo
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本發明相關於一種電源轉換器電路,尤指一種偵測電源轉換器電路之輸出電流之控制電路。The invention relates to a power converter circuit, in particular to a control circuit for detecting an output current of a power converter circuit.
請參考第1圖,第1圖為先前技術之電源轉換器電路10之示意圖。電源轉換器電路10為返馳式(flyback)電源轉換器電路,包含變壓器11、功率開關12、二極體13以及電容14。變壓器11包含一次側線圈NP、二次側線圈NS以及輔助側線圈NA,一次側線圈NP電性連接於輸入電壓VIN,輔助側線圈NA電性連接於電阻15以及電阻16所形成之分壓電路,以產生變壓器11之反射電壓VDET。功率開關12由驅動電壓VPWM所控制,用來調整電源轉換器電路10之輸出電壓以及輸出電流。Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art power converter circuit 10. The power converter circuit 10 is a flyback power converter circuit including a transformer 11, a power switch 12, a diode 13 and a capacitor 14. The transformer 11 includes a primary side coil NP, a secondary side coil NS, and an auxiliary side coil NA. The primary side coil NP is electrically connected to the input voltage VIN, and the auxiliary side coil NA is electrically connected to the resistor 15 and the resistor formed by the resistor 16. The road is used to generate the reflected voltage VDET of the transformer 11. The power switch 12 is controlled by a drive voltage VPWM for adjusting the output voltage of the power converter circuit 10 and the output current.
請參考第2圖,第2圖為第1圖之電源轉換器電路之操作波形圖。當驅動電壓VPWM將功率開關12導通時(邏輯高準位),即產生一次側電流IP,將能量儲存在變壓器11之中,電源轉換器電路在這個階段之波形如第2圖之週期T1所示。一次側電流IP的峰值IP1可表示為式(1):Please refer to FIG. 2, and FIG. 2 is an operational waveform diagram of the power converter circuit of FIG. When the driving voltage VPWM turns on the power switch 12 (logic high level), the primary side current IP is generated, and the energy is stored in the transformer 11, and the waveform of the power converter circuit at this stage is as shown in the period T1 of FIG. Show. The peak IP1 of the primary current IP can be expressed as equation (1):
其中LP是變壓器11的一次側線圈NP的電感值,TON是驅動電壓VPWM的導通時間。Where LP is the inductance value of the primary side coil NP of the transformer 11, and TON is the conduction time of the driving voltage VPWM.
當驅動電壓VPWM將功率開關12截止時(邏輯低準位),儲存在變壓器11中的能量釋放到變壓器11的二次側,並且經由二極體13釋放到電源轉換器電路之輸出端,產生二次側電流IS,電源轉換器電路在這個階段之波形如第2圖之週期T2所示。二次側電流IS的峰值ISSW可表示為式(2),變壓器11之放電時間TDS可表示為式(3),也代表二次側電流IS之放電時間:When the driving voltage VPWM turns off the power switch 12 (logic low level), the energy stored in the transformer 11 is released to the secondary side of the transformer 11, and is discharged to the output of the power converter circuit via the diode 13 to generate The secondary side current IS, the waveform of the power converter circuit at this stage is as shown in the period T2 of Fig. 2. The peak ISSW of the secondary side current IS can be expressed as Equation (2), and the discharge time TDS of the transformer 11 can be expressed as Equation (3), which also represents the discharge time of the secondary side current IS:
其中VO為電源轉換器電路之輸出電壓,VF為二極體13之順向偏壓,LS為變壓器11之二次側線圈NS之電感值。Where VO is the output voltage of the power converter circuit, VF is the forward bias of the diode 13, and LS is the inductance of the secondary side coil NS of the transformer 11.
同時,在變壓器11之輔助側線圈NA上產生一輔助電壓VAUX,輔助電壓VAUX與反射電壓VDET之關係可表示為式(4):At the same time, an auxiliary voltage VAUX is generated on the auxiliary side coil NA of the transformer 11, and the relationship between the auxiliary voltage VAUX and the reflected voltage VDET can be expressed as equation (4):
同時,儲存在變壓器11中的能量將對功率開關12之寄生電容CJ充電,寄生電容CJ之兩端將產生一電壓VDS,可表示為式(5)示:At the same time, the energy stored in the transformer 11 will charge the parasitic capacitance CJ of the power switch 12, and a voltage VDS will be generated at both ends of the parasitic capacitance CJ, which can be expressed as equation (5):
其中VIN是電源轉換器電路的輸入電壓,TNA、TNP以及TNS分別是變壓器11的輔助側線圈NA、一次側線圈NP以及二次側線圈NS的線圈匝數,R1和R2分別是電阻15以及電阻16的電阻值。Wherein VIN is the input voltage of the power converter circuit, and TNA, TNP, and TNS are the number of turns of the auxiliary side coil NA, the primary side coil NP, and the secondary side coil NS of the transformer 11, respectively, and R1 and R2 are the resistor 15 and the resistor, respectively. The resistance value of 16.
當儲存在變壓器11中的能量被完全釋放時,二次側電流IS下降為零,電源轉換器電路在這個階段之波形如第2圖之週期T3所示。電壓VDS在週期TQ結束時下降到谷底電壓,電壓VDS的下降斜率由一次側線圈NS之電感與功率開關13之寄電容所產生之諧振頻率所決定。當電壓VDS開始下降時,輔助電壓VAUX便開始減少。輔助電壓VAUX跟電壓VDS相關,可由式(6)表示:When the energy stored in the transformer 11 is completely released, the secondary side current IS drops to zero, and the waveform of the power converter circuit at this stage is as shown in the period T3 of Fig. 2. The voltage VDS drops to the valley voltage at the end of the period TQ, and the falling slope of the voltage VDS is determined by the resonance frequency of the inductance of the primary side coil NS and the capacitance of the power switch 13. When the voltage VDS begins to drop, the auxiliary voltage VAUX begins to decrease. The auxiliary voltage VAUX is related to the voltage VDS and can be expressed by the formula (6):
因此,從驅動電壓VPWM的下降緣到輔助電壓VAUX的下降轉角可得到式(2)中的放電時間TDS。Therefore, the discharge time TDS in the equation (2) can be obtained from the falling edge of the driving voltage VPWM to the falling corner of the auxiliary voltage VAUX.
一般電源轉換器電路必須在一次側和二次側之間提供電氣絕緣,若是利用二次側之回授電路來偵測輸出電壓,則需要使用光耦合器。另一方面,由於電源轉換器電路之控制器會利用變壓器之輔助側線圈來提供電源,而輔助側之電壓與二次側之電壓具有一定比例。因此,電源轉換器電路之控制器根據輔助側之電壓來調整電源轉換器電路之輸出電壓以及輸出電流可免除光耦合器以及二次側之回授電路。In general, the power converter circuit must provide electrical isolation between the primary side and the secondary side. If the secondary side feedback circuit is used to detect the output voltage, an optical coupler is required. On the other hand, since the controller of the power converter circuit uses the auxiliary side coil of the transformer to supply power, the voltage of the auxiliary side has a certain ratio with the voltage of the secondary side. Therefore, the controller of the power converter circuit adjusts the output voltage of the power converter circuit according to the voltage of the auxiliary side and the output current can eliminate the optical coupler and the feedback circuit of the secondary side.
因此,本發明之一目的在於提供一種偵測電源轉換器電路之輸出電流之控制電路。Accordingly, it is an object of the present invention to provide a control circuit for detecting an output current of a power converter circuit.
本發明係提供一種電源轉換器電路之控制電路,該電源轉換器電路包含一功率開關以及一變壓器,該控制電路包含一輸出電流控制單元、一前緣遮蔽單元、一比較器、一第一磁滯比較器、一第一電壓至電流轉換器以及一第一運算放大器。該輸出電流控制單元根據一回授控制電壓產生一輸出電流之參考電壓。該前緣遮蔽單元電性連接於該功率開關,以產生一輸出電流之偵測電壓。該比較器電性連接於該輸出電流控制單元以及該前緣遮蔽單元,用來將該輸出電流之偵測電壓與該輸出電流之參考電壓進行比較,以產生一截止訊號。該第一磁滯比較器用來接收該變壓器之一反射電壓,並將該反射電壓與一第一參考電壓進行比較,以產生一第一比較電壓。該第一電壓至電流轉換器電性連接於該輸出電流控制單元,用來根據該第一比較電壓將該輸出電流之參考電壓轉換為一第一電流訊號。該第一運算放大器電性連接於該電壓至電流轉換器,用來將該第一電流訊號之電壓值與一第二參考電壓進行比較,以產生該回授控制電壓。The invention provides a control circuit for a power converter circuit, the power converter circuit comprising a power switch and a transformer, the control circuit comprising an output current control unit, a leading edge shielding unit, a comparator, and a first magnetic A hysteresis comparator, a first voltage to current converter, and a first operational amplifier. The output current control unit generates a reference voltage of an output current according to a feedback control voltage. The leading edge shielding unit is electrically connected to the power switch to generate a detection voltage of an output current. The comparator is electrically connected to the output current control unit and the leading edge shielding unit for comparing the detected voltage of the output current with a reference voltage of the output current to generate a cutoff signal. The first hysteresis comparator is configured to receive a reflected voltage of the transformer and compare the reflected voltage with a first reference voltage to generate a first comparison voltage. The first voltage-to-current converter is electrically connected to the output current control unit for converting the reference voltage of the output current into a first current signal according to the first comparison voltage. The first operational amplifier is electrically connected to the voltage to current converter for comparing the voltage value of the first current signal with a second reference voltage to generate the feedback control voltage.
請參考第3圖,第3圖為本發明之電源轉換器電路20之示意圖。電源轉換器電路20為返馳式(flyback)電源轉換器電路,包含變壓器21、二極體23、電容24以及控制器30。變壓器21包含一次側線圈NP、二次側線圈NS以及輔助側線圈NA。一次側線圈NP電性連接於輸入電壓VIN,二次側線圈NS電性連接於二極體23以及電容24,用來產生輸出電壓,輔助側線圈NA可產生輔助電壓VAUX,並且電性連接於二極體31以及電容32,用來提供控制器30所需之電源。控制器30包含VDD、SWD、GND、ZCD、IST、ISN等六個針腳(pin)。針腳ZCD電性連接於電阻25以及電阻26所形成之分壓電路,用來接收變壓器21之反射電壓VDEF。針腳IST電性連接於電容33以及電阻34,用來控制輸出電流。針腳ISN電性連接於電阻35,用來偵測輸出電流。針腳SWD電性連接於一次側線圈NP,用來調整變壓器21之輸出電壓以及輸出電流。Please refer to FIG. 3, which is a schematic diagram of the power converter circuit 20 of the present invention. The power converter circuit 20 is a flyback power converter circuit including a transformer 21, a diode 23, a capacitor 24, and a controller 30. The transformer 21 includes a primary side coil NP, a secondary side coil NS, and an auxiliary side coil NA. The primary side coil NP is electrically connected to the input voltage VIN, the secondary side coil NS is electrically connected to the diode 23 and the capacitor 24 for generating an output voltage, and the auxiliary side coil NA can generate the auxiliary voltage VAUX and is electrically connected to The diode 31 and the capacitor 32 are used to provide the power required by the controller 30. The controller 30 includes six pins of VDD, SWD, GND, ZCD, IST, ISN, and the like. The pin ZCD is electrically connected to the voltage dividing circuit formed by the resistor 25 and the resistor 26 for receiving the reflected voltage VDEF of the transformer 21. The pin IST is electrically connected to the capacitor 33 and the resistor 34 for controlling the output current. The pin ISN is electrically connected to the resistor 35 for detecting the output current. The pin SWD is electrically connected to the primary side coil NP for adjusting the output voltage of the transformer 21 and the output current.
請參考第4圖,第4圖為本發明之控制器30之電路方塊圖。控制器30包含比較器41、第一運算放大器42、第二運算放大器43、前緣遮蔽(leading edge blanking,LEB)單元44、輸出電流控制單元45、第一磁滯比較器51、時序單元52、SR正反器61、緩衝器62、功率開關63、電壓至電流轉換器71、電容72、電阻73、磁滯比較器74、開關75、反或閘76以及電容77。前緣遮蔽單元44電性連接於功率開關63,用來防止偵測到不穩定的輸出電流,以產生輸出電流之偵測電壓,輸出電流控制單元45根據回授控制電壓VCMP產生輸出電流之參考電壓,比較器41電性連接於該輸出電流控制單元以及該前緣遮蔽單元,用來將輸出電流之偵測電壓與輸出電流之參考電壓進行比較,以產生截止訊號SOFF。另一方面,電壓至電流轉換器71接收ZCD電壓產生電流訊號I2,電阻73接收電流訊號I2產生針腳ZCD所接收之反射電壓,第一磁滯比較器51將反射電壓與第一參考電壓(0.4V)進行比較,以產生第一比較電壓V1,時序單元52根據該第一比較電壓V1提供時序訊號,以產生導通訊號SON。SR正反器61之設定(SET)端電性連接於時序單元52,SR正反器61之重設(RESET)端電性連接於比較器41,SR正反器61之輸出端根據截止訊號SOFF以及導通訊號SON產生驅動訊號,驅動訊號通過緩衝器62產生功率開關62之驅動電壓VPWM。Please refer to FIG. 4, which is a circuit block diagram of the controller 30 of the present invention. The controller 30 includes a comparator 41, a first operational amplifier 42, a second operational amplifier 43, a leading edge blanking (LEB) unit 44, an output current control unit 45, a first hysteresis comparator 51, and a timing unit 52. The SR flip-flop 61, the buffer 62, the power switch 63, the voltage to current converter 71, the capacitor 72, the resistor 73, the hysteresis comparator 74, the switch 75, the inverse OR gate 76, and the capacitor 77. The leading edge shielding unit 44 is electrically connected to the power switch 63 for preventing an unstable output current from being detected to generate a detection voltage of the output current, and the output current control unit 45 generates a reference of the output current according to the feedback control voltage VCMP. The comparator 41 is electrically connected to the output current control unit and the leading edge shielding unit for comparing the detection voltage of the output current with the reference voltage of the output current to generate the cutoff signal SOFF. On the other hand, the voltage to current converter 71 receives the ZCD voltage to generate the current signal I2, the resistor 73 receives the current signal I2 to generate the reflected voltage received by the pin ZCD, and the first hysteresis comparator 51 reflects the reflected voltage with the first reference voltage (0.4). V) performing a comparison to generate a first comparison voltage V1, and the timing unit 52 provides a timing signal according to the first comparison voltage V1 to generate a conduction number SON. The set (SET) terminal of the SR flip-flop 61 is electrically connected to the timing unit 52. The reset (RESET) terminal of the SR flip-flop 61 is electrically connected to the comparator 41, and the output of the SR flip-flop 61 is based on the cutoff signal. The SOFF and the conduction signal number SON generate a driving signal, and the driving signal generates the driving voltage VPWM of the power switch 62 through the buffer 62.
請參考第5圖,第5圖為第4圖之電壓波形圖。當功率開關63導通時,變壓器21之一次側線圈NP漸漸有電流流過,此時能量會儲存於變壓器21中。由於一次側線圈NP與二次側線圈NS極性是相反的,此時二極體23會被逆向偏壓,所以沒有能量轉移至負載,輸出之能量由電容24提供。當驅動電壓VPWM將功率開關63導通時(邏輯高準位),即產生一次側電流IP,將能量儲存在變壓器21之中,磁通密度將從剩磁增加到工作峰值,所以磁通電壓VFX由電壓1V開始上升。ZCD電壓可用來表示功率開關63截止時變壓器之反射電壓。當驅動電壓VPWM將功率開關63截止時(邏輯低準位),儲存在變壓器21中的能量釋放到變壓器21之二次側,並且經由二極體23釋放到電源轉換器電路之輸出端,產生二次側電流IS,此時ZCD電壓轉換為正值,磁通密度將從工作峰值下降到原本的剩磁,所以磁通電壓VFX開始下降,開關75被導通開始對反射電壓進行取樣。當磁通電壓VFX下降到電壓1.1V以下時,開關75截止,所以此時的反射電壓將被保持作為回授電壓VFB。當儲存在變壓器21中的能量被完全釋放時,二次側電流IS下降為零。隨著二次側電流IS的消失,ZCD電壓開始下降並在零電壓附近產生振盪,藉由時序單元52之控制,功率開關63將在ZCD電壓在經過一預定時間後再次被導通。因此,根據變壓器21之放電時間TDS以及二次側電流IS可計算出變壓器21之輸出電流,並進行回授控制。Please refer to Figure 5, and Figure 5 is the voltage waveform diagram of Figure 4. When the power switch 63 is turned on, the primary side coil NP of the transformer 21 gradually has a current flowing, and energy is stored in the transformer 21 at this time. Since the polarity of the primary side coil NP and the secondary side coil NS are opposite, the diode 23 is reversely biased at this time, so no energy is transferred to the load, and the output energy is supplied from the capacitor 24. When the driving voltage VPWM turns on the power switch 63 (logic high level), that is, the primary side current IP is generated, the energy is stored in the transformer 21, and the magnetic flux density is increased from the residual magnetization to the operating peak, so the magnetic flux voltage VFX It starts to rise from a voltage of 1V. The ZCD voltage can be used to indicate the reflected voltage of the transformer when the power switch 63 is turned off. When the driving voltage VPWM turns off the power switch 63 (logic low level), the energy stored in the transformer 21 is released to the secondary side of the transformer 21, and is discharged to the output terminal of the power converter circuit via the diode 23, resulting in The secondary side current IS, at which time the ZCD voltage is converted to a positive value, and the magnetic flux density is lowered from the operating peak to the original residual magnetization, so the magnetic flux voltage VFX starts to drop, and the switch 75 is turned on to start sampling the reflected voltage. When the magnetic flux voltage VFX falls below the voltage of 1.1 V, the switch 75 is turned off, so the reflected voltage at this time is held as the feedback voltage VFB. When the energy stored in the transformer 21 is completely released, the secondary side current IS drops to zero. As the secondary side current IS disappears, the ZCD voltage begins to drop and oscillates around the zero voltage, and by the control of the timing unit 52, the power switch 63 will be turned on again after the ZCD voltage has elapsed for a predetermined time. Therefore, the output current of the transformer 21 can be calculated based on the discharge time TDS of the transformer 21 and the secondary side current IS, and feedback control can be performed.
請再次參考第3圖至第5圖。在功率開關63導通的期間,一次側電流IP會線性增加。當功率開關63截止時,一次側電流IP會降為零,此時磁通電壓VFX開始下降,在變壓器21上之電壓極性將會反轉,並使得二極體23導通,將儲存在變壓器之能量傳送到電容24以及負載上。在功率開關63截止的期間,二次側電流IS會由最大值下降到零。因此,控制器30根據二次側電流IS下降到零時的反射電壓將被保持作為回授電壓VFB,而在二次側電流IS由最大值下降到零的期間,第一電壓至電流轉換器46將輸出電流之參考電壓I*轉換為電流訊號I1以產生IST電壓,再由第一運算放大器42以及第二運算放大器43產生回授控制電壓VCMP。Please refer to Figures 3 to 5 again. During the period in which the power switch 63 is turned on, the primary side current IP increases linearly. When the power switch 63 is turned off, the primary side current IP will drop to zero, at which time the magnetic flux voltage VFX begins to decrease, the polarity of the voltage on the transformer 21 will reverse, and the diode 23 will be turned on, which will be stored in the transformer. Energy is transferred to capacitor 24 and to the load. During the turn-off of the power switch 63, the secondary side current IS drops from a maximum value to zero. Therefore, the controller 30 will be held as the feedback voltage VFB according to the reflected voltage when the secondary side current IS drops to zero, and the first voltage to current converter during the period in which the secondary side current IS falls from the maximum value to zero. The reference voltage I* of the output current is converted into a current signal I1 to generate an IST voltage, and the feedback control voltage VCMP is generated by the first operational amplifier 42 and the second operational amplifier 43.
在本發明實施例中,輸出電流控制單元45根據回授控制電壓VCMP產生輸出電流之參考電壓I*如式(7)所示:In the embodiment of the present invention, the output current control unit 45 generates a reference voltage I* of the output current according to the feedback control voltage VCMP as shown in the formula (7):
I*=MAX {(VCMP -0.6)/4,0.25} (7)I*= MAX {( VCMP -0.6)/4,0.25} (7)
當反射電壓大於第一參考電壓(0.4V)時,變壓器21產生二次側電流IS,在此期間第一電壓至電流轉換器46根據第一比較電壓V1將輸出電流之參考電壓I*轉換為電流訊號I1,電流訊號I1輸出到針腳IST,電容33用來平均電流訊號I1,電阻34接收電流訊號I1產生IST電壓。第一運算放大器42將IST電壓與第二參考電壓(3V)進行比較,以產生回授控制電壓VCMP。由於IST電壓與輸出電流之參考電壓I*成正比,所以可藉由調整電阻34之電阻值以控制變壓器21之輸出電流。另一方面,電壓至電流轉換器71接收ZCD電壓產生電流訊號I2,電容72接收電流訊號I產生磁通電壓VFX,磁通電壓VFX用來表示變壓器21之磁通密度(flux density)的變化。磁滯比較器74將磁通電壓VFX與第三/第四參考電壓1V/1.1V進行比較以產生第二比較電壓V2,反或閘76接收第V2比較電壓以及驅動訊號以產生開關訊號SSW,開關75根據開關訊號SSW對反射電壓進行取樣,以作為回授電壓VFB,並利用電容77保持回授電壓VFB。第二運算放大器43將回授電壓VFB與第二參考電壓(3V)進行比較,以產生回授控制電壓VCMP。因此,本發明之控制器30根據變壓器21之輸出電流以及輸出電壓進行回授控制。When the reflected voltage is greater than the first reference voltage (0.4V), the transformer 21 generates a secondary side current IS during which the first voltage to current converter 46 converts the reference voltage I* of the output current into a first comparison voltage V1. The current signal I1, the current signal I1 is output to the pin IST, the capacitor 33 is used to average the current signal I1, and the resistor 34 receives the current signal I1 to generate the IST voltage. The first operational amplifier 42 compares the IST voltage with a second reference voltage (3V) to generate a feedback control voltage VCMP. Since the IST voltage is proportional to the reference voltage I* of the output current, the output current of the transformer 21 can be controlled by adjusting the resistance value of the resistor 34. On the other hand, the voltage-to-current converter 71 receives the ZCD voltage to generate a current signal I2, the capacitor 72 receives the current signal I to generate a magnetic flux voltage VFX, and the magnetic flux voltage VFX is used to indicate a change in the flux density of the transformer 21. The hysteresis comparator 74 compares the magnetic flux voltage VFX with the third/fourth reference voltage 1V/1.1V to generate a second comparison voltage V2, and the inverse gate 76 receives the V2 comparison voltage and the driving signal to generate the switching signal SSW. The switch 75 samples the reflected voltage according to the switching signal SSW as the feedback voltage VFB, and holds the feedback voltage VFB by the capacitor 77. The second operational amplifier 43 compares the feedback voltage VFB with a second reference voltage (3V) to generate a feedback control voltage VCMP. Therefore, the controller 30 of the present invention performs feedback control based on the output current of the transformer 21 and the output voltage.
綜上所述,本發明之電源轉換器電路之控制電路可偵測輸出電流進行回授控制。在本發明之實施例中,該電源轉換器電路包含一功率開關以及一變壓器,該控制電路包含一輸出電流控制單元、一前緣遮蔽單元、一比較器、一第一磁滯比較器、一第一電壓至電流轉換器以及一第一運算放大器。該輸出電流控制單元根據一回授控制電壓產生一輸出電流之參考電壓,該比較器將該前緣遮蔽單元產生之輸出電流之偵測電壓與該輸出電流之參考電壓進行比較,以產生該功率開關之截止訊號。該第一磁滯比較器根據該變壓器之反射電壓產生一第一比較電壓,該第一電壓至電流轉換器根據該第一比較電壓將該輸出電流之參考電壓轉換為一電流訊號,該第一運算放大器根據該電流訊號之電壓值產生該回授控制電壓。此外,本發明之電源轉換器電路之控制器根據變壓器之輔助側線圈之電壓來偵測電源轉換器電路之輸出電壓,可免除光耦合器以及二次側之回授電路。In summary, the control circuit of the power converter circuit of the present invention can detect the output current for feedback control. In an embodiment of the invention, the power converter circuit includes a power switch and a transformer, the control circuit includes an output current control unit, a leading edge shielding unit, a comparator, a first hysteresis comparator, and a A first voltage to current converter and a first operational amplifier. The output current control unit generates a reference voltage of the output current according to a feedback control voltage, and the comparator compares the detection voltage of the output current generated by the leading edge shielding unit with a reference voltage of the output current to generate the power. The cutoff signal of the switch. The first hysteresis comparator generates a first comparison voltage according to the reflected voltage of the transformer, and the first voltage to current converter converts the reference voltage of the output current into a current signal according to the first comparison voltage, the first The operational amplifier generates the feedback control voltage based on the voltage value of the current signal. In addition, the controller of the power converter circuit of the present invention detects the output voltage of the power converter circuit according to the voltage of the auxiliary side coil of the transformer, thereby eliminating the optical coupler and the feedback circuit of the secondary side.
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
10、20...電源轉換器電路10, 20. . . Power converter circuit
11、21...變壓器11, 21. . . transformer
12、63...功率開關12, 63. . . Power switch
13、23、31...二極體13, 23, 31. . . Dipole
14、24、32、33、72、77...電容14, 24, 32, 33, 72, 77. . . capacitance
15、16、25、26、34、35、73...電阻15, 16, 25, 26, 34, 35, 73. . . resistance
30...控制器30. . . Controller
41...比較器41. . . Comparators
42...第一運算放大器42. . . First operational amplifier
43...第二運算放大器43. . . Second operational amplifier
44...前緣遮蔽單元44. . . Leading edge shielding unit
45...輸出電流控制單元45. . . Output current control unit
46...第一電壓至電流轉換器46. . . First voltage to current converter
51...第一磁滯比較器51. . . First hysteresis comparator
52...時序單元52. . . Timing unit
61...SR正反器61. . . SR flip-flop
62...緩衝器62. . . buffer
63...功率開關63. . . Power switch
71...第二電壓至電流轉換器71. . . Second voltage to current converter
74...第二磁滯比較器74. . . Second hysteresis comparator
75...開關75. . . switch
76...反或閘76. . . Reverse or gate
ZCD、IST、ISN、VDD、SWD、GND...針腳ZCD, IST, ISN, VDD, SWD, GND. . . stitch
NP...一次側線圈NP. . . Primary side coil
NS...二次側線圈NS. . . Secondary side coil
NA...輔助側線圈NA. . . Auxiliary side coil
VIN...輸入電壓VIN. . . Input voltage
VAUX...輔助電壓VAUX. . . Auxiliary voltage
VDET...反射電壓VDET. . . Reflected voltage
VPWM...驅動電壓VPWM. . . Driving voltage
CJ...寄生電容CJ. . . Parasitic capacitance
VDS...功率開關訊號VDS. . . Power switch signal
IP...一次側電流IP. . . Primary current
IS...二次側電流IS. . . Secondary current
I1、I2...電流訊號I1, I2. . . Current signal
SON...導通訊號SON. . . Communication number
SOFF...截止訊號SOFF. . . Cutoff signal
SSW...開關訊號SSW. . . Switch signal
V1、V2...比較電壓V1, V2. . . Comparison voltage
VPWM...驅動電壓VPWM. . . Driving voltage
VFB...回授電壓VFB. . . Feedback voltage
VFX...磁通電壓VFX. . . Flux voltage
VCMP...回授控制電壓VCMP. . . Feedback control voltage
第1圖為先前技術之電源轉換器電路之示意圖。Figure 1 is a schematic diagram of a prior art power converter circuit.
第2圖為第1圖之電源轉換器電路之操作波形圖。Fig. 2 is an operational waveform diagram of the power converter circuit of Fig. 1.
第3圖為本發明之電源轉換器電路之示意圖。Figure 3 is a schematic diagram of the power converter circuit of the present invention.
第4圖為本發明之控制器之方塊示意圖。Figure 4 is a block diagram of the controller of the present invention.
第5圖為第4圖之電壓波形圖。Figure 5 is a voltage waveform diagram of Figure 4.
30...控制器30. . . Controller
41...比較器41. . . Comparators
42...第一運算放大器42. . . First operational amplifier
43...第二運算放大器43. . . Second operational amplifier
44...前緣遮蔽單元44. . . Leading edge shielding unit
45...輸出電流控制單元45. . . Output current control unit
46...第一電壓至電流轉換器46. . . First voltage to current converter
51...第一磁滯比較器51. . . First hysteresis comparator
52...時序單元52. . . Timing unit
61...SR正反器61. . . SR flip-flop
62...緩衝器62. . . buffer
63...功率開關63. . . Power switch
71...第二電壓至電流轉換器71. . . Second voltage to current converter
72、77...電容72, 77. . . capacitance
73...電阻73. . . resistance
74...第二磁滯比較器74. . . Second hysteresis comparator
75...開關75. . . switch
76...反或閘76. . . Reverse or gate
I1、I2...電流訊號I1, I2. . . Current signal
SON...導通訊號SON. . . Communication number
SOFF...截止訊號SOFF. . . Cutoff signal
SSW...開關訊號SSW. . . Switch signal
V1、V2...比較電壓V1, V2. . . Comparison voltage
VPWM...驅動電壓VPWM. . . Driving voltage
VFB...回授電壓VFB. . . Feedback voltage
VFX...磁通電壓VFX. . . Flux voltage
VCMP...回授控制電壓VCMP. . . Feedback control voltage
ZCD、ISN、IST、SWD...針腳ZCD, ISN, IST, SWD. . . stitch
Claims (9)
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US20040257833A1 (en) * | 2003-06-18 | 2004-12-23 | Ta-Yung Yang | Flyback power converter having a constant voltage and a constant current output under primary-side PWM control |
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US20040257833A1 (en) * | 2003-06-18 | 2004-12-23 | Ta-Yung Yang | Flyback power converter having a constant voltage and a constant current output under primary-side PWM control |
CN100525045C (en) * | 2003-07-28 | 2009-08-05 | 崇贸科技股份有限公司 | Primary-side controlled flyback power converter |
US20060214603A1 (en) * | 2005-03-22 | 2006-09-28 | In-Hwan Oh | Single-stage digital power converter for driving LEDs |
TWM303563U (en) * | 2006-05-24 | 2006-12-21 | System General Corp | Primary-side controlled switching regulator |
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