TWI404368B - Digital communication device and decoding method - Google Patents

Abstract

The invention discloses a digital communication apparatus and decoding method, wherein the digital communication apparatus comprises a burst wrong detecting device, an internal decoder and an outer decoder, wherein the burst wrong detecting device determines burst noise location corresponding to the data stream based on error check equation, and generates burst wrong indicating symbol accordingly; the inner decoder decodes the data stream to generate inner decoding stream; the inner decoder comprises a mark eraser for performing mark erasing program to internal decoding stream based on the burst wrong indicating symbol, so as to generate an erase indicating symbol corresponding to the internal decoding stream; the outer decoder decodes the internal decoding stream corresponding to the erase indicating symbol to generate receiver output. The digital communication apparatus and the decoding method can enforce error correction capability of communication system.

Description

Digital communication device and decoding method

The present invention relates to a digital communication device, and more particularly to an enhanced error-erasure decoding method and a digital communication device applicable to a burst error detection mechanism.

In conventional receivers, various types of noise, distortion, and interference are often factors that cause signal quality to deteriorate, resulting in output errors. Error-Correcting Coding (ECC) is a general-purpose technology that helps the receiver to resist the effects of the above factors, which reduces the probability of errors and enhances the reliability of the output data.

Concatenated coding is an error correction coding technique that implements multi-level coding, such as inner coding and outer coding. For example, a convolutional code or a Trellis-Coded Modulation (TCM) code can be used as an internal code to help overcome the random error of the spread. The Reed-Solomon (RS) code or the BCH (Bose-Chaudhuri Hocquenghem) code can be used as an external code to help overcome clumping errors.

Figure 1 is a block diagram of a conventional receiver for decoding a serial code. The receiver 100 shown in FIG. 1 includes a demodulation transformer 110, an internal decoder 120, a deinterleaver 130, and an external decoder 140. The demodulation transformer 110 receives the radio frequency signal #RF to generate a data stream, and the demodulation transformer 110 may include components such as a synthesizer for frequency down conversion, for frequency doubling. An anti-aliasing filter, a synchronizing device for timing or frequency recovery, and an equalizer for compensating for fading or impairing channel effects. After some or all of the above operations are performed, the demodulation transformer 110 can generate the data stream #S.

Depending on which internal code is used, internal decoder 120 may be implemented by a cyclotron decoder or a TCM decoder, which may perform an internal decoding process on data stream #S to generate internal decoded stream #I. After internal decoder 120, deinterleaver 130 deinterleaves internal decoded stream #I to produce deinterleaved stream #D. Deinterleaver 130 plays an important role in distributing certain types of burst noise to share the burden of error correction.

The outer decoder 140 performs an external decoding process on the deinterleaved stream #D to output a receiver output #OUT, and the outer decoder 140 can be implemented by an RS decoder or a BCH decoder. For example, when the RS code is used as an external code, the external decoder 140 can be implemented by an RS decoder. For the (n, k, 2t) RS code, the external decoder 140 can correct up to t errors. In other words, the external decoder 140 has the error correction capability to correct t errors. However, in some communication systems, especially terrestrial broadcasting systems, complex multipath channels can cause various fading or interference, and thus the equalizer of demodulator 110 cannot fully compensate for fading or interference. In such a situation, burst noise can cause the internal decoder 120 to malfunction and propagate to the external decoder 140, and the deinterleaver 130 cannot effectively disperse it. Therefore, in order to enhance the error correction capability, an erasure marking mechanism needs to be proposed.

If the demodulator 110 can detect burst noise and the internal decoder 120 has a mechanism to mark the unreliable symbol as an erasure indicator, the outer decoder 140 can be upgraded to the RS error erasure decoder. For the (n, k, 2t) RS code, if 2x + y ≦ 2t, the RS error erasure decoder can correct x errors and y erasures. In other words, if it is informed of some of the locations marked as erased errors, it is possible for the external decoder 140 to correct the actual number of errors over the codeword of t.

The erase tagging process must be performed based on reliable burst error detection. However, the current burst error detection mechanism is still in the initial stage of the technology. Therefore, there is a need to provide an enhanced burst error detector.

In order to enhance the error correction capability of the communication system, the following technical solution is provided: an embodiment of the present invention provides a digital communication device for decoding a data stream to generate a receiver output, where the digital communication device includes a burst error detector. Internal decoder and external decoder. The burst error detector is configured to determine a burst noise position corresponding to the data stream according to the error check equation, and generate a burst error indicator accordingly; the internal decoder is configured to decode the data stream to generate an internal decoded stream. The internal decoder includes an erase marker for performing an erase flag procedure on the internal decoded stream based on the burst error indicator to generate an erase indicator corresponding to the internal decoded stream; and an external decoder coupled to An internal decoder for decoding an internal decoded stream corresponding to the erasure indicator to produce a receiver output.

The embodiment of the present invention further provides a decoding method for decoding a data stream to generate a receiver output, where the decoding method includes: determining a cluster noise position corresponding to the data stream according to an error checking equation, and generating correspondingly Generating an error indicator; decoding the data stream to generate an internal decoded stream; performing an erase flag procedure on the internal decoded stream based on the burst error indicator to generate an erase indicator corresponding to the internal decoded stream; and decoding An internal decoded stream corresponding to the erase indicator to produce a receiver output.

The digital communication device and the decoding method described above can enhance the error correction capability of the communication system.

Certain terms are used throughout the description and subsequent claims to refer to particular components. Those of ordinary skill in the art should understand that hardware manufacturers may refer to the same components by different nouns. The scope of this specification and the subsequent patent application do not use the difference in name as the means of distinguishing components, but the difference in function of components as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.

Figure 2a is a schematic illustration of a digital communication device 200a in accordance with an embodiment of the present invention. In the present embodiment, the burst error detector 300 is provided to detect burst errors based on the data stream #S output by the demodulator 110. The internal decoder 220 employs an erasure marker 225 to output an erasure indicator #E based on the burst error indicator #B output from the burst error detector 300. More specifically, when the internal decoder 220 decodes the data stream #S into a recovered bit, the erasure marker 225 maps the data stream #S at the symbol level to the corresponding bit. yuan. When the internal decoded stream #I is converted to the deinterleaved stream #D, the deinterleaver 230 also deinterleaves the erasure indicator #E to produce a deinterleaved erasure indicator #E' that is output to the outer decoder 240a. . Subsequently, the external decoder 240a performs an adaptive error correction procedure based on the deinterleaved stream #D and the deinterleaved erase indicator #E' to output the receiver output #OUT.

It should be noted that the deinterleaver 230 is an optional component that depends on the architecture of the transmitter that generates the RF signal #RF. 2b is a schematic diagram of another digital communication device 200b according to an embodiment of the present invention, the digital communication device 200b not including a deinterleaver 230. As shown in FIG. 2b, internal decoder 220 provides internal decoded stream #I and erasure indicator #E to external decoder 240b. Subsequently, the external decoder 240b performs an adaptive error correction procedure based on the deinterleaved stream #D and the erasure indicator #E to output the receiver output #OUT. The specific operation of each functional block is detailed below.

Figure 3a is a schematic diagram of the burst error detector 300 shown in Figures 2a and 2b. The data stream #S is a continuous bit stream that is continuously input to the burst error detector 300 at a specific bit rate. The burst error detector 300 analyzes the data stream #S to generate a burst error indicator #B, which is used to indicate whether a burst error has occurred in the corresponding time period. In the burst error detector 300, the determining unit 310 slices or quantizes the stream #S, and extracts a useful bit from the stream #S to generate at least one encoded stream. #U. The useful bit is for the parity bit or error check code embedded in the data stream #S together with the data bit, the format of which depends on the different coding schemes described below. . For example, the data stream #S may be a symbol stream, so the decision unit 310 may function as a slicer or a quantizer, and the encoded stream #U may be output as a coded bit stream. Optionally, if the data stream #S is a parallel encoding bit, the encoded stream #U may be a serial encoded bit stream.

The joint logic unit 320 is coupled to the output of the decision unit 310 for performing a joint logical operation on the encoded stream #U based on an error-check equation to generate a logical value #L for the logical value #L Represents the correctness of a particular multiple encoded stream #U in a particular time period. In the present embodiment, the error checking equation is derived by a specific algorithm associated with the encoding scheme implemented by the digital communication devices 200a and 200b. The error checking equation may vary depending on the coding scheme implemented, which may be predetermined or estimated by the known architecture of the corresponding transmitter. Since the data stream #S is continuously input, the logical value #L is continuously outputted in each time slot, and each logical value #L corresponds to a specific plurality of encoded streams #U.

After joint logic unit 320, statistics unit 330 compiles a plurality of logical values #L over a period of time to produce cumulative value #A. The time period is for a set of consecutive time slots that are offset over time. The logical value #L is continuously generated for each time slot. At the same time, the cumulative value #A can be considered as a summary of a plurality of logical values #L in the continuous time slot.

The comparator 340 is coupled to the statistics unit 330 for comparing the accumulated value #A with the threshold value #th to detect whether a burst error occurs. If the cumulative value #A exceeds the threshold value #th, the comparator 340 asserts the burst error indicator #B to a specific value (eg, a logic "1") to indicate that a burst error has occurred recently. In contrast, if the cumulative value #A does not exceed the threshold value #th, the burst error indicator #B is set to another specific value (for example, a logical "0"). The threshold value #th may be a fixed value, a single-level value, or a multi-level value. It should be noted that other ways can also be employed to provide a suitable threshold value #th.

Figure 3b is a schematic diagram of a statistical unit 330b according to the embodiment shown in Figure 3a. According to the standard of the convolutional code, the encoded stream #U in the data stream #S is segmented by the encoding period (period), and in the statistical unit 330b, a delay line 334 is designated to represent the The encoding period (period), the delay line 334 includes a plurality of columns, each row corresponding to one time slot in the period, and each row storing one logical value #L. Adder 332 continuously receives logical value #L from joint logic unit 320 to accumulate each row of delay line 334. Thereafter, the selector 336 detects the segment boundary (puncture boundary) of the encoded stream #U, and outputs the value of the accumulated line corresponding to the segment boundary (puncture boundary) as the cumulative value #A. The mechanism for detecting the boundary of the segment can be known from different prior art, and a detailed description thereof will not be repeated.

In the statistics unit 330, the accumulation of each row in the delay line 334 may be repeated for one or more time periods (the encoding period of the encoded stream #S), and the selector 336 may select one of the delay lines 334 having the smallest initial cumulative result as the Said the boundary. Subsequently, the selector 336 outputs the cumulative result as the cumulative value #A based on the boundary.

Figure 3c is a schematic diagram of a statistical unit 330c according to the embodiment shown in Figure 3a. Similarly, the encoded stream #U in the data stream #S is segmented by the encoding period (period), and in the statistical unit 330b, the storage component 344 (eg, a buffer) stores the initial accumulation of the cumulative value #A. result. Adder 332 receives logical value #L from joint logic unit 320 and receives an initial cumulative result from storage component 344 to continuously sum up each input logical value #L with said initial cumulative result and correspondingly The aggregated results are stored in storage component 344 as the initial cumulative result. The counter 346 counts a time period (the encoding period of the encoded stream #S), thereby enabling the output of the initial accumulated result described in the component 344 to be stored as the cumulative value #A. Counter 346 then resets the initial cumulative result stored in storage component 344.

Figure 4a is a schematic diagram of a conventional internal encoder 400. The internal encoder 400 is a TCM block conforming to a transmitter of an 8-level Vestigial Sideband (8-VSB) standard, and the internal encoder 400 includes a pre-coder 410 and a fence. A trellis encoder 420 and a symbol mapper 436. The precoder 410 receives two information bits X ₁ and X ₂ stream and generate two bit streams Y ₁ and Y _2. The precoder 410 has a mutually exclusive (XOR) gate 402 and a delay component 404 with a 12-cycle delay period that receives the bit stream X ₂ to produce a bit stream Y ₂ . Fence encoder 420 receives two bit streams Y ₁ and Y ₂ and produces three output bit streams U ₀ , U _{1 ,} and U ₂ . The fence encoder 420 includes a mutex or gate 424 and delay components 422 and 426 having a delay period of 12 symbols, which receive the bit stream Y ₁ and produce output bit streams U ₀ and U ₁ . The symbol mapper 436 receives three bit streams output U _0, U ₁ and U _2, and generates a data symbol stream using a predetermined mapping rule #S 8-VSB standard definition.

To trellis encoder 420, the output bit stream U ₀ and U ₁ Y ₁ bitstreams line by using XOR gate 424 and to determine the two components 422 and 426 delay. Architecture by trellis encoder 420, the bit stream includes an output U ₀ and U ₁ and may be determined with three equations Y ₁ bit stream of uncorrelated, which expressed as follows:

U ₀ [n]=Q ₀ [n-1]; (1)

Q ₀ [n]=U ₁ [n]⊕Q ₁ [n-1]; (2)

Q ₁ [n-1]=U ₀ [n-1], (3)

Where n represents an index and each increment corresponds to a 12-symbol delay period, and Q ₀ and Q ₁ represent the outputs of delay components 422 and 426, respectively.

Therefore, the equation U0[n+1]=U1[n]⊕U0[n-1] can be derived based on equations (1), (2), and (3). Accordingly, the error checking equation can be determined as follows:

P[n]=U ₀ [n+1]⊕U ₁ [n]⊕U ₀ [n-1] (4)

A device for calculating an error metric can be designed using the error checking equation (4) inherent to the transmitter conforming to the 8-VSB standard. When P[n] has a logical value of "0", it indicates that the corresponding encoded stream #U is correct. Conversely, when P[n] has a logical value of "1", it means that the corresponding encoded stream #U is incorrect.

Figure 4b is a schematic diagram of the decision unit 310a and the joint logic unit 320a of the internal encoder 400 shown in Figure 4a. In joint logic unit 320a, delay component 405 and mutex or gate 407 form joint logic unit 320 as shown in FIG. 3a. Decision unit 310a and joint logic unit 320a are employed in the embodiment of FIG. 3a to form burst error detector 300.

For example, the data stream #S, which is usually derived from the equalizer of the demodulation transformer 110, is input to the decision unit 310a. The decision unit 310a generates three encoded streams U ₀ ', U ₁ ', and U ₂ ' using the symbol mapping rules symmetric with the symbol mapping rules of the symbol mapper 436 of the inner encoder 400 in FIG. 4a. If the encoded streams U ₀ ', U ₁ ', and U ₂ ' are correct, it can be assumed that the corresponding symbols in the data stream #S are also correct. Thus, the delay component 405 of the joint logic unit 320a can be used to simplify equation (4) where the encoded stream U ₁ ' is delayed by 12 symbols and the encoded stream U ₀ ' is delayed by 24 symbols. Subsequently, the mutex or gate 407 receives the delayed encoded streams U ₀ ' and U ₁ ' to perform an error checking operation, and the logical value #L of the mutex or gate 407 output represents an error check result. Obviously, in the present embodiment, the logical value "0" represents the setting to be correct, and the logical value "1" represents the setting to be incorrect.

Figure 5a is a schematic diagram of a conventional internal encoder 500. The internal encoder 500 is a TCM block of a transmitter conforming to the ITU-T Recommendation J.83 Annex B (hereinafter referred to as J83B) standard, which utilizes a 64 Quadrature Amplitude Modulation (QAM) mechanism. In Figure 5a, internal encoder 500 continuously receives a 7-bit data stream #Din. A parser 540 identifies a set of four 7-bit symbols (ie, 28 bits) and specifies the "I" component of the in-phase and the "Q" component of the quadrature. . As shown in Figure 5a, for the I component, the parser 540 outputs two uncoded bitstreams 502 (I ₂ , I ₅ , I ₈ , I ₁₁ , I ₁₃ ), 504 (I) of the upper (upper). ₁ , I ₄ , I ₇ , I ₁₀ , I ₁₂ ) and a lower encoded bit stream 512a (I ₀ , I ₃ , I ₆ , I ₉ ). For the Q component, the parser 540 outputs the upper two uncoded bitstreams 506 (Q ₂ , Q ₅ , Q ₈ , Q ₁₁ , Q ₁₃ ), 508 (Q ₁ , Q ₄ , Q ₇ , Q). ₁₀ , Q ₁₂ ) and the lower encoded bit stream 512b (Q ₀ , Q ₃ , Q ₆ , Q ₉ ). Uncoded bitstreams 502, 504, 506, and 508 are sent to QAM mapper 530, and encoded bitstreams 512a and 512b are sent to differential precoder 510. Differential precoder 510 performs rotationally invariant trellis coding for bit pairs Q ₀ and I ₀ , Q ₃ and I ₃ , Q ₆ and I ₆ and Q ₉ and I ₉ for I and Q. The differential precoder 510 then transmits the differentially encoded lower stream streams #X and #Y (4 bits) to the punctured binary convolutional encoders 520a and 520b, respectively.

In the present embodiment, the 4/5 rate (4/5-rate) puncture binary encoders 520a and 520b are based on a binary cyclotron encoder having a 1/2 rate of the puncture code. In general, in digital communication systems, error correction codes are used to increase redundancy to improve noise immunity. At a rate of 1/2, the puncture binary encoders 520a and 520b receive 4 bits (#X and #Y) and produce 8 coded bits. In addition, if all of the coded bits are transmitted as payloads, the load can be greatly reduced due to excessive redundancy, and the puncture function applied by the puncture binary encoders 520a and 520b can be used to compensate for the reduction in load. In other words, the transmission of some coded bits was previously agreed by the transmitter and the receiver was bypassed. The puncture binary encoders 520a and 520b conform to the J83B standard, which transmits 5 bits for every 8 coded bits, resulting in a total puncture rate of 4/5. That is, 5 bits are generated based on 4 input bits.

Finally, QAM mapper 530 receives encoded bit stream 502, and not from the puncture binary convolutional encoder 520a and 520b of an encoding stream _{#U (U 1, U 2,} U 3, U 4, U 5 ) with #V(V ₁ , V ₂ , V ₃ , V ₄ , V ₅ ), and generate 64QAM data stream #S.

Figure 5b is a schematic diagram of a puncture binary encoder 520a of the internal encoder 500 shown in Figure 5a. Since the architecture of the puncture binary encoders 520b and 520a is similar, the puncture binary encoder 520b will not be described in detail. It should be noted that the error checking equation derived in the following discussion may also be applied to the puncture binary encoder 520b. The puncture binary cyclotron encoder 520a includes four delay components 555, two mutually exclusive or gates 524 and 526, and a commutator 528. The four delay components 555 store four previous input bits X[0], X[-1], X[-2], and X[-3], thereby having 16 states in the puncture binary encoder 520a. As shown in Figure 5b, the codes OUT _U and OUT _L can be expressed as follows:

OUT _U =X[1]⊕X[-1]⊕X[-3]; (5)

OUT _L =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-3] (6)

Equations (5) and (6) are determined by generating codes G ₁ and G ₂ , where G1 = [010101] and G2 = [011111]. It should be noted that different cyclotron encoders have different generation codes. The puncture function of the diverter 528 is implemented using a puncture matrix [P1; P2] = [0001; 1111], where "0" indicates that the bit is not transmitted, and "1" indicates that the bit is transmitted sequentially.

For each trellis group, the puncture binary encoder 520a can be from four input bits denoted as X[1], X[2], X[3], and X[4]. Generate 8 coded bits. Based on the puncture matrix, the diverter 528 selects 5 bits from the 8 coded bits as the encoded stream #U. Here, a set of encoded streams (eg, U[5], U[4], U[3], U[2], U[1]) can be represented as a corresponding set of input bits (eg, X[ 4], X[3], X[2], X[1]) and the equations of the previously input bits (X[0], X[-1], X[12], X[-3]). In general, for the nth group, the 5 output bits can be expressed as follows:

U[n+1]=X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]

U[n+2]=X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]

U[n+3]=X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]

U[n+4]=X[n+4]⊕X[n+2]⊕X[n]

U[n+5]=X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]

Where n is the index. Except for the nth group, the previous two groups (the (n-2) and (n-1) groups) and the following two groups (the (n+1) and (n+2) groups) are also listed as follows. Reference:

Group (n-2)

U[n-9]=X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]⊕X[n-11]

U[n-8]=X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]

U[n-7]=X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]

U[n-6]=X[n-4]⊕X[n-6]⊕X[n-8]

U[n-5]=X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]

Group (n-1)

U[n-4]=X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]

U[n-3]=X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]

U[n-2]=X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]

U[n-1]=X[n]⊕X[n-2]⊕X[n-4]

U[n]=X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]

Group (n+1)

U[n+6]=X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]

U[n+7]=X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]

U[n+8]=X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]

U[n+9]=X[n+8]⊕X[n+6]⊕X[n+4]

U[n+10]=X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]

Group (n+2)

U[n+11]=X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]

U[n+12]=X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]

U[n+13]=X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]

U[n+14]=X[n+12]⊕X[n+10]⊕X[n+8]

U[n+15]=X[n+12]⊕X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]

Based on the above five consecutive output bits, the following equations that are not related to input bit X can be derived:

U[n-6]⊕U[n-5]⊕U[n-4]⊕U[n-3]⊕U[n-2]⊕U[n-1]⊕U[n+1]⊕U [n+4]⊕U[n+5]⊕U[n+8]⊕U[n+9]⊕U[n+11]⊕U[n+12]⊕U[n+13]⊕U[ n+14]⊕U[n+15]≡0

It can also be further derived as a polynomial form, expressed as:

P(x)=x*(1+x+x ² +x ³ +x ⁴ +x ⁶ +x ⁷ +x ¹⁰ +x ¹¹ +x ¹⁴ +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ +x ²⁰ +x ²¹ ) (7)

The joint logic unit 320 shown in Fig. 3a can be designed using the error checking equation (7) inherent to the transmitter conforming to the J83B standard.

On the other hand, in the receiver of the J83B cable system, since there is no training sequence, the puncture boundary or the puncture position is determined from the incoming bit stream. As necessary. As described above, a set of 5 output code bits is generated by 4 input bits indicating that the incoming bit stream of the TCM decoder in the receiver has 5 possible puncture locations. Therefore, the error checking equation (7) can only be applied to the correct puncture position (puncture boundary) among the five possible puncture positions.

Figure 5c is a schematic diagram of the joint logic unit 320b in response to the puncture binary encoder 520a shown in Figure 5b, which conforms to the J83B standard and uses error checking equation (7) to verify the correctness of the data stream #S. In the digital communication device 200, the radio frequency signal #RF is received and continuously demodulated by the demodulator 110 into a data stream #S. This embodiment utilizes a 64-QAM demodulation mechanism. The joint logic unit 320b includes a delay line 560 and a mutex or gate 562, wherein the delay line 560 includes a plurality of delay components D connected in series, and the mutex or gate 562 has a plurality of inputs, the plurality of inputs being respectively coupled to the delay The line circuit delays the output of one of the plurality of delay components D of the line 560. The decision unit 310 shown in Fig. 3a receives the in-phase and quadrature components of the data stream #S to retrieve the encoded streams #U and #V described in Fig. 5a again. In the present embodiment, only the encoded stream #U is described.

The encoded stream #U is passed to the federated logic unit 320b. In joint logic unit 320b, delay line 560 stores a limited sequence of encoded streams #U using a plurality of delay components D. In the present embodiment, delay line 560 has 21 delay components D to store the sequence from U[n-6] to U[n+14] in encoded stream #U. According to the error check equation (7), the output of the first (right), 2, 3, 4, 5, 6, 8, 11, 12, 15, 16, 18, 19, 20, 21 (left) delay units D And the current bit is connected to the input of the mutex or gate 562. The mutex or gate 562 continuously performs a mutual exclusion or operation on the above input to output a plurality of consecutive logical values #L. Each of the logical values #L represents a result of the error check equation (7).

Alternatively, the burst error detector 300 can be used in a wide variety of burst detection applications. For example, Figure 5d shows a puncture binary encoder 520d, which is defined by the Digital Video Broadcasting (DVB) standard ETSI EN 300 744 V1.4.1 (2001-01) and has 1/2, 2/3 and 3/4 different punctured code rates. The puncture binary cyclotron encoder 520d includes six delay components 555, two mutually exclusive gates 524 and 526, and a diverter 528. The six delay components 555 store six previous input bits X[0], X[-1]. , X[-2], X[-3], X[-4], and X[-5]. As shown in Figure 5d, the codes OUT _U and OUT _{L of the} input diverter 528 can be expressed as follows:

OUT _U =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-5]; (8)

OUT _L =X[1]⊕X[-1]⊕X[-2]⊕X[-4]⊕X[-5] (9)

The three puncture rates recommended by the European DVB standard include 1/2, 2/3 and 3/4. Based on equations (8), (9) and the specific puncture code rate, at least one equation containing only the output bit and its parity polynomial can be derived. For the sake of brevity, the relevant derivation will not be repeated here.

When the puncture rate is set to 1/2, the puncture sequence [1-up 1-down] can be expressed as:

U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]=X[2]+X[1]+X[0]+X[-1]+X[-4]

Similarly, U[4]~U[16] can also be obtained from the puncture sequence. Therefore, based on U[1]~U[16], the following equation can be derived:

U[1]⊕U[2]⊕U[4]⊕U[5]⊕U[7]⊕U[8]⊕U[11]⊕U[13]⊕U[15]⊕U[16]= 0

The error checking equation can also be derived from this, which can be expressed as:

P(x)=1+x+x ³ +x ⁵ +x ⁸ +x ⁹ +x ¹¹ +x ¹² +x ¹⁴ +x ¹⁵ (10)

When the puncture rate is set to 2/3, the puncture sequence [1-up 1-down 2-down] can be expressed as:

U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]

U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]

Similarly, U[5]~U[20] can also be obtained from the puncture sequence. Therefore, based on the U[1] to U[16] whose puncture rate is set to 2/3, the following error checking equation can be obtained:

U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[8]⊕U[10]⊕U[12]⊕U[13]⊕U[15]⊕U[18]⊕ U[19]⊕U[20]=0

Its polynomial form is expressed as: P(x)=1+x+x ² +x ⁵ +x ⁷ +x ⁸ +x ¹⁰ +x ¹² +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ (11)

Further, when the puncture rate is set to 3/4, the puncture sequence [1-up 1-down 2-down 3-up] can be expressed as:

U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]

U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]

U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]

U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]

U[5]=X[4]+X[3]+X[2]+X[1]+X[-2]

Similarly, U[6]~U[34] can also be obtained from the puncture sequence. Therefore, based on the puncture code rate set to 2/3 U[1] to U[16], the equation can be expressed as follows:

U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[7]⊕U[10]⊕U[14]⊕U[15]⊕U[16]⊕U[24]⊕ U[28]⊕U[29]⊕U[31]⊕U[32]⊕U[33]⊕U[34]=0

Its polynomial form is:

P(x)=1+x+x ² +x ³ +x ⁵ +x ⁶ +x ¹⁰ +x ¹⁸ +x ¹⁹ +x ²⁰ +x ²⁴ +x ²⁷ +x ³⁰ +x ³¹ +x ³² +x ³³ (12)

It will be apparent that the architecture suggested by Figure 5c can be modified to implement different error checking equations such as (10), (11) and (12).

Fig. 6 is a diagram showing an example of an erasure marking program implemented by the erasure marker 225 of Figs. 2a and 2b. The state above the top of Figure 6 is the status of the burst error indicator #B. In cycle C _1, burst error indicator #B high (high), shows that there are burst errors. In cycle C _2, burst error indicator #B is low (low), showed no burst error.

For example, the internal decoder 220 of the 2a and 2b diagrams may employ a Viterbi Algorithm to decode the data stream #S, and the sixth picture is from the backtrack performed by the internal decoder 220 (trace back) The residual path found in the program is used to decode the internal decoded stream #I. The erase mark program is executed during the operation of the Viterbi decoding program. Since the burst error cycle C _1, which requires a higher standard of decision erased. The shadowed node represents the state of the marker. Conversely, since the C ₂ period not burst errors, which can be determined using standard lower the erasure. The lower part of Fig. 6 is the signal state of the erasure indicator #E, which is determined according to the mark on the residual path in the Trellis diagram. If a state on the residual path is flagged, the erase marker 225 issues an erase indicator #E of logic "1". Conversely, if a state on the residual path is not marked, the erase marker 225 issues an erase indicator #E of logic "0".

The embodiment shown in Fig. 6 can enable the outer decoder 240a of Fig. 2a to decode the deinterleaved stream #D according to the unreliable position, wherein the unreliable position has been deinterleaved with the erase indicator #E 'Determining the erasure position corresponding to the deinterleaved stream #D, and the deinterleaving erasure indicator #E' is the deinterleaver 230 of Fig. 2a generated by deinterleaving the erasure indicator #E. Similarly, the embodiment shown in FIG. 6 can be used in the external decoder 240b of FIG. 2b to determine an unreliable position of the erased position corresponding to the internal decoded stream #I based on the erased indicator #E. Decode the internal decoded stream #I.

Figure 7a is a schematic diagram of an external decoder 240a for correcting the deinterleaved stream #D to produce a receiver output #OUT, in accordance with an embodiment of the present invention. The deinterleaved stream #D is an (n, k, 2t) RS coded signal. The external decoder 240a includes a first error correcting unit 710, a second error correcting unit 720, and a multiplexer 730. As described above, the digital communication device 200a in FIG. 2a is a serial-type code receiver, and the operation of the erasure marker 225 is determined by the burst error detector 300 coupled to the demodulation transformer 110. The burst location is incorrect, and the deinterleaved erase indicator #E' generated by the deinterleaver 130 during execution of the decoding represents the unreliable position in the deinterlaced stream #D.

In the outer decoder 240a, the first error correcting unit 710 decodes the deinterleaved stream #D to generate a first initial output #O1. Since the operation of the first error correction unit 710 is independent of the deinterlace erase indicator #E', the incorrect erase flag program that may be performed by the erase marker 225 does not affect the performance of the first error correction unit 710. . The first error correction unit 710 can correct up to t errors in each codeword. On the other hand, the second error correcting unit 720 decodes the deinterleaved stream #D in accordance with the deinterlace erasure indicator #E' to generate a second initial output #O2. More specifically, the second error correcting unit 720 decodes the deinterleaved stream #D by taking the unreliable position determined by the deinterlace erasure indicator #E' as the erasing position. If 2x+y≦2t, x errors and y erases within one codeword can be successfully corrected. That is, the second error correcting unit 720 can correct up to 2t erasures by additionally providing the information provided by the interleave erasure indicator #E'. In other words, if all the error positions in a code word are accurately determined by the erasure marker 225 as the erasure position, and no incorrect erasure position is marked, the second error correction unit 720 can correct up to 2t errors. It is equivalent to twice the correction capability of the first error correcting unit 710.

In this embodiment, the first error correction unit 710 and the second error correction unit 720 can operate in parallel. For each codeword in the deinterlaced stream #D, both the first error correction unit 710 and the second error correction unit 720 may attempt to decode the codeword to generate a first initial output #O1 and a second initial output, respectively. #O2. The above solution can ensure the correction capability of the external decoder 240a when the number of errors of one codeword in the deinterleaved stream #D does not exceed t, and enhance the external when the number of errors of one codeword in the deinterleaved stream #D exceeds t Correction capability of decoder 240a.

In addition, when decoding the codeword of the deinterleaved stream #D, the first error correcting unit 710 further generates the first flag #f1 to indicate whether each codeword in the deinterleaved stream #D has been corrected by the first error. Unit 710 is successfully corrected. Similarly, when the codeword of the deinterleaved stream #D is decoded according to the deinterlace erasure indicator #E', the second error correcting unit 720 also generates the second flag #f2 to indicate whether to deinterleave the stream #D Each codeword has been successfully corrected by the second error correction unit 720. According to the first flag #f1 and the second flag #f2, the multiplexer 730 selects one of the first initial output #O1 and the second initial output #O2 as the receiver output #OUT.

Since the first error correcting unit 710 is a relatively reliable decoder and its performance is not affected by an incorrect erasure marking program that may be performed by the erasure marker 225, as long as the first flag #f1 indicates a solution The interleaved stream #D has been successfully corrected by the first error correcting unit 710 to generate the first initial output #O1, and the multiplexer 730 can select the first initial output #O1 as the receiver output #OUT.

In the present embodiment, the deinterleaver 230 is not limited to being a necessary component. In general, the deinterleaver 230 is placed before the input of the first error correcting unit 710 and the second error correcting unit 720 to input the first error correcting unit 710 and the second error correcting unit to deinterleave the stream #D. The internal decoded stream #I from the internal decoder 220 is deinterleaved before 720, and the erasure erase indicator #E is deinterleaved, thereby generating the deinterleaved erase indicator #E' and supplying it to the second error correcting unit 720. Alternatively, as shown in FIG. 2b, external decoder 240b is directly coupled to internal decoder 220 to process internal decoded stream #I instead of deinterleaved stream #D.

Figure 7b is a schematic diagram similar to external decoder 240b of the embodiment shown in Figure 7a. The external decoder 240b is employed in the embodiment shown in FIG. 2b, which operates based on the erasure indicator #E and the internal decoded stream #I, and the deinterleaver 230 is omitted in FIG. 2b. The first error correction unit 710 decodes the internal decoded stream #I to generate a first initial output #O1, and the second error correction unit 720 decodes the internal decoded stream #I according to the erasure indicator #E to generate a second initial output # O2. More specifically, the second error correcting unit 720 decodes the deinterleaved stream #D by taking the unreliable position determined by the erasure indicator #E as the erasing position. When decoding the codeword of the internal decoded stream #I, the first error correcting unit 710 further generates the first flag #f1 to indicate whether each codeword in the internal decoded stream #I has been used by the first error correcting unit 710. Successfully corrected. Similarly, when the codeword of the internal decoded stream #I is decoded according to the erasure indicator #E, the second error correcting unit 720 also generates the second flag #f2 to indicate whether each code in the stream #I is internally decoded. The words have all been successfully corrected by the second error correcting unit 720. According to the first flag #f1 and the second flag #f2, the multiplexer 730 selects one of the first initial output #O1 and the second initial output #O2 as the receiver output #OUT. Based on the above description of the external decoder 240a, those skilled in the art will be aware of how the external decoder 240b performs the operations and functions. Therefore, detailed descriptions of its operations and functions are not described herein.

The above are only the preferred embodiments of the present invention, and equivalent changes and modifications made by those skilled in the art to the spirit of the present invention are intended to be included in the scope of the appended claims.

100. . . receiver

110. . . Demodulation transformer

120. . . Internal decoder

130. . . Deinterleaver

140. . . External decoder

200a, 200b. . . Digital communication device

220. . . Internal decoder

225. . . Erase marker

230. . . Deinterleaver

240a, 240b. . . External decoder

300. . . Crash error detector

310, 310a. . . Decision unit

320, 320a, 320b. . . Joint logical unit

330, 330b, 330c. . . Statistical unit

340. . . Comparators

332. . . Adder

334, 560. . . Delay line

336. . . Selector

344. . . Storage component

346. . . counter

400, 500. . . Internal encoder

410. . . Precoder

420. . . Fence encoder

436. . . Symbol mapper

402, 424, 407, 524, 526, 562. . . Mutual exclusion or gate

404, 422, 426, 405, 555. . . Delay component

510. . . Differential precoder

512a, 512b. . . Coded bit stream

502, 504, 506, 508. . . Uncoded bit stream

520a, 520b, 520d. . . Puncture binary rotary encoder

530. . . QAM mapper

540. . . Parser

528. . . Steering gear

710. . . First error correction unit

720. . . Second error correction unit

730. . . Multiplexer

Figure 1 is a schematic diagram of a conventional receiver.

Figure 2a is a schematic illustration of an example of a digital communication device in accordance with an embodiment of the present invention.

Figure 2b is a schematic illustration of another example of a digital communication device in accordance with an embodiment of the present invention.

Figure 3a is a schematic diagram of an example of a burst error detector in accordance with an embodiment of the present invention.

Figure 3b is a schematic diagram of an example of a statistical unit of the embodiment shown in Figure 3a.

Figure 3c is a diagram showing another example of a statistical unit according to the embodiment shown in Figure 3a.

Figure 4a is a schematic diagram of a conventional internal encoder.

Figure 4b is a schematic diagram of an example of a decision unit and a joint logic unit responsive to the internal encoder shown in Figure 4a.

Figure 5a is a schematic diagram of another conventional internal encoder.

Figure 5b is a schematic diagram showing an example of a puncture binary cyclotron encoder of the internal encoder shown in Figure 5a.

Figure 5c is a schematic diagram of an example of a joint logic unit responsive to the puncture binary encoder shown in Figure 5b.

Figure 5d is a schematic diagram of another example of a puncture binary rotary encoder of the internal encoder shown in Figure 5a.

Figure 6 is a schematic diagram of an example of an erase marking procedure.

Figure 7a is a schematic diagram of an example of an external decoder.

Figure 7b is a schematic diagram of another example of an external decoder.

110. . . Demodulation transformer

200a. . . Digital communication device

220. . . Internal decoder

225. . . Erase marker

230. . . Deinterleaver

240a. . . External decoder

300. . . Crash error detector

Claims (27)

A digital communication device for decoding a data stream to generate a receiver output, the digital communication device comprising: a burst error detector for determining a cluster corresponding to the data stream according to an error checking equation Generating a noise location and correspondingly generating a burst error indicator; an internal decoder for decoding the data stream to generate an internal decoded stream, the internal decoder including an erase marker, the erase The marker is configured to perform an erasure flagging process on the internal decoded stream based on the burst error indicator to generate an erasure indicator corresponding to the internal decoded stream; and an external decoder coupled to the internal And a decoder for decoding the internal decoded stream corresponding to the erasure indicator to generate the receiver output. The digital communication device of claim 1, wherein the erasure marker performs the erasure flag process by using one of a plurality of decision criteria according to the burst error indicator to generate the erasure indicator. . The digital communication device of claim 1, wherein: when the burst error detector sets the burst error indicator to a first value, the erase marker adopts a first decision criterion. Performing the erasure flagging process on the internal decoded stream; and when the burst error detector sets the burst error indicator to a second value, the erasure marker adopts a second decision criterion The erase tagging process is performed on the internal decoded stream. The digital communication device of claim 1, further comprising a deinterleaver coupled to the internal decoder and the external decoder, the deinterleaver deinterleaving the internal decoded stream and the erasure indication a symbol to respectively generate a deinterleaved stream and a deinterlace erasure indicator corresponding to one of the deinterleaved streams, wherein the outer decoder decodes the deinterleaved stream corresponding to the deinterleaved erase indicator to The receiver output is generated. The digital communication device of claim 1, wherein the external decoder comprises: a first error correction unit for correcting the internal decoded stream to generate a first initial output; and a second error correction unit For correcting the internal decoded stream corresponding to the erasure indicator to generate a second initial output; and a multiplexer coupled to the first error correction unit and the second error correction unit for One of the first initial output and the second initial output is selected to be the receiver output. The digital communication device of claim 5, wherein the second error correction unit decodes the unreliable position indicated by the erasure indicator to correspond to an erase position of the internal decoded stream. Internal decoding stream. The digital communication device of claim 6, wherein the first error correction unit further generates a first flag, wherein the first flag is used to indicate whether the internal decoded stream is successfully succeeded by the first error correction unit. Correcting; the second error correcting unit further generates a second flag, the second flag is used to indicate whether the internal decoded stream is successfully corrected by the second error correcting unit; and the multiplexer according to the first flag and the The second flag selects one of the first initial output and the second initial output as the receiver output. The digital communication device according to claim 1, wherein the data stream conforms to an eighth-order residual sideband standard, and the data stream includes parallel coding bits U ₀ , U ₁ and U ₂ , wherein U ₀ represents U Parity of ₁ is expressed as: U ₀ [n+1]=U ₁ [n]⊕U ₀ [n-1], where n represents a time slot, operator ⊕ represents a mutex or operation; and the error The check equation is expressed as: P[n]=U ₀ [n+1]⊕U ₁ [n]⊕U ₀ [n-1], where P[n] represents a logical value, when the logical value is 0, Indicates that the encoded stream of one of the data streams is correct. When the logical value is 1, it indicates that the encoded stream of the data stream is erroneous. The digital communication device according to claim 1, wherein the data stream conforms to the ITU-T Recommendation J.83 Annex B standard, and the error checking equation is a parity check polynomial P[x], which is expressed as :P(x)=x*(1+x+x ² +x ³ +x ⁴ +x ⁶ +x ⁷ +x ¹⁰ +x ¹¹ +x ¹⁴ +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ +x ²⁰ +x ²¹ ). The digital communication device according to claim 1, wherein the data stream conforms to a digital video broadcasting standard, and the error checking equation is a parity check polynomial P[x], when the data stream rate is At 1/2, it is expressed as: P(x)=1+x+x ³ +x ⁵ +x ⁸ +x ⁹ +x ¹¹ +x ¹² +x ¹⁴ +x ¹⁵ , when the code rate of the data stream When it is 2/3, it is expressed as: P(x)=1+x+x ² +x ⁵ +x ⁷ +x ⁸ +x ¹⁰ +x ¹² +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ , when When the code stream has a code rate of 3/4, it is expressed as: P(x)=1+x+x ² +x ³ +x ⁵ +x ⁶ +x ¹⁰ +x ¹⁸ +x ¹⁹ +x ²⁰ + x ²⁴ +x ²⁷ +x ³⁰ +x ³¹ +x ³² +x ³³ . The digital communication device of claim 1, wherein the burst error detector comprises: a determining unit that receives the data stream to generate at least one encoded stream; and a joint logic unit coupled to the a determining unit, configured to perform a joint logic operation on the encoded stream based on the error checking equation to generate a logical value for indicating the correctness of the encoded stream; a statistical unit coupled to the joint logical unit, And a plurality of consecutive logic values for compiling a time period to generate a cumulative value; and a comparator coupled to the statistical unit for comparing the accumulated value with a threshold value to generate a representation corresponding to the One of the time periods of the burst error is the burst error indicator. The digital communication device of claim 11, wherein the joint logic unit comprises: a delay line having a plurality of delay components connected in series for storing a limited sequence of the data stream; and a mutual exclusion Or gates having a plurality of inputs, optionally receiving the outputs of the plurality of delay components to implement the error checking equation, wherein the outputs of the selected plurality of delay components perform a mutual exclusion or operation to generate the logic values. The digital communication device of claim 11, wherein the statistical unit comprises: a delay line comprising a plurality of rows for storing a plurality of initial cumulative results of the accumulated value, wherein each row corresponds to a time in the time period. a slot, an adder that recursively and successively accumulates logical values of each row sequentially input; and a selector for detecting a boundary of the data stream and outputting the plurality of initial cumulative results based on the boundary One of them as the cumulative value. The digital communication device of claim 13, wherein when the accumulation operation of each row is repeated for at least one time period, the selector selects one of the plurality of rows having a minimum initial cumulative result as the boundary, and The boundary outputs the initial cumulative result as the cumulative value. The digital communication device of claim 11, wherein the statistical unit comprises: an adder for summing each successive input logical value from the joint logical unit with an initial cumulative result as the An initial accumulation result; a storage component for storing the cumulative result from the adder; and a counter for enabling an output of the initial cumulative result in the storage component to use the initial cumulative result as each time period The cumulative value. The digital communication device of claim 11, further comprising a demodulator for receiving a radio frequency signal and demodulating the radio frequency signal to generate the data stream. A decoding method for decoding a data stream to generate a receiver output, the decoding method comprising: determining a cluster noise position corresponding to the data stream according to an error checking equation, and generating a burst correspondingly An error indicator; decoding the data stream to generate an internal decoded stream; performing an erase flag procedure on the internal decoded stream based on the burst error indicator to generate an erase corresponding to the one of the internal decoded streams An indicator; and decoding the internal decoded stream corresponding to the erasure indicator to generate the receiver output. The decoding method of claim 17, wherein the erasure marking program comprises: performing the erasure marking procedure by one of a plurality of decision criteria according to the burst error indicator to generate the erasure indication symbol. The decoding method of claim 17, further comprising: when the burst error indicator is set to a first value, using a first decision criterion to perform the erasure flag on the internal decoded stream a program; and when the burst error indicator is set to a second value, a second decision criterion is employed to perform the erase flag procedure for the internal decoded stream. The decoding method of claim 17, further comprising: deinterleaving the internal decoded stream and the erasure indicator to respectively generate a deinterleaved stream and deinterleaving corresponding to one of the deinterleaved streams An erase indicator; and decoding the deinterleaved stream corresponding to the deinterleaved erase indicator to generate the receiver output. The decoding method of claim 17, wherein the decoding the deinterleaved stream comprises: performing a first error correction on the internal decoded stream to generate a first initial output; the internal decoded string The stream performs a second error correction to generate a second initial output; and selects one of the first initial output and the second initial output as the receiver output. The decoding method of claim 21, wherein the second error correction comprises: decoding the unreliable position indicated by the erasure indicator to correspond to an erasure position of the internal decoded stream, Internal decoding stream. The decoding method according to claim 17, wherein the data stream conforms to an eighth-order residual sideband standard, and the data stream includes parallel encoding bits U ₀ , U ₁ and U ₂ , wherein U ₀ represents U ₁ Parity, expressed as: U ₀ [n+1]=U ₁ [n]⊕U ₀ [n-1], where n represents a time slot, operator ⊕ represents a mutex or operation; and the error check The equation is expressed as: P[n]=U ₀ [n+1]⊕U ₁ [n]⊕U ₀ [n-1], where P[n] represents a logical value, and when the logical value is 0, the expression One of the data stream encoding streams is correct. When the logical value is 1, it indicates that the encoded stream of the data stream is erroneous. The decoding method according to claim 17, wherein the data stream conforms to the ITU-T Recommendation J.83 Annex B standard, and the error checking equation is a parity check polynomial P[x], which is expressed as: P(x)=x*(1+x+x ² +x ³ +x ⁴ +x ⁶ +x ⁷ +x ¹⁰ +x ¹¹ +x ¹⁴ +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ +x ²⁰ +x ²¹ ). The decoding method according to claim 17, wherein the data stream conforms to a digital video broadcasting standard, and the error checking equation is a parity check polynomial P[x], and the code rate of the data stream is 1 /2, which is expressed as: P(x)=1+x+x ³ +x ⁵ +x ⁸ +x ⁹ +x ¹¹ +x ¹² +x ¹⁴ +x ¹⁵ , when the rate of the data stream is At 2/3, it is expressed as: P(x)=1+x+x ² +x ⁵ +x ⁷ +x ⁸ +x ¹⁰ +x ¹² +x ¹⁶ +x ¹⁷ +x ¹⁸ +x ¹⁹ , when When the code rate of the data stream is 3/4, it is expressed as: P(x)=1+x+x ² +x ³ +x ⁵ +x ⁶ +x ¹⁰ +x ¹⁸ +x ¹⁹ +x ²⁰ +x ²⁴ +x ²⁷ +x ³⁰ +x ³¹ +x ³² +x ³³ . The decoding method of claim 17, wherein the step of determining the burst noise location comprises: receiving the data stream to generate at least one encoded stream; performing the encoded stream based on the error checking equation Combining logic operations to generate a logical value representing one of the correctness of the encoded stream; compiling a plurality of consecutive logical values over a period of time to generate a cumulative value; and comparing the accumulated value to a threshold to generate Used to indicate the burst error indicator corresponding to whether a burst error occurred during the time period. The decoding method of claim 17, further comprising: receiving a radio frequency signal and demodulating the radio frequency signal to generate the data stream.