TWI404368B - Digital communication device and decoding method - Google Patents
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Description
本發明係有關於一種數位通訊裝置,且特別有關於一種可應用於叢發(burst)錯誤偵測機制之增強型錯誤擦除(error-erasure)解碼方法及數位通訊裝置。The present invention relates to a digital communication device, and more particularly to an enhanced error-erasure decoding method and a digital communication device applicable to a burst error detection mechanism.
於傳統接收器中,各種類型之雜訊、失真及干擾通常皆係為致使信號品質惡化、從而導致輸出錯誤之因素。糾錯編碼(Error-Correcting Coding,ECC)係為有助於接收器抵制上述因素影響之通用技術,其可減小錯誤之機率並增強輸出資料之可靠性。In conventional receivers, various types of noise, distortion, and interference are often factors that cause signal quality to deteriorate, resulting in output errors. Error-Correcting Coding (ECC) is a general-purpose technology that helps the receiver to resist the effects of the above factors, which reduces the probability of errors and enhances the reliability of the output data.
串接式編碼(concatenated coding)係為一種實施多級編碼之糾錯編碼技術,所述多級編碼可例如內部編碼(inner coding)及外部編碼(outer coding)。舉例而言,迴旋碼(convolutional code)或格碼調變(Trellis-Coded Modulation,TCM)碼可作為內部碼,其有助於克服散佈之隨機誤差。而里德所羅門(Reed-Solomon,RS)碼或BCH(Bose-Chaudhuri Hocquenghem)碼可作為外部碼,其有助於克服叢發錯誤。Concatenated coding is an error correction coding technique that implements multi-level coding, such as inner coding and outer coding. For example, a convolutional code or a Trellis-Coded Modulation (TCM) code can be used as an internal code to help overcome the random error of the spread. The Reed-Solomon (RS) code or the BCH (Bose-Chaudhuri Hocquenghem) code can be used as an external code to help overcome clumping errors.
第1圖係用於解碼串接式碼之傳統接收器之方塊圖。第1圖所示之接收器100包含解調變器110、內部解碼器120、解交錯器130及外部解碼器140。解調變器110接收射頻信號#RF以產生資料串流,所述解調變器110可包含如下組件,例如:用於下變頻(frequency down conversion)之合成器(synthesizer)、用於疊頻消除(anti-aliasing)之濾波器、用於時序或頻率恢復之同步裝置以及用於補償衰落或減損性(impairment)通道效應之等化器。上述操作之一部分或全部被執行後,解調變器110可產生資料串流#S。Figure 1 is a block diagram of a conventional receiver for decoding a serial code. The receiver 100 shown in FIG. 1 includes a demodulation transformer 110, an internal decoder 120, a deinterleaver 130, and an external decoder 140. The demodulation transformer 110 receives the radio frequency signal #RF to generate a data stream, and the demodulation transformer 110 may include components such as a synthesizer for frequency down conversion, for frequency doubling. An anti-aliasing filter, a synchronizing device for timing or frequency recovery, and an equalizer for compensating for fading or impairing channel effects. After some or all of the above operations are performed, the demodulation transformer 110 can generate the data stream #S.
取決於使用何種內部碼,內部解碼器120可藉由迴旋解碼器或TCM解碼器來實作,其可對資料串流#S執行內部解碼程序以產生內部解碼串流#I。於內部解碼器120之後,解交錯器130解交錯內部解碼串流#I以產生解交錯串流#D。解交錯器130於分散某些類型之叢發雜訊以分擔錯誤校正負擔中扮演著重要角色。Depending on which internal code is used, internal decoder 120 may be implemented by a cyclotron decoder or a TCM decoder, which may perform an internal decoding process on data stream #S to generate internal decoded stream #I. After internal decoder 120, deinterleaver 130 deinterleaves internal decoded stream #I to produce deinterleaved stream #D. Deinterleaver 130 plays an important role in distributing certain types of burst noise to share the burden of error correction.
外部解碼器140對解交錯串流#D執行外部解碼程序,以輸出接收器輸出#OUT,且所述外部解碼器140可藉由RS解碼器或BCH解碼器來實作。舉例而言,當RS碼被用作外部碼時,外部解碼器140可藉由RS解碼器來實作。對於(n,k,2t)RS碼而言,外部解碼器140最多可校正t個錯誤。換言之,外部解碼器140具有校正t個錯誤之錯誤校正能力。然而,於某些通訊系統中,尤其是地面廣播(terrestrial broadcasting)系統,複雜的多路徑通道會導致各種衰落或干擾,因此解調變器110之等化器無法完全補償衰落或干擾。於此種狀況下,叢發雜訊可導致內部解碼器120發生錯誤並傳播至外部解碼器140,而解交錯器130亦無法將其有效分散。因此,為增強錯誤校正能力,需要提出一種擦除標記(erasure marking)機制。The outer decoder 140 performs an external decoding process on the deinterleaved stream #D to output a receiver output #OUT, and the outer decoder 140 can be implemented by an RS decoder or a BCH decoder. For example, when the RS code is used as an external code, the external decoder 140 can be implemented by an RS decoder. For the (n, k, 2t) RS code, the external decoder 140 can correct up to t errors. In other words, the external decoder 140 has the error correction capability to correct t errors. However, in some communication systems, especially terrestrial broadcasting systems, complex multipath channels can cause various fading or interference, and thus the equalizer of demodulator 110 cannot fully compensate for fading or interference. In such a situation, burst noise can cause the internal decoder 120 to malfunction and propagate to the external decoder 140, and the deinterleaver 130 cannot effectively disperse it. Therefore, in order to enhance the error correction capability, an erasure marking mechanism needs to be proposed.
若解調變器110可偵測叢發雜訊,且內部解碼器120具有將不可靠符號標記為擦除指示符之機制,則外部解碼器140可被升級至RS錯誤擦除解碼器。對於(n,k,2t)RS碼而言,若2x+y≦2t,則RS錯誤擦除解碼器可校正x個錯誤及y個擦除。換言之,若被告知一些被標記為擦除之錯誤的位置,外部解碼器140有可能可校正實際錯誤數超過t之碼字(codeword)。If the demodulator 110 can detect burst noise and the internal decoder 120 has a mechanism to mark the unreliable symbol as an erasure indicator, the outer decoder 140 can be upgraded to the RS error erasure decoder. For the (n, k, 2t) RS code, if 2x + y ≦ 2t, the RS error erasure decoder can correct x errors and y erasures. In other words, if it is informed of some of the locations marked as erased errors, it is possible for the external decoder 140 to correct the actual number of errors over the codeword of t.
擦除標記程序必須基於可靠的叢發錯誤偵測來執行,然而,當前之叢發錯誤偵測機制仍係為處於初始階段之技術。因此,需要提供一種增強型叢發錯誤偵測器。The erase tagging process must be performed based on reliable burst error detection. However, the current burst error detection mechanism is still in the initial stage of the technology. Therefore, there is a need to provide an enhanced burst error detector.
為增強通訊系統之錯誤校正能力,特提供以下技術方案:本發明實施例提供一種數位通訊裝置,用於解碼資料串流以產生接收器輸出,所述數位通訊裝置包含叢發錯誤偵測器、內部解碼器以及外部解碼器。叢發錯誤偵測器用於依據錯誤檢查方程式決定與資料串流對應之叢發雜訊位置,並相應地產生叢發錯誤指示符;內部解碼器用於解碼資料串流以產生內部解碼串流,所述內部解碼器包含擦除標記器,用於基於叢發錯誤指示符對內部解碼串流執行擦除標記程序,以產生對應於內部解碼串流之擦除指示符;以及外部解碼器耦接至內部解碼器,用於解碼與擦除指示符對應之內部解碼串流以產生接收器輸出。In order to enhance the error correction capability of the communication system, the following technical solution is provided: an embodiment of the present invention provides a digital communication device for decoding a data stream to generate a receiver output, where the digital communication device includes a burst error detector. Internal decoder and external decoder. The burst error detector is configured to determine a burst noise position corresponding to the data stream according to the error check equation, and generate a burst error indicator accordingly; the internal decoder is configured to decode the data stream to generate an internal decoded stream. The internal decoder includes an erase marker for performing an erase flag procedure on the internal decoded stream based on the burst error indicator to generate an erase indicator corresponding to the internal decoded stream; and an external decoder coupled to An internal decoder for decoding an internal decoded stream corresponding to the erasure indicator to produce a receiver output.
本發明實施例另提供一種種解碼方法,用於解碼資料串流以產生接收器輸出,所述解碼方法包含:依據錯誤檢查方程式決定與資料串流對應之叢發雜訊位置,並相應地產生叢發錯誤指示符;解碼資料串流以產生內部解碼串流;基於叢發錯誤指示符對內部解碼串流執行擦除標記程序,以產生對應於內部解碼串流之擦除指示符;以及解碼與擦除指示符對應之內部解碼串流以產生接收器輸出。The embodiment of the present invention further provides a decoding method for decoding a data stream to generate a receiver output, where the decoding method includes: determining a cluster noise position corresponding to the data stream according to an error checking equation, and generating correspondingly Generating an error indicator; decoding the data stream to generate an internal decoded stream; performing an erase flag procedure on the internal decoded stream based on the burst error indicator to generate an erase indicator corresponding to the internal decoded stream; and decoding An internal decoded stream corresponding to the erase indicator to produce a receiver output.
以上所述的數位通訊裝置及解碼方法能夠增強通訊系統之錯誤校正能力。The digital communication device and the decoding method described above can enhance the error correction capability of the communication system.
於說明書及後續的申請專利範圍當中使用了某些詞彙來指稱特定的組件。所屬領域中具有通常知識者應可理解,硬體製造商可能會用不同的名詞來稱呼同樣的組件。本說明書及後續的申請專利範圍並不以名稱的差異來作為區分組件的方式,而是以組件在功能上的差異來作為區分的準則。於通篇說明書及後續的請求項當中所提及的「包含」係為一開放式的用語,故應解釋成「包含但不限定於」。另外,「耦接」一詞在此係包含任何直接及間接的電氣連接手段。因此,若文中描述一第一裝置耦接於一第二裝置,則代表該第一裝置可直接電氣連接於該第二裝置,或透過其他裝置或連接手段間接地電氣連接至該第二裝置。Certain terms are used throughout the description and subsequent claims to refer to particular components. Those of ordinary skill in the art should understand that hardware manufacturers may refer to the same components by different nouns. The scope of this specification and the subsequent patent application do not use the difference in name as the means of distinguishing components, but the difference in function of components as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means.
第2a圖係依本發明實施例之數位通訊裝置200a之示意圖。於本實施例中,叢發錯誤偵測器300被提供,以基於解調變器110輸出之資料串流#S來偵測叢發錯誤。內部解碼器220採用了擦除標記器225,以基於叢發錯誤偵測器300輸出之叢發錯誤指示符#B來輸出擦除指示符#E。更具體地,當內部解碼器220將資料串流#S解碼為已恢復位元(recovered bit)時,擦除標記器225將資料串流#S於符號級(symbol level)映射至對應的位元。於將內部解碼串流#I轉換為解交錯串流#D時,解交錯器230亦解交錯擦除指示符#E,以產生輸出至外部解碼器240a之解交錯擦除指示符#E’。隨後,外部解碼器240a基於解交錯串流#D及解交錯擦除指示符#E’執行可適性錯誤校正程序,以輸出接收器輸出#OUT。Figure 2a is a schematic illustration of a digital communication device 200a in accordance with an embodiment of the present invention. In the present embodiment, the burst error detector 300 is provided to detect burst errors based on the data stream #S output by the demodulator 110. The internal decoder 220 employs an erasure marker 225 to output an erasure indicator #E based on the burst error indicator #B output from the burst error detector 300. More specifically, when the internal decoder 220 decodes the data stream #S into a recovered bit, the erasure marker 225 maps the data stream #S at the symbol level to the corresponding bit. yuan. When the internal decoded stream #I is converted to the deinterleaved stream #D, the deinterleaver 230 also deinterleaves the erasure indicator #E to produce a deinterleaved erasure indicator #E' that is output to the outer decoder 240a. . Subsequently, the external decoder 240a performs an adaptive error correction procedure based on the deinterleaved stream #D and the deinterleaved erase indicator #E' to output the receiver output #OUT.
應注意,解交錯器230係為可選之組件,其取決於產生射頻信號#RF之傳送器之架構。第2b圖係依本發明實施例之另一數位通訊裝置200b之示意圖,所述數位通訊裝置200b不包含解交錯器230。如第2b圖所示,內部解碼器220提供內部解碼串流#I及擦除指示符#E至外部解碼器240b。隨後,外部解碼器240b基於解交錯串流#D及擦除指示符#E執行可適性錯誤校正程序,以輸出接收器輸出#OUT。各功能區塊之具體操作詳述如下。It should be noted that the deinterleaver 230 is an optional component that depends on the architecture of the transmitter that generates the RF signal #RF. 2b is a schematic diagram of another digital communication device 200b according to an embodiment of the present invention, the digital communication device 200b not including a deinterleaver 230. As shown in FIG. 2b, internal decoder 220 provides internal decoded stream #I and erasure indicator #E to external decoder 240b. Subsequently, the external decoder 240b performs an adaptive error correction procedure based on the deinterleaved stream #D and the erasure indicator #E to output the receiver output #OUT. The specific operation of each functional block is detailed below.
第3a圖係第2a及2b圖所示之叢發錯誤偵測器300之示意圖。資料串流#S係為連續位元串流,其以特定位元率連續輸入至叢發錯誤偵測器300。叢發錯誤偵測器300分析資料串流#S以產生叢發錯誤指示符#B,所述叢發錯誤指示符#B用以表示對應時段中是否出現叢發錯誤。於叢發錯誤偵測器300中,決定單元310截割(slices)或量化資料串流#S,且從資料串流#S中擷取有用位元(useful bit)以產生至少一編碼串流#U。所述有用位元係針對與資料位元一同嵌入資料串流#S中之奇偶校驗位(parity bit)或錯誤檢查碼(error check code)而言,其格式取決於下述的不同編碼方案。舉例而言,資料串流#S可係為符號串流,因此決定單元310可作為限幅器(slicer)或量化器(quantizer),而編碼串流#U可作為編碼位元串流輸出。可選地,若資料串流#S係為並行編碼位元,則編碼串流#U可係為串行編碼位元串流。Figure 3a is a schematic diagram of the burst error detector 300 shown in Figures 2a and 2b. The data stream #S is a continuous bit stream that is continuously input to the burst error detector 300 at a specific bit rate. The burst error detector 300 analyzes the data stream #S to generate a burst error indicator #B, which is used to indicate whether a burst error has occurred in the corresponding time period. In the burst error detector 300, the determining unit 310 slices or quantizes the stream #S, and extracts a useful bit from the stream #S to generate at least one encoded stream. #U. The useful bit is for the parity bit or error check code embedded in the data stream #S together with the data bit, the format of which depends on the different coding schemes described below. . For example, the data stream #S may be a symbol stream, so the decision unit 310 may function as a slicer or a quantizer, and the encoded stream #U may be output as a coded bit stream. Optionally, if the data stream #S is a parallel encoding bit, the encoded stream #U may be a serial encoded bit stream.
聯合邏輯單元320耦接至決定單元310之輸出,用於基於錯誤檢查方程式(error-check equation)對編碼串流#U執行聯合邏輯操作以產生邏輯值#L,所述邏輯值#L用於表示特定時段中特定多個編碼串流#U之正確性。於本實施例中,所述錯誤檢查方程式係藉由與數位通訊裝置200a及200b實施之編碼方案相關之特定演算法得出。所述錯誤檢查方程式可因應實施的編碼方案而改變,其可藉由對應之傳送器之已知架構而預先決定或估計。由於資料串流#S係連續輸入,因此邏輯值#L連續地於每一時槽輸出,且每一邏輯值#L對應於特定多個編碼串流#U。The joint logic unit 320 is coupled to the output of the decision unit 310 for performing a joint logical operation on the encoded stream #U based on an error-check equation to generate a logical value #L for the logical value #L Represents the correctness of a particular multiple encoded stream #U in a particular time period. In the present embodiment, the error checking equation is derived by a specific algorithm associated with the encoding scheme implemented by the digital communication devices 200a and 200b. The error checking equation may vary depending on the coding scheme implemented, which may be predetermined or estimated by the known architecture of the corresponding transmitter. Since the data stream #S is continuously input, the logical value #L is continuously outputted in each time slot, and each logical value #L corresponds to a specific plurality of encoded streams #U.
於聯合邏輯單元320之後,統計單元330編譯一個時段內的多個邏輯值#L,以產生累積值#A。所述時段係針對隨時間偏移之一組連續時槽而言。所述邏輯值#L連續地於每一時槽產生。同時,累積值#A可被較佳地視為連續時槽中多個邏輯值#L之彙總。After joint logic unit 320, statistics unit 330 compiles a plurality of logical values #L over a period of time to produce cumulative value #A. The time period is for a set of consecutive time slots that are offset over time. The logical value #L is continuously generated for each time slot. At the same time, the cumulative value #A can be considered as a summary of a plurality of logical values #L in the continuous time slot.
比較器340耦接至統計單元330,用於比較累積值#A與門檻值#th以偵測是否有叢發錯誤出現。若累積值#A超過門檻值#th,比較器340將叢發錯誤指示符#B設置(asserts)為一個特定值(例如邏輯“1”)以表示叢發錯誤已於近期發生。相反,若累積值#A未超過門檻值#th,則叢發錯誤指示符#B被設置為另一特定值(例如邏輯“0”)。所述門檻值#th可係為固定值、一階(single-level)值或多階(multi-level)值。應注意,其他方式亦可被採用以提供適合的門檻值#th。The comparator 340 is coupled to the statistics unit 330 for comparing the accumulated value #A with the threshold value #th to detect whether a burst error occurs. If the cumulative value #A exceeds the threshold value #th, the comparator 340 asserts the burst error indicator #B to a specific value (eg, a logic "1") to indicate that a burst error has occurred recently. In contrast, if the cumulative value #A does not exceed the threshold value #th, the burst error indicator #B is set to another specific value (for example, a logical "0"). The threshold value #th may be a fixed value, a single-level value, or a multi-level value. It should be noted that other ways can also be employed to provide a suitable threshold value #th.
第3b圖係依第3a圖所示實施例之統計單元330b之示意圖。依據迴旋碼之標準,資料串流#S中之編碼串流#U係藉由編碼週期(時段)來分段,且於統計單元330b中,延遲線(delay line)334被指定以代表所述編碼週期(時段),所述延遲線334包含多行(column),每一行對應於所述時段中一個時槽,且每一行儲存一個邏輯值#L。加法器332自聯合邏輯單元320處連續接收邏輯值#L,以累計延遲線334之每一行。之後,選擇器336偵測編碼串流#U之段邊界(穿刺邊界-puncture boundary),並輸出對應於所述段邊界(穿刺邊界)之累積的行的值以作為累積值#A。偵測所述段邊界之機制可由不同之先前技術得知,其詳細描述不另贅述。Figure 3b is a schematic diagram of a statistical unit 330b according to the embodiment shown in Figure 3a. According to the standard of the convolutional code, the encoded stream #U in the data stream #S is segmented by the encoding period (period), and in the statistical unit 330b, a delay line 334 is designated to represent the The encoding period (period), the delay line 334 includes a plurality of columns, each row corresponding to one time slot in the period, and each row storing one logical value #L. Adder 332 continuously receives logical value #L from joint logic unit 320 to accumulate each row of delay line 334. Thereafter, the selector 336 detects the segment boundary (puncture boundary) of the encoded stream #U, and outputs the value of the accumulated line corresponding to the segment boundary (puncture boundary) as the cumulative value #A. The mechanism for detecting the boundary of the segment can be known from different prior art, and a detailed description thereof will not be repeated.
於統計單元330中,延遲線334中每一行之累積可重複一個或多個時段(編碼串流#S之編碼週期),選擇器336可選擇延遲線334中具有最小初始累積結果之一行作為所述邊界。隨後,選擇器336基於所述邊界,輸出所述累積結果以作為累積值#A。In the statistics unit 330, the accumulation of each row in the delay line 334 may be repeated for one or more time periods (the encoding period of the encoded stream #S), and the selector 336 may select one of the delay lines 334 having the smallest initial cumulative result as the Said the boundary. Subsequently, the selector 336 outputs the cumulative result as the cumulative value #A based on the boundary.
第3c圖係依第3a圖所示實施例之統計單元330c之示意圖。類似地,資料串流#S中之編碼串流#U係藉由編碼週期(時段)來分段,且於統計單元330b中,儲存組件344(例如緩衝器)儲存累積值#A之初始累積結果。加法器332從聯合邏輯單元320處接收邏輯值#L並從儲存組件344接收初始累積結果,以連續地加總每一輸入的邏輯值#L與所述的初始累積結果,並相應地將所述加總結果儲存於儲存組件344中以作為所述的初始累積結果。計數器346計數一個時段(編碼串流#S之編碼週期),從而致能儲存組件344中所述的初始累積結果之輸出,以作為累積值#A。隨後,計數器346重置儲存於儲存組件344中之初始累積結果。Figure 3c is a schematic diagram of a statistical unit 330c according to the embodiment shown in Figure 3a. Similarly, the encoded stream #U in the data stream #S is segmented by the encoding period (period), and in the statistical unit 330b, the storage component 344 (eg, a buffer) stores the initial accumulation of the cumulative value #A. result. Adder 332 receives logical value #L from joint logic unit 320 and receives an initial cumulative result from storage component 344 to continuously sum up each input logical value #L with said initial cumulative result and correspondingly The aggregated results are stored in storage component 344 as the initial cumulative result. The counter 346 counts a time period (the encoding period of the encoded stream #S), thereby enabling the output of the initial accumulated result described in the component 344 to be stored as the cumulative value #A. Counter 346 then resets the initial cumulative result stored in storage component 344.
第4a圖係傳統內部編碼器400之示意圖。內部編碼器400係為符合八階殘邊帶(8-level Vestigial Sideband,8-VSB)標準之傳送器之TCM區塊,所述內部編碼器400包含預編碼器(pre-coder)410、籬柵編碼器(trellis encoder)420及符號映射器(symbol mapper)436。預編碼器410接收兩個資訊位元串流X1 與X2 並分別產生兩個位元串流Y1 與Y2 。預編碼器410具有互斥或(XOR)閘402及延遲週期為12符號之延遲組件404,其接收位元串流X2 以產生位元串流Y2 。籬柵編碼器420接收兩個位元串流Y1 與Y2 並產生三個輸出位元串流U0 、U1 及U2 。所述籬柵編碼器420包含互斥或閘424及延遲週期為12符號之延遲組件422與426,其接收位元串流Y1 並產生輸出位元串流U0 及U1 。符號映射器436接收三個輸出位元串流U0 、U1 及U2 ,並利用8-VSB標準定義之預定符號映射規則產生資料串流#S。Figure 4a is a schematic diagram of a conventional internal encoder 400. The internal encoder 400 is a TCM block conforming to a transmitter of an 8-level Vestigial Sideband (8-VSB) standard, and the internal encoder 400 includes a pre-coder 410 and a fence. A trellis encoder 420 and a symbol mapper 436. The precoder 410 receives two information bits X 1 and X 2 stream and generate two bit streams Y 1 and Y 2. The precoder 410 has a mutually exclusive (XOR) gate 402 and a delay component 404 with a 12-cycle delay period that receives the bit stream X 2 to produce a bit stream Y 2 . Fence encoder 420 receives two bit streams Y 1 and Y 2 and produces three output bit streams U 0 , U 1 , and U 2 . The fence encoder 420 includes a mutex or gate 424 and delay components 422 and 426 having a delay period of 12 symbols, which receive the bit stream Y 1 and produce output bit streams U 0 and U 1 . The symbol mapper 436 receives three bit streams output U 0, U 1 and U 2, and generates a data symbol stream using a predetermined mapping rule #S 8-VSB standard definition.
於籬柵編碼器420中,輸出位元串流U0 及U1 係藉由位元串流Y1 並利用互斥或閘424及兩個延遲組件422與426來決定。依籬柵編碼器420之架構,包含輸出位元串流U0 及U1 且與位元串流Y1 不相關之三個方程式可被決定,其表述如下:To trellis encoder 420, the output bit stream U 0 and U 1 Y 1 bitstreams line by using XOR gate 424 and to determine the two components 422 and 426 delay. Architecture by trellis encoder 420, the bit stream includes an output U 0 and U 1 and may be determined with three equations Y 1 bit stream of uncorrelated, which expressed as follows:
U0 [n]=Q0 [n-1]; (1)U 0 [n]=Q 0 [n-1]; (1)
Q0 [n]=U1 [n]⊕Q1 [n-1]; (2)Q 0 [n]=U 1 [n]⊕Q 1 [n-1]; (2)
Q1 [n-1]=U0 [n-1], (3)Q 1 [n-1]=U 0 [n-1], (3)
其中,n代表索引且每一增量皆對應於一個12符號延遲週期,Q0 及Q1 分別代表延遲組件422與426之輸出。Where n represents an index and each increment corresponds to a 12-symbol delay period, and Q 0 and Q 1 represent the outputs of delay components 422 and 426, respectively.
因此,等式U0[n+1]=U1[n]⊕U0[n-1]可基於方程式(1)、(2)和(3)而推導得出。相應地,誤差檢查方程式可決定如下:Therefore, the equation U0[n+1]=U1[n]⊕U0[n-1] can be derived based on equations (1), (2), and (3). Accordingly, the error checking equation can be determined as follows:
P[n]=U0 [n+1]⊕U1 [n]⊕U0 [n-1] (4)P[n]=U 0 [n+1]⊕U 1 [n]⊕U 0 [n-1] (4)
利用符合8-VSB標準之傳送器固有的錯誤檢查方程式(4),可設計一種計算錯誤量度(error metric)之裝置。P[n]具有邏輯值“0”時表示對應之編碼串流#U正確。相反,P[n]具有邏輯值“1”時則表示對應之編碼串流#U不正確。A device for calculating an error metric can be designed using the error checking equation (4) inherent to the transmitter conforming to the 8-VSB standard. When P[n] has a logical value of "0", it indicates that the corresponding encoded stream #U is correct. Conversely, when P[n] has a logical value of "1", it means that the corresponding encoded stream #U is incorrect.
第4b圖係決定單元310a及響應第4a圖所示內部編碼器400之聯合邏輯單元320a之示意圖。於聯合邏輯單元320a中,延遲組件405與互斥或閘407構成第3a圖所示之聯合邏輯單元320。決定單元310a及聯合邏輯單元320a於第3a圖之實施例中被採用,以構成叢發錯誤偵測器300。Figure 4b is a schematic diagram of the decision unit 310a and the joint logic unit 320a of the internal encoder 400 shown in Figure 4a. In joint logic unit 320a, delay component 405 and mutex or gate 407 form joint logic unit 320 as shown in FIG. 3a. Decision unit 310a and joint logic unit 320a are employed in the embodiment of FIG. 3a to form burst error detector 300.
舉例而言,通常源自解調變器110之等化器之資料串流#S被輸入至決定單元310a。利用與第4a圖中內部編碼器400之符號映射器436之符號映射規則對稱之符號映射規則,決定單元310a產生三個編碼串流U0 ’、U1 ’及U2 ’。若編碼串流U0 ’、U1 ’及U2 ’係為正確的,則可假定資料串流#S中之對應符號亦係為正確的。因此,聯合邏輯單元320a之延遲組件405可被用以簡化方程式(4),其中編碼串流U1 ’被延遲12符號,編碼串流U0 ’被延遲24符號。隨後,互斥或閘407接收延遲的編碼串流U0 ’及U1 ’以執行錯誤檢查操作,而互斥或閘407輸出之邏輯值#L則代表錯誤檢查結果。顯然,於本實施例中,邏輯值“0”代表設置為正確的,而邏輯值“1”則代表設置為不正確的。For example, the data stream #S, which is usually derived from the equalizer of the demodulation transformer 110, is input to the decision unit 310a. The decision unit 310a generates three encoded streams U 0 ', U 1 ', and U 2 ' using the symbol mapping rules symmetric with the symbol mapping rules of the symbol mapper 436 of the inner encoder 400 in FIG. 4a. If the encoded streams U 0 ', U 1 ', and U 2 ' are correct, it can be assumed that the corresponding symbols in the data stream #S are also correct. Thus, the delay component 405 of the joint logic unit 320a can be used to simplify equation (4) where the encoded stream U 1 ' is delayed by 12 symbols and the encoded stream U 0 ' is delayed by 24 symbols. Subsequently, the mutex or gate 407 receives the delayed encoded streams U 0 ' and U 1 ' to perform an error checking operation, and the logical value #L of the mutex or gate 407 output represents an error check result. Obviously, in the present embodiment, the logical value "0" represents the setting to be correct, and the logical value "1" represents the setting to be incorrect.
第5a圖係傳統內部編碼器500之示意圖。內部編碼器500係為符合ITU-T Recommendation J.83 Annex B(以下稱為J83B)標準之傳送器之TCM區塊,其係利用64正交振幅調變(Quadrature Amplitude Modulation,QAM)機制。於第5a圖中,內部編碼器500連續接收7位元之資料串流#Din。解析器(parser)540識別一組的四個7位元符號(亦即28位元),並指定同相(in-phase)之“I”組分及正交(quadrature)之“Q”組分。如第5a圖所示,對於I組分,解析器540輸出上部(upper)之兩個未編碼位元串流502(I2 ,I5 ,I8 ,I11 ,I13 )、504(I1 ,I4 ,I7 ,I10 ,I12 )以及下部(lower)之編碼位元串流512a(I0 ,I3 ,I6 ,I9 )。而對於Q組分,解析器540輸出上部的兩個未編碼位元串流506(Q2 ,Q5 ,Q8 ,Q11 ,Q13 )、508(Q1 ,Q4 ,Q7 ,Q10 ,Q12 )以及下部的編碼位元串流512b(Q0 ,Q3 ,Q6 ,Q9 )。未編碼位元串流502、504、506及508被發送至QAM映射器530,而編碼位元串流512a及512b則被發送至差分預編碼器510。差分預編碼器510對I與Q之位元對Q0 與I0 、Q3 與I3 、Q6 與I6 及Q9 與I9 執行旋轉不變籬柵編碼(rotationally invariant trellis coding)。差分預編碼器510隨後將差分編碼之下部串流#X與#Y(4位元)分別傳送至穿刺二進位迴旋編碼器(punctured binary convolutional encoder)520a與520b。Figure 5a is a schematic diagram of a conventional internal encoder 500. The internal encoder 500 is a TCM block of a transmitter conforming to the ITU-T Recommendation J.83 Annex B (hereinafter referred to as J83B) standard, which utilizes a 64 Quadrature Amplitude Modulation (QAM) mechanism. In Figure 5a, internal encoder 500 continuously receives a 7-bit data stream #Din. A parser 540 identifies a set of four 7-bit symbols (ie, 28 bits) and specifies the "I" component of the in-phase and the "Q" component of the quadrature. . As shown in Figure 5a, for the I component, the parser 540 outputs two uncoded bitstreams 502 (I 2 , I 5 , I 8 , I 11 , I 13 ), 504 (I) of the upper (upper). 1 , I 4 , I 7 , I 10 , I 12 ) and a lower encoded bit stream 512a (I 0 , I 3 , I 6 , I 9 ). For the Q component, the parser 540 outputs the upper two uncoded bitstreams 506 (Q 2 , Q 5 , Q 8 , Q 11 , Q 13 ), 508 (Q 1 , Q 4 , Q 7 , Q). 10 , Q 12 ) and the lower encoded bit stream 512b (Q 0 , Q 3 , Q 6 , Q 9 ). Uncoded bitstreams 502, 504, 506, and 508 are sent to QAM mapper 530, and encoded bitstreams 512a and 512b are sent to differential precoder 510. Differential precoder 510 performs rotationally invariant trellis coding for bit pairs Q 0 and I 0 , Q 3 and I 3 , Q 6 and I 6 and Q 9 and I 9 for I and Q. The differential precoder 510 then transmits the differentially encoded lower stream streams #X and #Y (4 bits) to the punctured binary convolutional encoders 520a and 520b, respectively.
於本實施例中,4/5速率(4/5-rate)之穿刺二進位迴旋編碼器520a與520b係基於具有穿刺碼之1/2速率之二進位迴旋編碼器。通常而言,於數位通訊系統中,錯誤校正碼被用以增加冗餘(redundancy)以提升抗雜訊能力。於1/2速率下,穿刺二進位迴旋編碼器520a與520b接收4位元(#X與#Y)並產生8個編碼位元。此外,若所有編碼位元皆被作為負荷(payload)傳送,則負荷可因過度之冗餘而極大地減少,穿刺二進位迴旋編碼器520a與520b應用之穿刺功能可用於補償負荷之減少。換言之,一些編碼位元之傳送先前係由傳送器同意的,且接收器被旁路(bypassed)。穿刺二進位迴旋編碼器520a與520b符合J83B標準,其為每8個編碼位元傳送5個位元,從而導致總的穿刺碼率為4/5。亦即,依據4個輸入位元產生5個位元。In the present embodiment, the 4/5 rate (4/5-rate) puncture binary encoders 520a and 520b are based on a binary cyclotron encoder having a 1/2 rate of the puncture code. In general, in digital communication systems, error correction codes are used to increase redundancy to improve noise immunity. At a rate of 1/2, the puncture binary encoders 520a and 520b receive 4 bits (#X and #Y) and produce 8 coded bits. In addition, if all of the coded bits are transmitted as payloads, the load can be greatly reduced due to excessive redundancy, and the puncture function applied by the puncture binary encoders 520a and 520b can be used to compensate for the reduction in load. In other words, the transmission of some coded bits was previously agreed by the transmitter and the receiver was bypassed. The puncture binary encoders 520a and 520b conform to the J83B standard, which transmits 5 bits for every 8 coded bits, resulting in a total puncture rate of 4/5. That is, 5 bits are generated based on 4 input bits.
最後,QAM映射器530接收未編碼位元串流502、504、506及來自穿刺二進位迴旋編碼器520a與520b之編碼串流#U(U1 ,U2 ,U3 ,U4 ,U5 )與#V(V1 ,V2 ,V3 ,V4 ,V5 ),並產生64QAM資料串流#S。Finally, QAM mapper 530 receives encoded bit stream 502, and not from the puncture binary convolutional encoder 520a and 520b of an encoding stream #U (U 1, U 2, U 3, U 4, U 5 ) with #V(V 1 , V 2 , V 3 , V 4 , V 5 ), and generate 64QAM data stream #S.
第5b圖係依第5a圖所示內部編碼器500之穿刺二進位迴旋編碼器520a之示意圖。由於穿刺二進位迴旋編碼器520b與520a之架構類似,故穿刺二進位迴旋編碼器520b將不再詳細描述。應注意,下述討論中推導出之錯誤檢查方程式亦可適用於穿刺二進位迴旋編碼器520b。穿刺二進位迴旋編碼器520a包含四個延遲組件555、兩個互斥或閘524與526以及轉向器(commutator)528。四個延遲組件555儲存四個先前輸入位元X[0]、X[-1]、X[-2]及X[-3],從而穿刺二進位迴旋編碼器520a中具有16個狀態。如第5b圖所示,碼OUTU 及OUTL 可表示如下:Figure 5b is a schematic diagram of a puncture binary encoder 520a of the internal encoder 500 shown in Figure 5a. Since the architecture of the puncture binary encoders 520b and 520a is similar, the puncture binary encoder 520b will not be described in detail. It should be noted that the error checking equation derived in the following discussion may also be applied to the puncture binary encoder 520b. The puncture binary cyclotron encoder 520a includes four delay components 555, two mutually exclusive or gates 524 and 526, and a commutator 528. The four delay components 555 store four previous input bits X[0], X[-1], X[-2], and X[-3], thereby having 16 states in the puncture binary encoder 520a. As shown in Figure 5b, the codes OUT U and OUT L can be expressed as follows:
OUTU =X[1]⊕X[-1]⊕X[-3]; (5)OUT U =X[1]⊕X[-1]⊕X[-3]; (5)
OUTL =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-3] (6)OUT L =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-3] (6)
方程式(5)和(6)係藉由產生碼(generating code)G1 與G2 來決定,其中G1=[010101],G2=[011111]。應注意,不同的迴旋編碼器具有不同的產生碼。轉向器528之穿刺功能係利用穿刺矩陣(puncture matrix)[P1;P2]=[0001;1111]來實現,其中“0”表示該位元不傳送,“1”表示該位元依序傳送。Equations (5) and (6) are determined by generating codes G 1 and G 2 , where G1 = [010101] and G2 = [011111]. It should be noted that different cyclotron encoders have different generation codes. The puncture function of the diverter 528 is implemented using a puncture matrix [P1; P2] = [0001; 1111], where "0" indicates that the bit is not transmitted, and "1" indicates that the bit is transmitted sequentially.
對於每一籬柵組(trellis group)而言,穿刺二進位迴旋編碼器520a可從表示為X[1]、X[2]、X[3]及X[4]之4個輸入位元中產生8個編碼位元。依據穿刺矩陣,轉向器528從8個編碼位元中選擇5個位元以作為編碼串流#U。此處,一組編碼串流(例如U[5]、U[4]、U[3]、U[2]、U[1])可被表示為對應的一組輸入位元(例如X[4]、X[3]、X[2]、X[1])與先前輸入位元(X[0]、X[-1]、X[12]、X[-3])之方程式。一般而言,對於第n組,5個輸出位元可表示如下:For each trellis group, the puncture binary encoder 520a can be from four input bits denoted as X[1], X[2], X[3], and X[4]. Generate 8 coded bits. Based on the puncture matrix, the diverter 528 selects 5 bits from the 8 coded bits as the encoded stream #U. Here, a set of encoded streams (eg, U[5], U[4], U[3], U[2], U[1]) can be represented as a corresponding set of input bits (eg, X[ 4], X[3], X[2], X[1]) and the equations of the previously input bits (X[0], X[-1], X[12], X[-3]). In general, for the nth group, the 5 output bits can be expressed as follows:
U[n+1]=X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]U[n+1]=X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]
U[n+2]=X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]U[n+2]=X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]⊕X[n-2]
U[n+3]=X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]U[n+3]=X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]⊕X[n-1]
U[n+4]=X[n+4]⊕X[n+2]⊕X[n]U[n+4]=X[n+4]⊕X[n+2]⊕X[n]
U[n+5]=X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]U[n+5]=X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]⊕X[n]
其中,n代表索引。除第n組之外,先前兩組(第(n-2)及(n-1)組)及後續兩組(第(n+1)及(n+2)組)亦列示如下,以作參考:Where n is the index. Except for the nth group, the previous two groups (the (n-2) and (n-1) groups) and the following two groups (the (n+1) and (n+2) groups) are also listed as follows. Reference:
U[n-9]=X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]⊕X[n-11]U[n-9]=X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]⊕X[n-11]
U[n-8]=X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]U[n-8]=X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]⊕X[n-10]
U[n-7]=X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]U[n-7]=X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]⊕X[n-9]
U[n-6]=X[n-4]⊕X[n-6]⊕X[n-8]U[n-6]=X[n-4]⊕X[n-6]⊕X[n-8]
U[n-5]=X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]U[n-5]=X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]⊕X[n-8]
U[n-4]=X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]U[n-4]=X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]⊕X[n-7]
U[n-3]=X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]U[n-3]=X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]⊕X[n-6]
U[n-2]=X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]U[n-2]=X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]⊕X[n-5]
U[n-1]=X[n]⊕X[n-2]⊕X[n-4]U[n-1]=X[n]⊕X[n-2]⊕X[n-4]
U[n]=X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]U[n]=X[n]⊕X[n-1]⊕X[n-2]⊕X[n-3]⊕X[n-4]
U[n+6]=X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]U[n+6]=X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]⊕X[n+1]
U[n+7]=X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]U[n+7]=X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]⊕X[n+2]
U[n+8]=X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]U[n+8]=X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]⊕X[n+3]
U[n+9]=X[n+8]⊕X[n+6]⊕X[n+4]U[n+9]=X[n+8]⊕X[n+6]⊕X[n+4]
U[n+10]=X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]U[n+10]=X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]⊕X[n+4]
U[n+11]=X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]U[n+11]=X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]⊕X[n+5]
U[n+12]=X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]U[n+12]=X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]⊕X[n+6]
U[n+13]=X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]U[n+13]=X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]⊕X[n+7]
U[n+14]=X[n+12]⊕X[n+10]⊕X[n+8]U[n+14]=X[n+12]⊕X[n+10]⊕X[n+8]
U[n+15]=X[n+12]⊕X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]U[n+15]=X[n+12]⊕X[n+11]⊕X[n+10]⊕X[n+9]⊕X[n+8]
依據上述連續5組之輸出位元,可推導出與輸入位元X不相關之下述等式:Based on the above five consecutive output bits, the following equations that are not related to input bit X can be derived:
U[n-6]⊕U[n-5]⊕U[n-4]⊕U[n-3]⊕U[n-2]⊕U[n-1]⊕U[n+1]⊕U[n+4]⊕U[n+5]⊕U[n+8]⊕U[n+9]⊕U[n+11]⊕U[n+12]⊕U[n+13]⊕U[n+14]⊕U[n+15]≡0U[n-6]⊕U[n-5]⊕U[n-4]⊕U[n-3]⊕U[n-2]⊕U[n-1]⊕U[n+1]⊕U [n+4]⊕U[n+5]⊕U[n+8]⊕U[n+9]⊕U[n+11]⊕U[n+12]⊕U[n+13]⊕U[ n+14]⊕U[n+15]≡0
其亦可被進一步推導為多項式形式,表示為:It can also be further derived as a polynomial form, expressed as:
P(x)=x*(1+x+x2 +x3 +x4 +x6 +x7 +x10 +x11 +x14 +x16 +x17 +x18 +x19 +x20 +x21 ) (7)P(x)=x*(1+x+x 2 +x 3 +x 4 +x 6 +x 7 +x 10 +x 11 +x 14 +x 16 +x 17 +x 18 +x 19 +x 20 +x 21 ) (7)
利用符合J83B標準之傳送器固有之錯誤檢查方程式(7),可設計出第3a圖所示之聯合邏輯單元320。The joint logic unit 320 shown in Fig. 3a can be designed using the error checking equation (7) inherent to the transmitter conforming to the J83B standard.
另一方面,於J83B纜線系統(cable system)之接收器中,由於不存在訓練序列(training sequence),從傳入(incoming)位元串流中確定穿刺邊界或穿刺位置(puctured position)係為必要的。如上所述,一組5個輸出碼位元係藉由4個輸入位元產生,其表明接收器中TCM解碼器之傳入位元串流具有5個可能之穿刺位置。因此,錯誤檢查方程式(7)僅可應用於5個可能之穿刺位置中的正確穿刺位置(穿刺邊界)。On the other hand, in the receiver of the J83B cable system, since there is no training sequence, the puncture boundary or the puncture position is determined from the incoming bit stream. As necessary. As described above, a set of 5 output code bits is generated by 4 input bits indicating that the incoming bit stream of the TCM decoder in the receiver has 5 possible puncture locations. Therefore, the error checking equation (7) can only be applied to the correct puncture position (puncture boundary) among the five possible puncture positions.
第5c圖係響應第5b圖所示穿刺二進位迴旋編碼器520a之聯合邏輯單元320b之示意圖,其符合J83B標準並利用錯誤檢查方程式(7)來檢驗資料串流#S之正確性。於數位通訊裝置200中,射頻信號#RF被接收,並被解調變器110連續地解調變為資料串流#S,本實施例係利用64-QAM解調變機制。聯合邏輯單元320b包含延遲線560及互斥或閘562,其中延遲線560包含串接之多個延遲組件D,且互斥或閘562具有多個輸入,所述多個輸入分別耦接至延遲線電路延遲線560之多個延遲組件D之一部分的輸出。第3a圖所示之決定單元310接收資料串流#S之同相及正交組分以再次擷取第5a圖所述之編碼串流#U與#V。於本實施例中,僅描述編碼串流#U。Figure 5c is a schematic diagram of the joint logic unit 320b in response to the puncture binary encoder 520a shown in Figure 5b, which conforms to the J83B standard and uses error checking equation (7) to verify the correctness of the data stream #S. In the digital communication device 200, the radio frequency signal #RF is received and continuously demodulated by the demodulator 110 into a data stream #S. This embodiment utilizes a 64-QAM demodulation mechanism. The joint logic unit 320b includes a delay line 560 and a mutex or gate 562, wherein the delay line 560 includes a plurality of delay components D connected in series, and the mutex or gate 562 has a plurality of inputs, the plurality of inputs being respectively coupled to the delay The line circuit delays the output of one of the plurality of delay components D of the line 560. The decision unit 310 shown in Fig. 3a receives the in-phase and quadrature components of the data stream #S to retrieve the encoded streams #U and #V described in Fig. 5a again. In the present embodiment, only the encoded stream #U is described.
編碼串流#U被傳送至聯合邏輯單元320b。於聯合邏輯單元320b中,延遲線560利用多個延遲組件D儲存編碼串流#U之有限序列。於本實施例中,延遲線560具有21個延遲組件D以儲存編碼串流#U中從U[n-6]至U[n+14]之序列。依據錯誤檢查方程式(7),第1(右側)、2、3、4、5、6、8、11、12、15、16、18、19、20、21(左側)個延遲單元D之輸出及當前位元連接至互斥或閘562之輸入。互斥或閘562連續地對上述輸入執行互斥或操作以輸出多個連續的邏輯值#L。其中每一邏輯值#L代表錯誤檢查方程式(7)之一個結果。The encoded stream #U is passed to the federated logic unit 320b. In joint logic unit 320b, delay line 560 stores a limited sequence of encoded streams #U using a plurality of delay components D. In the present embodiment, delay line 560 has 21 delay components D to store the sequence from U[n-6] to U[n+14] in encoded stream #U. According to the error check equation (7), the output of the first (right), 2, 3, 4, 5, 6, 8, 11, 12, 15, 16, 18, 19, 20, 21 (left) delay units D And the current bit is connected to the input of the mutex or gate 562. The mutex or gate 562 continuously performs a mutual exclusion or operation on the above input to output a plurality of consecutive logical values #L. Each of the logical values #L represents a result of the error check equation (7).
可選地,叢發錯誤偵測器300可廣泛地於所有叢發錯誤偵測之應用中使用。舉例而言,第5d圖所示係為穿刺二進位迴旋編碼器520d,其係藉由數位視訊廣播(Digital Video Broadcasting,DVB)標準ETSI EN 300 744 V1.4.1(2001-01)定義並具有包含1/2、2/3及3/4之不同穿刺碼率(punctured code rate)。穿刺二進位迴旋編碼器520d包含6個延遲組件555、兩個互斥或閘524與526以及轉向器528。6個延遲組件555儲存6個先前輸入位元X[0]、X[-1]、X[-2]、X[-3]、X[-4]及X[-5]。如第5d圖所示,輸入轉向器528之碼OUTU 及OUTL 可表示如下:Alternatively, the burst error detector 300 can be used in a wide variety of burst detection applications. For example, Figure 5d shows a puncture binary encoder 520d, which is defined by the Digital Video Broadcasting (DVB) standard ETSI EN 300 744 V1.4.1 (2001-01) and has 1/2, 2/3 and 3/4 different punctured code rates. The puncture binary cyclotron encoder 520d includes six delay components 555, two mutually exclusive gates 524 and 526, and a diverter 528. The six delay components 555 store six previous input bits X[0], X[-1]. , X[-2], X[-3], X[-4], and X[-5]. As shown in Figure 5d, the codes OUT U and OUT L of the input diverter 528 can be expressed as follows:
OUTU =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-5]; (8)OUT U =X[1]⊕X[0]⊕X[-1]⊕X[-2]⊕X[-5]; (8)
OUTL =X[1]⊕X[-1]⊕X[-2]⊕X[-4]⊕X[-5] (9)OUT L =X[1]⊕X[-1]⊕X[-2]⊕X[-4]⊕X[-5] (9)
歐洲DVB標準建議之三個穿刺碼率包含1/2、2/3及3/4。依據方程式(8)、(9)及特定穿刺碼率,可推導出至少一個僅包含輸出位元及其奇偶校驗多項式之等式。為簡便起見,相關推導於此不另贅述。The three puncture rates recommended by the European DVB standard include 1/2, 2/3 and 3/4. Based on equations (8), (9) and the specific puncture code rate, at least one equation containing only the output bit and its parity polynomial can be derived. For the sake of brevity, the relevant derivation will not be repeated here.
當穿刺碼率設定為1/2時,穿刺序列[1-up 1-down]可表示為:When the puncture rate is set to 1/2, the puncture sequence [1-up 1-down] can be expressed as:
U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]
U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]
U[3]=X[2]+X[1]+X[0]+X[-1]+X[-4]U[3]=X[2]+X[1]+X[0]+X[-1]+X[-4]
類似地,U[4]~U[16]亦可自穿刺序列獲取。因此,基於U[1]~U[16]可得出如下等式:Similarly, U[4]~U[16] can also be obtained from the puncture sequence. Therefore, based on U[1]~U[16], the following equation can be derived:
U[1]⊕U[2]⊕U[4]⊕U[5]⊕U[7]⊕U[8]⊕U[11]⊕U[13]⊕U[15]⊕U[16]=0U[1]⊕U[2]⊕U[4]⊕U[5]⊕U[7]⊕U[8]⊕U[11]⊕U[13]⊕U[15]⊕U[16]= 0
錯誤檢查方程式亦可由此得出,其可表示為:The error checking equation can also be derived from this, which can be expressed as:
P(x)=1+x+x3 +x5 +x8 +x9 +x11 +x12 +x14 +x15 (10)P(x)=1+x+x 3 +x 5 +x 8 +x 9 +x 11 +x 12 +x 14 +x 15 (10)
當穿刺碼率設定為2/3時,穿刺序列[1-up 1-down 2-down]可表示為:When the puncture rate is set to 2/3, the puncture sequence [1-up 1-down 2-down] can be expressed as:
U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]
U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]
U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]
U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]
類似地,U[5]~U[20]亦可自穿刺序列獲取。因此,基於穿刺碼率設定為2/3之U[1]~U[16],可得出如下錯誤檢查方程式:Similarly, U[5]~U[20] can also be obtained from the puncture sequence. Therefore, based on the U[1] to U[16] whose puncture rate is set to 2/3, the following error checking equation can be obtained:
U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[8]⊕U[10]⊕U[12]⊕U[13]⊕U[15]⊕U[18]⊕U[19]⊕U[20]=0U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[8]⊕U[10]⊕U[12]⊕U[13]⊕U[15]⊕U[18]⊕ U[19]⊕U[20]=0
其多項式形式表示為:P(x)=1+x+x2 +x5 +x7 +x8 +x10 +x12 +x16 +x17 +x18 +x19 (11)Its polynomial form is expressed as: P(x)=1+x+x 2 +x 5 +x 7 +x 8 +x 10 +x 12 +x 16 +x 17 +x 18 +x 19 (11)
更進一步,當穿刺碼率設定為3/4時,穿刺序列[1-up 1-down 2-down 3-up]可表示為:Further, when the puncture rate is set to 3/4, the puncture sequence [1-up 1-down 2-down 3-up] can be expressed as:
U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]U[1]=X[1]+X[0]+X[-1]+X[-2]+X[-5]
U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]U[2]=X[1]+X[-1]+X[-2]+X[-4]+X[-5]
U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]U[3]=X[2]+X[0]+X[-1]+X[-3]+X[-4]
U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]U[4]=X[3]+X[2]+X[1]+X[0]+X[-3]
U[5]=X[4]+X[3]+X[2]+X[1]+X[-2]U[5]=X[4]+X[3]+X[2]+X[1]+X[-2]
類似地,U[6]~U[34]亦可自穿刺序列獲取。因此,基於穿刺碼率設定為2/3之U[1]~U[16],所述等式可表示如下:Similarly, U[6]~U[34] can also be obtained from the puncture sequence. Therefore, based on the puncture code rate set to 2/3 U[1] to U[16], the equation can be expressed as follows:
U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[7]⊕U[10]⊕U[14]⊕U[15]⊕U[16]⊕U[24]⊕U[28]⊕U[29]⊕U[31]⊕U[32]⊕U[33]⊕U[34]=0U[1]⊕U[2]⊕U[3]⊕U[4]⊕U[7]⊕U[10]⊕U[14]⊕U[15]⊕U[16]⊕U[24]⊕ U[28]⊕U[29]⊕U[31]⊕U[32]⊕U[33]⊕U[34]=0
其多項式形式為:Its polynomial form is:
P(x)=1+x+x2 +x3 +x5 +x6 +x10 +x18 +x19 +x20 +x24 +x27 +x30 +x31 +x32 +x33 (12)P(x)=1+x+x 2 +x 3 +x 5 +x 6 +x 10 +x 18 +x 19 +x 20 +x 24 +x 27 +x 30 +x 31 +x 32 +x 33 (12)
顯然,第5c圖所建議之架構可被修飾,以實施例如(10)、(11)及(12)之不同的錯誤檢查方程式。It will be apparent that the architecture suggested by Figure 5c can be modified to implement different error checking equations such as (10), (11) and (12).
第6圖係藉由第2a及2b圖之擦除標記器225實施之擦除標記程序之範例的示意圖。第6圖之上部係叢發錯誤指示符#B之狀態。於週期C1 中,叢發錯誤指示符#B為高(high),表明有叢發錯誤出現。於週期C2 中,叢發錯誤指示符#B為低(low),表明沒有叢發錯誤出現。Fig. 6 is a diagram showing an example of an erasure marking program implemented by the erasure marker 225 of Figs. 2a and 2b. The state above the top of Figure 6 is the status of the burst error indicator #B. In cycle C 1, burst error indicator #B high (high), shows that there are burst errors. In cycle C 2, burst error indicator #B is low (low), showed no burst error.
舉例而言,第2a及2b圖之內部解碼器220可採用維特比演算法(Viterbi Algorithm)以解碼資料串流#S,第6圖中部係從藉由內部解碼器220執行之回溯(trace back)程序中找出的殘餘路徑(survivor path),用以解碼其中的內部解碼串流#I。所述擦除標記程序係於維特比解碼程序運行期間執行。由於週期C1 中出現叢發錯誤,其需要更高之標準來決定擦除。帶有陰影之節點(shadowed node)代表標記的狀態。相反地,由於週期C2 中未出現叢發錯誤,其可使用更低之標準來決定擦除。第6圖之下部係擦除指示符#E之信號狀態,其係依據籬柵圖(Trellis diagram)中殘餘路徑上之標記而決定。若殘餘路徑上一個狀態被標記,則擦除標記器225發出邏輯“1”之擦除指示符#E。相反地,若殘餘路徑上一個狀態未被標記,則擦除標記器225發出邏輯“0”之擦除指示符#E。For example, the internal decoder 220 of the 2a and 2b diagrams may employ a Viterbi Algorithm to decode the data stream #S, and the sixth picture is from the backtrack performed by the internal decoder 220 (trace back) The residual path found in the program is used to decode the internal decoded stream #I. The erase mark program is executed during the operation of the Viterbi decoding program. Since the burst error cycle C 1, which requires a higher standard of decision erased. The shadowed node represents the state of the marker. Conversely, since the C 2 period not burst errors, which can be determined using standard lower the erasure. The lower part of Fig. 6 is the signal state of the erasure indicator #E, which is determined according to the mark on the residual path in the Trellis diagram. If a state on the residual path is flagged, the erase marker 225 issues an erase indicator #E of logic "1". Conversely, if a state on the residual path is not marked, the erase marker 225 issues an erase indicator #E of logic "0".
第6圖所示之實施例可致能第2a圖之外部解碼器240a,以根據不可靠位置解碼解交錯串流#D,其中,所述不可靠位置已被解交錯擦除指示符#E’確定為與解交錯串流#D對應之擦除位置,且解交錯擦除指示符#E’係第2a圖之解交錯器230藉由解交錯擦除指示符#E而產生。類似地,第6圖所示之實施例可用於第2b圖之外部解碼器240b,以根據已被擦除指示符#E確定為與內部解碼串流#I對應之擦除位置的不可靠位置解碼內部解碼串流#I。The embodiment shown in Fig. 6 can enable the outer decoder 240a of Fig. 2a to decode the deinterleaved stream #D according to the unreliable position, wherein the unreliable position has been deinterleaved with the erase indicator #E 'Determining the erasure position corresponding to the deinterleaved stream #D, and the deinterleaving erasure indicator #E' is the deinterleaver 230 of Fig. 2a generated by deinterleaving the erasure indicator #E. Similarly, the embodiment shown in FIG. 6 can be used in the external decoder 240b of FIG. 2b to determine an unreliable position of the erased position corresponding to the internal decoded stream #I based on the erased indicator #E. Decode the internal decoded stream #I.
第7a圖係依本發明實施例之外部解碼器240a的示意圖,所述外部解碼器240a用於校正解交錯串流#D以產生接收器輸出#OUT。解交錯串流#D係為(n,k,2t)RS編碼信號。外部解碼器240a包含第一錯誤校正單元710、第二錯誤校正單元720及多工器730。如上所述,第2a圖中之數位通訊裝置200a係為串接式碼接收器,擦除標記器225之運行係依據由耦接至解調變器110之叢發錯誤偵測器300決定之叢發錯誤位置,且執行解碼期間由解交錯器130產生之解交錯擦除指示符#E’係表示解交錯串流#D中之不可靠位置。Figure 7a is a schematic diagram of an external decoder 240a for correcting the deinterleaved stream #D to produce a receiver output #OUT, in accordance with an embodiment of the present invention. The deinterleaved stream #D is an (n, k, 2t) RS coded signal. The external decoder 240a includes a first error correcting unit 710, a second error correcting unit 720, and a multiplexer 730. As described above, the digital communication device 200a in FIG. 2a is a serial-type code receiver, and the operation of the erasure marker 225 is determined by the burst error detector 300 coupled to the demodulation transformer 110. The burst location is incorrect, and the deinterleaved erase indicator #E' generated by the deinterleaver 130 during execution of the decoding represents the unreliable position in the deinterlaced stream #D.
於外部解碼器240a中,第一錯誤校正單元710解碼解交錯串流#D以產生第一初始輸出#O1。由於第一錯誤校正單元710之運行與解交錯擦除指示符#E’無關,因此,可能由擦除標記器225執行之不正確的擦除標記程序不會影響第一錯誤校正單元710之性能。第一錯誤校正單元710最多可校正每一碼字中t個錯誤。另一方面,第二錯誤校正單元720依據解交錯擦除指示符#E’解碼解交錯串流#D以產生第二初始輸出#O2。更具體地,藉由將解交錯擦除指示符#E’確定之不可靠位置作為擦除位置,第二錯誤校正單元720解碼解交錯串流#D。若2x+y≦2t,則一個碼字內的x個錯誤及y個擦除可被成功校正。亦即,藉由解交錯擦除指示符#E’提供之額外資訊,第二錯誤校正單元720最多可校正2t個擦除。換言之,若一個碼字內所有錯誤位置皆被擦除標記器225準確地決定為擦除位置,且沒有不正確的擦除位置被標記,第二錯誤校正單元720最多可校正2t個錯誤,其相當於第一錯誤校正單元710校正能力的兩倍。In the outer decoder 240a, the first error correcting unit 710 decodes the deinterleaved stream #D to generate a first initial output #O1. Since the operation of the first error correction unit 710 is independent of the deinterlace erase indicator #E', the incorrect erase flag program that may be performed by the erase marker 225 does not affect the performance of the first error correction unit 710. . The first error correction unit 710 can correct up to t errors in each codeword. On the other hand, the second error correcting unit 720 decodes the deinterleaved stream #D in accordance with the deinterlace erasure indicator #E' to generate a second initial output #O2. More specifically, the second error correcting unit 720 decodes the deinterleaved stream #D by taking the unreliable position determined by the deinterlace erasure indicator #E' as the erasing position. If 2x+y≦2t, x errors and y erases within one codeword can be successfully corrected. That is, the second error correcting unit 720 can correct up to 2t erasures by additionally providing the information provided by the interleave erasure indicator #E'. In other words, if all the error positions in a code word are accurately determined by the erasure marker 225 as the erasure position, and no incorrect erasure position is marked, the second error correction unit 720 can correct up to 2t errors. It is equivalent to twice the correction capability of the first error correcting unit 710.
於本實施例中,第一錯誤校正單元710與第二錯誤校正單元720可並行運作。對於解交錯串流#D中每一碼字而言,第一錯誤校正單元710與第二錯誤校正單元720皆可嘗試解碼所述碼字以分別產生第一初始輸出#O1及第二初始輸出#O2。上述方案可於解交錯串流#D中一個碼字之錯誤數量不超過t時確保外部解碼器240a之校正能力,並於解交錯串流#D中一個碼字之錯誤數量超過t時增強外部解碼器240a之校正能力。In this embodiment, the first error correction unit 710 and the second error correction unit 720 can operate in parallel. For each codeword in the deinterlaced stream #D, both the first error correction unit 710 and the second error correction unit 720 may attempt to decode the codeword to generate a first initial output #O1 and a second initial output, respectively. #O2. The above solution can ensure the correction capability of the external decoder 240a when the number of errors of one codeword in the deinterleaved stream #D does not exceed t, and enhance the external when the number of errors of one codeword in the deinterleaved stream #D exceeds t Correction capability of decoder 240a.
此外,當解碼解交錯串流#D之碼字時,第一錯誤校正單元710進一步產生第一標誌#f1,以表示是否解交錯串流#D中每一碼字皆已被第一錯誤校正單元710成功校正。類似地,當依據解交錯擦除指示符#E’解碼解交錯串流#D之碼字時,第二錯誤校正單元720亦產生第二標誌#f2,以表示是否解交錯串流#D中每一碼字皆已被第二錯誤校正單元720成功校正。依據第一標誌#f1及第二標誌#f2,多工器730選擇第一初始輸出#O1及第二初始輸出#O2其中之一以作為接收器輸出#OUT。In addition, when decoding the codeword of the deinterleaved stream #D, the first error correcting unit 710 further generates the first flag #f1 to indicate whether each codeword in the deinterleaved stream #D has been corrected by the first error. Unit 710 is successfully corrected. Similarly, when the codeword of the deinterleaved stream #D is decoded according to the deinterlace erasure indicator #E', the second error correcting unit 720 also generates the second flag #f2 to indicate whether to deinterleave the stream #D Each codeword has been successfully corrected by the second error correction unit 720. According to the first flag #f1 and the second flag #f2, the multiplexer 730 selects one of the first initial output #O1 and the second initial output #O2 as the receiver output #OUT.
由於第一錯誤校正單元710係為相對可靠之解碼器,且其性能不會受到可能由擦除標記器225執行之不正確的擦除標記程序的影響,因此,只要第一標誌#f1表示解交錯串流#D已被第一錯誤校正單元710成功校正以產生第一初始輸出#O1,則多工器730可選擇第一初始輸出#O1以作為接收器輸出#OUT。Since the first error correcting unit 710 is a relatively reliable decoder and its performance is not affected by an incorrect erasure marking program that may be performed by the erasure marker 225, as long as the first flag #f1 indicates a solution The interleaved stream #D has been successfully corrected by the first error correcting unit 710 to generate the first initial output #O1, and the multiplexer 730 can select the first initial output #O1 as the receiver output #OUT.
於本實施例中,解交錯器230不僅限於係為必要組件。一般而言,解交錯器230被置於第一錯誤校正單元710與第二錯誤校正單元720之輸入端之前,以於解交錯串流#D輸入第一錯誤校正單元710與第二錯誤校正單元720之前解交錯來自內部解碼器220之內部解碼串流#I,並解交錯擦除指示符#E,從而產生解交錯擦除指示符#E’並將其提供至第二錯誤校正單元720。可選地,如第2b圖所示,外部解碼器240b直接連接至內部解碼器220,以處理內部解碼串流#I而並非解交錯串流#D。In the present embodiment, the deinterleaver 230 is not limited to being a necessary component. In general, the deinterleaver 230 is placed before the input of the first error correcting unit 710 and the second error correcting unit 720 to input the first error correcting unit 710 and the second error correcting unit to deinterleave the stream #D. The internal decoded stream #I from the internal decoder 220 is deinterleaved before 720, and the erasure erase indicator #E is deinterleaved, thereby generating the deinterleaved erase indicator #E' and supplying it to the second error correcting unit 720. Alternatively, as shown in FIG. 2b, external decoder 240b is directly coupled to internal decoder 220 to process internal decoded stream #I instead of deinterleaved stream #D.
第7b圖係類似於第7a圖所示實施例之外部解碼器240b之示意圖。外部解碼器240b係於第2b圖所示之實施例中採用,其基於擦除指示符#E及內部解碼串流#I而運作,解交錯器230於第2b圖中被省略。第一錯誤校正單元710解碼內部解碼串流#I以產生第一初始輸出#O1,且第二錯誤校正單元720依據擦除指示符#E解碼內部解碼串流#I以產生第二初始輸出#O2。更具體地,藉由將擦除指示符#E確定之不可靠位置作為擦除位置,第二錯誤校正單元720解碼解交錯串流#D。當解碼內部解碼串流#I之碼字時,第一錯誤校正單元710進一步產生第一標誌#f1,以表示是否內部解碼串流#I中每一碼字皆已被第一錯誤校正單元710成功校正。類似地,當依據擦除指示符#E解碼內部解碼串流#I之碼字時,第二錯誤校正單元720亦產生第二標誌#f2,以表示是否內部解碼串流#I中每一碼字皆已被第二錯誤校正單元720成功校正。依據第一標誌#f1及第二標誌#f2,多工器730選擇第一初始輸出#O1及第二初始輸出#O2其中之一以作為接收器輸出#OUT。基於以上所述外部解碼器240a之相關描述,本領域熟習該項技藝者應可知悉外部解碼器240b如何執行所述操作及功能。因此,其操作及功能之詳細描述於此不另贅述。Figure 7b is a schematic diagram similar to external decoder 240b of the embodiment shown in Figure 7a. The external decoder 240b is employed in the embodiment shown in FIG. 2b, which operates based on the erasure indicator #E and the internal decoded stream #I, and the deinterleaver 230 is omitted in FIG. 2b. The first error correction unit 710 decodes the internal decoded stream #I to generate a first initial output #O1, and the second error correction unit 720 decodes the internal decoded stream #I according to the erasure indicator #E to generate a second initial output # O2. More specifically, the second error correcting unit 720 decodes the deinterleaved stream #D by taking the unreliable position determined by the erasure indicator #E as the erasing position. When decoding the codeword of the internal decoded stream #I, the first error correcting unit 710 further generates the first flag #f1 to indicate whether each codeword in the internal decoded stream #I has been used by the first error correcting unit 710. Successfully corrected. Similarly, when the codeword of the internal decoded stream #I is decoded according to the erasure indicator #E, the second error correcting unit 720 also generates the second flag #f2 to indicate whether each code in the stream #I is internally decoded. The words have all been successfully corrected by the second error correcting unit 720. According to the first flag #f1 and the second flag #f2, the multiplexer 730 selects one of the first initial output #O1 and the second initial output #O2 as the receiver output #OUT. Based on the above description of the external decoder 240a, those skilled in the art will be aware of how the external decoder 240b performs the operations and functions. Therefore, detailed descriptions of its operations and functions are not described herein.
以上所述僅為本發明之較佳實施例,舉凡熟悉本案之人士援依本發明之精神所做之等效變化與修飾,皆應涵蓋於後附之申請專利範圍內。The above are only the preferred embodiments of the present invention, and equivalent changes and modifications made by those skilled in the art to the spirit of the present invention are intended to be included in the scope of the appended claims.
100...接收器100. . . receiver
110...解調變器110. . . Demodulation transformer
120...內部解碼器120. . . Internal decoder
130...解交錯器130. . . Deinterleaver
140...外部解碼器140. . . External decoder
200a、200b...數位通訊裝置200a, 200b. . . Digital communication device
220...內部解碼器220. . . Internal decoder
225...擦除標記器225. . . Erase marker
230...解交錯器230. . . Deinterleaver
240a、240b...外部解碼器240a, 240b. . . External decoder
300...叢發錯誤偵測器300. . . Crash error detector
310、310a...決定單元310, 310a. . . Decision unit
320、320a、320b...聯合邏輯單元320, 320a, 320b. . . Joint logical unit
330、330b、330c...統計單元330, 330b, 330c. . . Statistical unit
340...比較器340. . . Comparators
332...加法器332. . . Adder
334、560...延遲線334, 560. . . Delay line
336...選擇器336. . . Selector
344...儲存組件344. . . Storage component
346...計數器346. . . counter
400、500...內部編碼器400, 500. . . Internal encoder
410...預編碼器410. . . Precoder
420...籬柵編碼器420. . . Fence encoder
436...符號映射器436. . . Symbol mapper
402、424、407、524、526、562...互斥或閘402, 424, 407, 524, 526, 562. . . Mutual exclusion or gate
404、422、426、405、555...延遲組件404, 422, 426, 405, 555. . . Delay component
510...差分預編碼器510. . . Differential precoder
512a、512b...編碼位元串流512a, 512b. . . Coded bit stream
502、504、506、508...未編碼位元串流502, 504, 506, 508. . . Uncoded bit stream
520a、520b、520d...穿刺二進位迴旋編碼器520a, 520b, 520d. . . Puncture binary rotary encoder
530...QAM映射器530. . . QAM mapper
540...解析器540. . . Parser
528...轉向器528. . . Steering gear
710...第一錯誤校正單元710. . . First error correction unit
720...第二錯誤校正單元720. . . Second error correction unit
730...多工器730. . . Multiplexer
第1圖係傳統接收器之示意圖。Figure 1 is a schematic diagram of a conventional receiver.
第2a圖係依本發明實施例之數位通訊裝置之範例的示意圖。Figure 2a is a schematic illustration of an example of a digital communication device in accordance with an embodiment of the present invention.
第2b圖係依本發明實施例之數位通訊裝置之另一範例的示意圖。Figure 2b is a schematic illustration of another example of a digital communication device in accordance with an embodiment of the present invention.
第3a圖係依本發明實施例之叢發錯誤偵測器之範例的示意圖。Figure 3a is a schematic diagram of an example of a burst error detector in accordance with an embodiment of the present invention.
第3b圖係依第3a圖所示實施例之統計單元之範例的示意圖。Figure 3b is a schematic diagram of an example of a statistical unit of the embodiment shown in Figure 3a.
第3c圖係依第3a圖所示實施例之統計單元之另一範例示意圖。Figure 3c is a diagram showing another example of a statistical unit according to the embodiment shown in Figure 3a.
第4a圖係傳統內部編碼器之示意圖。Figure 4a is a schematic diagram of a conventional internal encoder.
第4b圖係決定單元及響應第4a圖所示內部編碼器之聯合邏輯單元之範例的示意圖。Figure 4b is a schematic diagram of an example of a decision unit and a joint logic unit responsive to the internal encoder shown in Figure 4a.
第5a圖係另一傳統內部編碼器之示意圖。Figure 5a is a schematic diagram of another conventional internal encoder.
第5b圖係依第5a圖所示內部編碼器之穿刺二進位迴旋編碼器之範例示意圖。Figure 5b is a schematic diagram showing an example of a puncture binary cyclotron encoder of the internal encoder shown in Figure 5a.
第5c圖係響應第5b圖所示穿刺二進位迴旋編碼器之聯合邏輯單元之範例的示意圖。Figure 5c is a schematic diagram of an example of a joint logic unit responsive to the puncture binary encoder shown in Figure 5b.
第5d圖係依第5a圖所示內部編碼器之穿刺二進位迴旋編碼器之另一範例的示意圖。Figure 5d is a schematic diagram of another example of a puncture binary rotary encoder of the internal encoder shown in Figure 5a.
第6圖係擦除標記程序之範例的示意圖。Figure 6 is a schematic diagram of an example of an erase marking procedure.
第7a圖係外部解碼器之範例的示意圖。Figure 7a is a schematic diagram of an example of an external decoder.
第7b圖係外部解碼器之另一範例的示意圖。Figure 7b is a schematic diagram of another example of an external decoder.
110...解調變器110. . . Demodulation transformer
200a...數位通訊裝置200a. . . Digital communication device
220...內部解碼器220. . . Internal decoder
225...擦除標記器225. . . Erase marker
230...解交錯器230. . . Deinterleaver
240a...外部解碼器240a. . . External decoder
300...叢發錯誤偵測器300. . . Crash error detector
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US20050022095A1 (en) * | 2003-07-10 | 2005-01-27 | Samsung Electronics Co., Ltd. | Error correction decoding method and apparatus |
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US5206864A (en) * | 1990-12-04 | 1993-04-27 | Motorola Inc. | Concatenated coding method and apparatus with errors and erasures decoding |
US20040061964A1 (en) * | 2002-10-01 | 2004-04-01 | Kabushiki Kaisha Toshiba | Method and apparatus for turbo coding and decoding in a disk drive |
US20050022095A1 (en) * | 2003-07-10 | 2005-01-27 | Samsung Electronics Co., Ltd. | Error correction decoding method and apparatus |
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