TWI402851B - Electronic devices and the related data transmission methods - Google Patents

Description

Electronic device and data transmission method thereof

The invention relates to data transmission, in particular to data transmission of flash memory.

The general principle of random access memory (DRAM) operation, using the charge and discharge of similar capacitors to determine the 0 or 1 of the storage bit, must also recharge and discharge the DRAM to ensure storage The existence of information. However, the flash memory, the unit of storage is called a basic cell, and the gate and gate of the internal metal-oxide-semiconductor (MOS) device. In addition, there is only one layer of oxide oxide than the conventional one, and another layer of floating gate is added. Also because of this layer of floating gates, the flash memory can operate in three modes: writing, reading, and erasing. When a negative electron is injected into the floating gate, the cell is written as 0 from the digit 1. When the negative electron is removed, the cell is equivalent to changing from 0 to 1, which is equivalent to the erase operation.

Moreover, compared with the traditional storage devices, flash memory has gradually become a substitute for traditional storage devices due to its low power consumption, high reliability, and fear of vibration and other manufacturing costs. However, since flash memory usually brings a relatively high error rate, in order to meet the requirements of high reliability, a specific algorithm is needed to perform error checking and correction on the data.

The invention provides an electronic device comprising a flash memory, a memory controller, a buffer unit and an error checking and correcting circuit, wherein the flash memory is used for storing a first data, and the memory controller is not subjected to an error. Checking and writing the first data in parallel with the error checking and correcting circuit, and the error checking and correcting circuit performs error checking and correction on the first data to output a result signal to the buffer unit, and the buffer unit is based on the result The signal corrects the first data as a first valid data.

The invention also provides an electronic device comprising a buffer unit; a flash memory for storing a plurality of data; and a memory controller for sequentially outputting a plurality of data without error checking and correction; The error checking and correcting circuit is configured to perform error checking and correction on the plurality of pieces of data to generate a corresponding plurality of result signals; and an arbitration unit for sequentially transmitting the plurality of pieces of data output by the memory controller to the buffer And receiving, by the unit, one of the plurality of result signals, interrupting the current data transmission, and transmitting the result signal to the buffer unit; wherein the buffer unit corrects one of the plurality of data according to the result signal In order to serve as a valid material.

The present invention also provides a data transmission method, comprising: reading and receiving a first data from a flash memory; writing a first data that has not undergone error checking and correction into a buffer unit; writing the first data Simultaneously, a buffer unit performs error checking and correction on the first data to generate a result signal; and corrects the first data as a valid data by the result signal.

The invention also provides a data transmission method, which comprises receiving a plurality of data; and sequentially outputting the plurality of data to a buffer unit, and sequentially performing error checking and correction on the plurality of data to generate a corresponding plurality of result signals; Receiving one of the plurality of result signals, interrupting the current data transmission and transmitting the result signal to the buffer unit; and correcting one of the plurality of data according to the result signal by the buffer unit to serve as a Valid information.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

In order to improve the data transmission performance of the entire electronic system, the original data read by the flash memory in the electronic system is directly sent to a data buffer through the memory controller, regardless of whether the data is erroneous or not. As will be appreciated by those skilled in the art, the data buffer of the present invention is broadly defined and is not limited to local small-capacity storage units, for example, may be the main memory of a computer system. Although the original data has been saved to the data buffer, the data cannot be directly sent to the backend device at this time, and the data is allowed to be sent to the backend device only after the error detection and correction is completed. If the error check and correction circuit detects a data error, the data can be corrected in the data buffer. At the same time of error correction, the following original data can continue to be sent to the data buffer without interruption, so that the bus of the flash memory will not be stopped due to the error correction.

Figure 1 is a schematic diagram showing one of an electronic device. As shown, the electronic device 100A includes a flash memory 10, a memory controller 20, an Error Check and Correct (ECC) circuit 30, a buffer unit 40, and an interface unit 50. For example, the electronic device 200 can be a computer system, and the electronic device 100A can be a storage device, such as a portable hard disk, a solid state disk (SSD), but is not limited thereto.

The flash memory 10 is used as a non-volatile memory for storing data. The memory controller 20 is configured to read the data stored in the flash memory 10 and output it to the error checking and correction circuit 30 and the buffer unit 40. The buffer unit 40 can be a first in first out (FIFO), but is not limited thereto. The buffer unit 40 includes a storage array 42 for storing data and a control logic circuit 44 for controlling the operation of the buffer unit 40, and the storage array 42 is composed of a plurality of buffers 421 to 423. The interface unit 50 can be connected to the electronic device 200 by a Universal Serial Bus (USB), an Integrated Device Electronic (IDE), or a Serial Advanced Technology Attachment (SATA). Data transmission is performed, but is not limited to this.

In the embodiment of the present invention, the memory controller 20 directly writes the original data OD (ie, the data that has not undergone error checking and correction) read from the flash memory 10 into the buffer unit 40 without The error checking and correction circuit 30 is waited for error checking and correction of the original material OD. The buffer unit 40 corrects the original data OD and acts as a valid data VS according to the error check and correction circuit 30 for error detection and correction of the original data OD, and transmits the valid data VS through the interface unit 50. Go to the electronic device 200. Therefore, the data transmission between the flash memory 10 and the memory controller 20 will not be interrupted due to error checking and correction, so that the performance degradation of the system can be avoided.

The detailed operation of the electronic device 100A will be described below with reference to Fig. 2 . As shown in the figure, S1 represents a data stream written by the memory controller 20 to the buffer unit 40, S2 represents an error check and correction cycle, and S3 represents a result signal RS output by the error check and correction circuit 30. The data stream, and S4 is a data stream representing the valid data transmitted by the buffer unit 40 to the electronic device 200.

The memory controller 20 sequentially writes the original data OD1 OD3 (that is, the data that has not undergone error checking and correction) read by the flash memory 10 into the buffer unit 40, and at the same time, the memory controller 20 The original data OD1~OD3 are also sequentially transmitted to the error checking and correction circuit 30 for error checking and correction. For example, the memory controller 20 sequentially writes the original data OD1 OD3 to the buffers 421 423 423 in the buffer unit 40.

In the error check and correction period ECC1, the error check and correction circuit 30 performs error check and correction on the original data OD1 to generate a corresponding result signal RS1, and outputs it to the buffer unit 40. The buffer unit 40 corrects the original data OD1 stored in the buffer 421 according to the result signal RS1 as a valid data VS1. At this time, the buffer unit 40 can transmit the valid data VS1 to the electronic device 200 through the interface unit 50.

In the error check and correction period ECC2, the error check and correction circuit 30 performs error check and correction on the original data OD2 to generate a corresponding result signal RS2, and outputs it to the buffer unit 40. The buffer unit 40 corrects the original data OD2 stored in the buffer 422 according to the result signal RS2 as a valid data VS2. At this time, the buffer unit 40 can transmit the valid data VS2 to the electronic device 200 through the interface unit 50, and so on. Moreover, in some embodiments, multiple error checking and correction circuits 30 can be used to simultaneously perform error checking and correction on multiple pieces of original data.

Figure 3 is another embodiment of the electronic device of the present invention. As shown, the electronic device 100B is similar to that shown in FIG. 1 except that an arbitration unit 60 is disposed between the memory controller 20 and the error checking and correction circuit 30 and the buffer unit 40. Arbitration unit 60 is operative to selectively output raw data from memory controller 20 or result signals from error checking and correction circuit 30.

In this embodiment, the memory controller 20 outputs the original data OD1 read by the flash memory 10 (ie, data that has not undergone error checking and correction) to the arbitration unit 60, and at the same time, the memory control. The device 20 also transmits the original data OD1 to the error checking and correction circuit 30 for error checking and correction. At this time, since the error check and correction of the original data OD1 have not been completed, the arbitration unit 60 writes the received original data OD1 into the buffer 421 of the buffer unit 40. Then, the memory controller 20 sequentially reads the original data OD2 and OD3 from the flash memory 10, and sequentially outputs the data OD2 and OD3 to the arbitration unit 60, and the arbitration unit 60 follows the original data OD2 and OD3 received. The sequence is written in the buffers 422 and 423 of the buffer unit 40. When the error check and correction of the original material OD1 is completed, the error check and correction circuit 30 generates a corresponding result signal RS1, which is output to the arbitration unit 60. When the arbitration unit 60 receives the result signal RS1, it interrupts the current data transmission, transmits the resultant signal RS1 to the buffer unit 40, and then resumes the data transmission. Further, the buffer unit 40 corrects the original material OD1 in accordance with the result signal RS1 so as to be a valid data VS1. At this time, the buffer unit 40 can transmit the valid data VS1 to the electronic device 200 through the interface unit 50, and so on.

Figure 4 is another embodiment of an electronic device. As shown, the electronic device 100C is similar to the electronic device 100A shown in FIG. 1 with the difference that it further includes a central processing unit 70 and a bus bar 80. The central processing unit 70 is coupled to the memory controller 20, the error checking and correction circuit 30, the buffer unit 40, and the interface unit 50 via the bus bar 80. The operations of the memory controller 20, the error check and correction circuit 30, the buffer unit 40, and the interface unit 50 are the same as those shown in Figs. 1 and 2, and will not be described again. It should be noted that when the error checking and correction circuit 30 detects that one of the original materials OD1 OD OD3 cannot be corrected, a signal SI is generated to notify the central processing unit 70 to enable the memory controller 20 to be flashed. Re-read the data in memory or perform other processing. In addition, when it is detected that the storage queue 42 has been full, the control logic circuit 44 in the buffer unit 40 outputs a signal SF to notify the memory controller 20 to temporarily stop the data transmission. Moreover, when it is detected that the storage queue 42 has been emptied, the control logic circuit 44 in the buffer unit 40 outputs a signal SE notification interface unit 50 to temporarily stop transmitting data to the electronic device 200.

In summary, in the present invention, when the original data OD1 is erroneously checked and corrected, the memory controller 20 continues to send subsequent original data (for example, OD2, OD3, ...) into the buffer unit 40, so the flash memory The data transfer between the 10 and the memory controller 20 will not be interrupted due to error checking and correction. Moreover, the buffer unit 40 corrects the received data according to the result signal generated by the error check and correction circuit 30, and then transmits the data to the electronic device 200 through the interface unit 50.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope is subject to the definition of the scope of the patent application attached.

10. . . Flash memory

20. . . Memory controller

30. . . Error checking and correction circuit

40. . . Buffer unit

42. . . Storage queue

44. . . Control logic

50. . . Interface unit

60. . . Arbitration unit

100A~100C, 200. . . Electronic device

421~423. . . Buffer

OD, OD1~OD3. . . Source material

ECC1~ECC2. . . Error checking and correction cycle

RS, RS1, RS2. . . Result signal

VS, VS1, VS2. . . Valid data

S1. . . Data stream written by the memory controller to the buffer unit

S2. . . Error checking and correction cycle

S3. . . Data flow of the result signal output by the error check and correction circuit

S4. . . Data stream of valid data transmitted by the buffer unit to the electronic device

SF, SE, SI. . . signal

Figure 1 shows an embodiment of an electronic device.

Figure 2 is a flow chart of data transmission of one of the electronic devices.

Figure 3 shows another embodiment of an electronic device.

Figure 4 is a diagram showing another embodiment of an electronic device.

10. . . Flash memory

20. . . Memory controller

30. . . Error checking and correction circuit

40. . . Buffer unit

42. . . Storage queue

44. . . Control logic

50. . . Interface unit

60. . . Arbitration unit

100A, 200. . . Electronic device

421~423. . . Buffer

OD. . . Source material

RS. . . Result signal

VS. . . Valid data

Claims (13)

An electronic device comprising: a flash memory for storing a first data; a buffer unit; an error checking and correcting circuit; a memory controller, wherein the first data is written in parallel to the buffer unit and An error checking and correcting circuit, and the error checking and correcting circuit performs error checking and correction on the first data to output a result signal to the buffer unit, and the buffer unit corrects the first data according to the result signal. As a first valid data, the memory controller outputs a second data to the buffer unit when the error checking and correcting circuit performs error checking and correction on the first data. The electronic device of claim 1, further comprising: an arbitration unit, configured to receive the first data, the second data output by the memory controller, and the output of the error checking and correcting circuit The result signal is outputted, and one of the second data and the result signal is outputted to the buffer unit. The electronic device of claim 2, wherein the arbitration unit interrupts transmission of the second data when receiving the result signal to transmit the received result signal to the buffer unit. The electronic device of claim 1, further comprising an interface unit for reading the first effective one of the buffer units Data and transfer to another electronic device. The electronic device of claim 1, wherein the buffer unit comprises: a buffer for storing the first data; and a control logic circuit for correcting and storing in the buffer according to the result signal. The first information in the above is obtained to obtain the first valid data mentioned above. An electronic device comprising: a buffer unit; a flash memory for storing a plurality of data; a memory controller for sequentially outputting the plurality of data without error checking and correction; an error check and a correction circuit for performing error checking and correction on the plurality of pieces of data to generate a corresponding plurality of result signals; and an arbitration unit for sequentially transmitting the plurality of pieces of data output by the memory controller to And the buffer unit, when receiving one of the plurality of result signals, interrupting the current data transmission, and transmitting the received result signal to the buffer unit; wherein the buffer unit is based on the result signal, Correct one of the above plurality of data to be used as a valid material. The electronic device of claim 6, further comprising an interface unit for reading the above-mentioned effective resources in the buffer unit And transferred to another electronic device. A data transmission method includes: performing a error check and correction on the first data to generate a result signal while writing a first data to a buffer unit; and correcting the first data by using the result signal, As a first valid material. The data transmission method of claim 8, further comprising transmitting the first valid data in the buffer unit to an electronic device. The data transmission method of claim 8, further comprising: receiving a second data; and if the second data and the result signal are simultaneously received, outputting the second data and one of the result signals To the above buffer unit. The data transmission method of claim 10, further comprising, when receiving the result signal, suspending transmission of the second data to the buffer unit. A data transmission method includes: receiving a plurality of data; sequentially outputting the plurality of data to a buffer unit, and sequentially performing error checking and correction on the plurality of data to generate a corresponding plurality of result signals; Receiving one of the plurality of result signals, interrupting the current data transmission, and transmitting the received result signal And to the buffer unit; and correcting one of the plurality of pieces of data according to the received result signal to serve as a valid data. The data transmission method of claim 12, further comprising transmitting the valid data in the buffer unit to an electronic device.