TWI402764B - Discrete graphics system, computer system for discrete graphics system, dgs unit, dgs housing, and method thereof - Google Patents

Description

Separate graphics system, computer system for separate graphics system, separate graphics system unit, separate graphics system (DGS) cover, and method thereof

The invention is generally related to computer graphics execution. More particularly, the present invention relates to a highly scalable graphics processor for each graphics application. The present invention discloses a separate graphics method and system for a form factor independent of a computer system motherboard.

Rendering of 3D graphics is very popular among various video games and other applications. The calculus is a generic term that describes an overall multi-step process that converts a database representation from one of the 3D objects into an imaginary two-dimensional projection of the object on a viewing plane.

The calculation process involves a number of steps, such as setting a polygon model containing the information required for the shadow/texturing process, applying a linear transformation to the polygon mesh model, trimming the polygon to conform to a viewport, scanning Converting/rasterizing the polygon to a set of pixel coordinates and dimming/brightening the individual pixels using interpolated or progressive shading techniques.

Graphics Processing Units (GPUs) are specially designed integrated circuit devices widely used in graphics systems to accelerate the performance of 3D calculus applications. GPUs are commonly used in conjunction with a central processing unit (CPUs) to create 3D images for execution on one or more applications on a computer system. Today's GPUs typically use a graphics pipeline to process data.

The power supply of today's GPU subsystems (such as additional graphics cards, etc.) is gradually increasing to include a larger amount of overall power supply value of a desktop computer system, and can be combined with a CPU of an electrical system in complexity and precision. Compare it. A modern GPU can include an integrated circuit device with more than 200 million transistors and operating at hundreds of millions of hertz. Today's GPUs can consume hundreds of watts of power and require carefully designed thermal protection components (such as cooling fans, contact with adequate airflow, etc.).

In general, the configuration and performance of the GPU subsystem (eg, GPU graphics card) can be limited by several overall system design factors. The GPU subsystem is typically designed to interface with an ATX-compatible computer system motherboard. The ATX motherboard size specification refers to the industry standard motherboard board size specifications that are widely used by leading industry manufacturers. Such manufacturers include, for example, CPU manufacturers, chipset manufacturers, motherboard manufacturers, and the like.

For example, the ATX motherboard size specification provides a limited amount of space for a card-based GPU. A typical plug-in GPU is connected to the motherboard through an AGP slot. The AGP slot has a limited amount of space available to the plug-in GPU. This limited space directly affects the efficiency of the thermal protection components of the plug-in GPU. In addition, as the performance of plug-in GPUs increases, the available power (ie, specified voltage and current) of the AGP connection has become insufficient.

The BTX motherboard size specification refers to an updated industry standard motherboard motherboard size specification. The BTX motherboard size specification is considered to be the next-generation ATX continuation specification for a "desktop" PC chassis, and is supported by the industry's leading manufacturers as well as the older ATX motherboard size specifications. Unfortunately, the BTX motherboard size specification has even encountered even more problems with high performance GPU subsystems.

A problem with the size of the BTX motherboard is that the BTX design specification has many limitations on the style and performance of the GPU subsystem. For example, the BTX design specification places the CPU of the desktop system at the front-end entrance for cooling airflow, and places the GPU subsystem (such as a graphics card) on the downward airflow of the CPU, and on the GPU. The physical size of the system (i.e., x-y-z size), available airflow, available thermal dissipation, and power transfer are limited.

Similar limitations exist in the notebook computer motherboard size specifications. For example, the future evolution of the GPU subsystem of a notebook computer is limited by the fact that the notebook computer rack (eg, motherboard platform, chassis, airflow, etc.) is optimized for CPUs and their associated needs. This optimization limits the available heat dissipation arrangements, power transfer, and physical dimensions (ie, x-y-z dimensions) that any graphics subsystem implements.

Certain emerging industry standards will also limit the future performance evolution of the GPU subsystem. PCI Express is one such standard. Some versions of the PCI Express standard specify a maximum available power for a connected device (eg, the PCI SIG specification specifies 150 watts for PCI Express graphics). As GPU subsystem performance continues to increase, the demands of higher-order GPU implementations can significantly exceed the specified maximum available power. In addition to insufficient power, some versions of the PCI Express standard specify insufficient bandwidth between the GPU subsystem and other computer system platforms (such as system memory, CPU, etc.). The insufficient bandwidth limits the channel between the GPU subsystem and the resources of the computer system platform, thereby limiting the upward scaling capability of the GPU subsystem performance.

Embodiments of the present invention provide a separate graphics method and system for a motherboard module size independent of a computer system. Embodiments of the present invention should eliminate data transmission bandwidth limitations and motherboard size limitations that limit the upward scaling capability of a GPU subsystem.

In one embodiment, the present invention is implemented as a discrete graphics system (DGS) for executing 3D graphics instructions of a computer system. The split graphics system includes one or more GPUs for executing 3D graphics instructions and a DGS system chassis for configuring the GPU(s). A sequence of busbar connectors is built into the DGS system rack and is used to connect the GPU(s). Having the sequence busbar connector detachably connect the DGS and the GPU(s) to the computer system. The GPU(s) of the DGS accesses the computer system through the serial bus connector to execute 3D graphics commands of the computer system. In one embodiment, the calculated 3D data is then passed back to the computer system for display on a display connected to one of the computer systems. In another embodiment, the calculated 3D data is passed to a display that is directly connected to the DGS for display to the user. In an embodiment, the DGS uses a plurality of plug-in GPUs. The GPUs can be implemented as a single GPU add-on graphics card (eg, one GPU per card), a multi-GPU add-on graphics card (eg, two or more GPUs per card). In an embodiment, multiple pieces of additional graphics cards are used, with each card having two or more GPUs.

In one embodiment, the invention is implemented as a DGS (Separate Graphics System) unit. The DGS unit includes a rack for configuring a GPU and a mounting unit coupled to the system rack and for housing the GPU. a sequence of busbar connectors connected to the rack and connected to the GPU mounting unit, wherein the serial busbar connector is configured to removably connect the GPU to a computer system to cause the CPU to connect through the serial busbar The device accesses the computer system and executes 3-D graphics commands of the computer system. A power supply is coupled to the system rack to provide power independent of the computer system to the GPU. In an embodiment, the DGS unit includes a thermal management system to cool the GPU and the power supply. In another embodiment, the DGS unit includes a volume management system to control operation of the thermal management system and the power supply to limit noise generated by the DGS unit. In an embodiment, the DGS uses a plurality of plug-in GPUs. The GPUs can be implemented as a single GPU add-on graphics card (eg, one GPU per card), a multi-GPU add-on graphics card (eg, two or more GPUs per card). In an embodiment, multiple pieces of additional graphics cards are used, with each card having two or more GPUs.

In one embodiment, the invention is implemented as a scalable split graphics system (DGS). The DGS includes a sequence of bus bridges (eg, PCI Express) for connecting multiple GPUs to a sequence of busses. A sequence of bus bar connectors is connected to the sequence bus bar bridge. A system rack is coupled to the sequence bus bridge and the serial bus connector and is configured to house the GPUs. The serial bus connector can be removably coupled to a computer system. The GPUs access the computer system through the serial bus bridge and the serial bus connector to collectively execute 3-D graphics commands of the computer system. In one embodiment, the serial bus bridge is enabled to up-scaling the 3-D computational performance of the computer system by connecting at least one new GPU to operate in conjunction with an existing GPU. The new GPU and the existing GPU jointly execute graphics instructions of the computer system. In an embodiment, the multi-GPU graphics system uses a plurality of plug-in GPUs. The GPUs can be implemented as a single GPU add-on graphics card (eg, one GPU per card), a multi-GPU add-on graphics card (eg, two or more GPUs per card). In an embodiment, multiple pieces of additional graphics cards are used, with each card having two or more GPUs.

Reference will now be made in detail to the preferred embodiments of the invention, and Even though the invention will be described in connection with the preferred embodiments, it is understood that the invention is not intended to limit the invention. Rather, the invention is intended to cover alternatives, modifications, and equivalents, which are included in the spirit and scope of the invention as defined by the appended claims. In the following detailed description of the embodiments of the invention, the invention However, those skilled in the art will appreciate that the invention may be practiced without these specific details. In other cases, methods and procedures are known. The components and circuits are not described in detail since they do not unnecessarily obstruct the embodiments of the present invention.

MARKS AND NAMES: Certain portions of the detailed description are presented in terms of procedures, steps, logic blocks, processing, and other operational symbol representations on a data bit in a computer memory. These descriptions and representations are the tools used by those skilled in the art to more effectively express their substantial works to other skilled artisans. A program, computer execution steps, logic blocks, processing, etc., are generally considered to be a self-consistent sequence of steps or instructions leading to a desired result. This step requires a physical manipulation of the physical quantity. Although not necessarily, these quantities are generally in the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated in a computer. It has proven convenient to classify these signals as bits, values, items, symbols, features, forms, numbers, etc., primarily for reasons of general usage.

However, it should be understood that all of these and similar terms are related to the appropriate physical quantities and are merely convenient labels for these quantities. Unless otherwise stated in the following description, it should be understood that in various parts of the invention, such as "processing" or "accessing" or "executing" or "storing" Terms such as "storing" or "rendering" refer to the operation and processing of a computer system (such as computer system 100 of Figure 1) or similar electronic computing device, which is manipulated and will be registered and memorized by the computer system. The data presented by the physical (electronic) quantity in the volume is converted to other data similarly presented in the physical quantity of the computer system memory or login or other such information storage, transmission or display device.

Computer System Platform: Referring now to Figure 1, a computer system 100 in accordance with an embodiment of the present invention is illustrated. Computer system 100 in accordance with an embodiment of the present invention provides the execution platform for implementing a portion of the software-based functionality of the present invention. As shown in FIG. 1, the computer system 100 includes a CPU 101 and a system memory 102. A separate graphics system 110 (e.g., DGS thereafter) is coupled to the CPU 101 and the system memory 102 via a bus 115 and a bridge 120. In the system 100 embodiment, the system memory 102 stores instructions and data for the CPU 101 and the DGS 110. The DGS 110 accesses the system memory 102 through the bridge 120. The bridge 120 communicates with the DGS 110 through the bus bar 115 and operates by bridging the bus bar 115 and the individual data formats of the computer system 100. It should be noted that the computer system 100 includes any type of computer device including, but not limited to, a desktop computer, a server, a workstation, a notebook computer, a computer-based simulator, a palmtop computer, and other portable/handheld devices. Devices such as a number of assistants, tablet computers, game controllers, mobile phones, smart phones, handheld gaming systems, and the like.

As previously mentioned, some of the processes and steps of the present invention are implemented in one embodiment as a computer readable memory (e.g., system memory 102) in a computer system (e.g., system 100) and are A series of instructions (such as a software program) executed by the CPU 101 and the DGS 110. When executed, the instructions cause the computer system 100 to perform the functions of the present invention as described below.

The computer system 100 embodiment of Figure 1 illustrates the incorporation of a basic component of a computer system to perform 3D graphics instructions using a DGS 110. The DGS 110 includes at least one GPU to execute 3D graphics instructions. The GPU(s) are enclosed in a DGS system rack for accommodating the GPU(s) and providing the necessary resources for optimal operation. The DGS 110 includes a sequence of bus bar connectors to connect the bus bar 115 and thereby connect the DGS 110 to the bus bar component 120. In one embodiment, the bus bar 115 is a PCI Express sequence bus. The GPU(s) of the DGS 110 accesses the computer system through the sequence bus 115 to execute 3D graphics commands of the computer system. In this manner, the DGS 110 provides a separate graphics system that is separate and independent of the resources/limitations of the computer system 100. The internal components of the DGS 110 will be described in more detail below (e.g., Figure 7, etc.).

2 illustrates a DGS 110 in accordance with an embodiment of the present invention, wherein the DGS 110 is directly coupled to a display 201 (eg, a liquid crystal display, a video tube display, etc.). In this embodiment, the DGS 110 includes the components necessary to drive the display 201 (e.g., frame buffers, digital analog converters (DACs), etc.). The display 201 is coupled to the DGS 110 via, for example, a display adapter card line 202 (e.g., analog video line, digital video line, etc.).

One of the advantages provided by the DGS 110 embodiment of FIG. 2 is that the calculated video data (eg, the frame of the 3D video) that was originally transmitted to the computer system 100 on the bus bar 115 can be directly transmitted to the display. 201. This will reduce the bandwidth requirement set on the bus bar 115.

Figure 3 illustrates a DGS 310 in accordance with an embodiment of the present invention in which the DGS 310 is configured to be directly coupled to a computer system 300 using the display 201 (e.g., different from being connected to the DGS in the embodiment of Figure 2). The DGS 310 embodiment is configured to transmit the calculated video data back to the computer system 300 using the available bandwidth of the bus 115. The DGS 310 operates in conjunction with components of the computer system 300 (e.g., CPU 301, system memory 302, bridge 320, and computer system GPU 330) to present the calculated video data to the display 201. Thus in this case, resources of the computer system GPU 330 (e.g., frame buffers, DACs, etc.) are used to drive the display 201.

One advantage provided by the DGS embodiment of Figure 3 is that the available resources of a typical desktop or notebook computer system can be used to drive the display 201. This allows the DGS 310 to be more easily connected and used by a typical computer system. For example, when a performance advantage of a powerful 3D calculus system is required, the DGS 310 can be immediately plugged into the computer system 300 and immediately begin to drive the display 201, while forcing a user to unplug the display 201 from the computer system 300. And reconnecting the display to the DGS 310 is different.

Figure 4 illustrates some of the components of computer system 400 and a busbar 415 in accordance with one embodiment of the present invention. In this embodiment, the bus bar 415 is a PCI Express bus bar. The PCI Express bus 415 connects a DGS 410 to one of the PCI Express bridges 420 of the computer system 400. The PCI Express Bridge 420 provides the CPU 401, system memory 402, and the personal device (e.g., disk drive 421, DVD player 422, etc.).

The use of a PCI Express bus 415 provides a number of advantages. For example, PCI Express includes a sequence of bus standards that serialize data for more efficient transmission than older parallel bus standards (eg, AGP, etc.). Furthermore, the PCI Express standard defines an enhanced bandwidth transmission mode whereby a number of "lanes" can be combined to scale the data transmission bandwidth. For example, a typical PCI Express bus that connects a graphics subsystem to system memory is designated as a "16-channel" bus, thereby connecting 16 serial PCI Express data channels to provide a single-channel PCI Express bus. 16 times the data transmission bandwidth. If more bandwidth is needed, an additional number of PCI Express lanes can be used to implement the bus 415.

The PCI Express bus 415 can be much longer than the earlier parallel bus. For example, the length of the prior art AGP busbar cannot be greater than a few millimeters without the risk of data distortion and data corruption. This effectively forces the GPU to be placed or plugged directly into the motherboard of the computer system. Conversely, a PCI Express bus bar can be much longer than one meter in length, thus allowing the DGS 410 to be completely removed from the rack of the computer system 400 (eg, placed a distance away).

Figure 5 illustrates some of the components of a computer system in accordance with one embodiment of the present invention. In the computer system 500 embodiment, a PCI Express North Bridge 424 and a PCI Express South Bridge 425 are used in place of a single bridge 420 of the computer system 400 of FIG. Computer system 500 illustrates a typical Northbridge/Southbridge configuration in which the Northbridge 424 provides a memory master/memory controller function to the system memory 402, and the Southbridge 425 provides data transmission bandwidth to the perimeter. Devices (e.g., disk drive 421, DVD player 422, etc.).

Figure 6 illustrates a diagram depicting the manner in which a DGS is coupled to a computer system via PCI Express connectors 601 and 602 in accordance with an embodiment of the present invention. The PCI Express standard provides an instant plug-in capability so that devices can be connected in operation and removed from a PCI Express bus. This allows the DGS 410 to be inserted into the computer system 400 almost at will. For example, when high performance 3D calculus is required (eg, when a high precision instant 3D calculus application is required), the DGS 410 can be easily inserted to provide the desired performance. Moreover, as previously discussed, a PCI Express bus line 415 can be more than one meter in length, thereby allowing the DGS 410 to be completely removed from the rack of the computer system 500.

Figure 7 illustrates the internal components of a DGS 710 in accordance with one embodiment of the present invention. As described in Figure 7, the DGS 710 includes a rack that is separate from the rack of the computer system. The rack includes a DGS bridge 720 to connect to the PCI Express bus 415, one or more GPUs 730, a power supply 721, a thermal management system 722, and a volume management system 723.

As shown in FIG. 7, the DGS 710 embodiment includes one or more GPUs for executing graphics instructions from a combined computer system, such as computer system 500. As previously mentioned, the graphics command is received from the computer system via the PCI Express bus 415.

The independent power supply 721 is for providing power to the DGS component independently of a power supply of a computer system. Thus, future power supply requirements for increased GPU performance may be independent of any external limitations of any industry standard computer system configuration (eg, ATX motherboard size specifications, BTX motherboard size specifications, etc.).

The thermal management system 722 is for providing a source of cooling independent of the cooling configuration of a computer system. Therefore, the increased cooling requirements for future GPU performance may not be subject to any external constraints (such as BTX cooling standards, etc.). For example, the thermal management system 722 can include the cooling fan, heat conduit mechanism, liquid cooling mechanism, and the like.

Similarly, the volume management system 723 is used to provide a volume management mechanism/algorithm that is independent of the cooling, power, or operational limitations of a computer system. For example, a special sound absorbing material can be used in the frame of the DGS 710. Similarly, a special mode of operation can be used to control the speed/operation of the power supply 721 and thermal management system 722 of the DGS 710 to reduce noise.

Figure 8 illustrates an exemplary configuration of internal components of DGS 710 in accordance with an embodiment of the present invention. As shown in FIG. 8, the DGS 710 includes a cooling fan (HSF) 801 and a power supply fan (PSF) 802 to provide thermal dissipation of the GPU (s) 730 and the power supply 721. In the embodiment of Fig. 8, these components are controlled by a volume management system 723. In the embodiment of Figure 8, a separate power connection 803 (e.g., an AC power source) is shown coupled to the power supply 721 and displays a dedicated connection to the display.

Figure 9 illustrates a scalable DGS 910 in accordance with an embodiment of the present invention. As shown in FIG. 9, the DGS 910 includes the DGS bridge 720, which functions to connect a plurality of GPUs with the PCI Express bus 415. The figure shows a number of GPUs connected to the bridge 720. This is shown in the figure as GPU 1 901, GPU 2 902, and GPU X 904. Each GPU (GPU 1 to GPU X) has an additional bus connection (shown as a link 911-914) that is otherwise connected to the DGS bridge 720.

The DGS 910 embodiment shows a scaling feature of a DGS in accordance with an embodiment of the present invention. The function of the DGS bridge 720 is that the connection 911-914 cooperatively shares the data transmission bandwidth of the PCI Express bus. This sharing is used to allow the GPUs to cooperatively execute 3D graphics instructions from a combined computer system, such as computer system 500.

As previously mentioned, the available data transmission bandwidth is accompanied by a multi-channel PCI Express bus connection (e.g., a 16-channel PCI Express bus) to remove the performance frequency that exists in conventional technology type parallel bus connections. This available data transmission bandwidth allows the performance of a graphics subsystem to be scaled quickly. Embodiments of the present invention utilize this increased data transmission bandwidth by using GPUs in a collaborative computing array.

The graphics processing workload can be allocated between available GPUs so that the workload can be executed in parallel. This collaborative execution enables the graphics subsystem to perform quickly. Moreover, due to the features of a DGS system in accordance with embodiments of the present invention, the boost is not limited by the limitations of any combined computer system (e.g., power limitations, thermal limitations, etc.).

For example, since the DGS system 910 can include its own dedicated power supply (eg, power supply 721 of FIG. 8), and since the DGS system 910 can include its own thermal management system (eg, 8th The HSF 801 and PSF 802 of the figure, the performance of the overall graphics subsystem is free to evolve rapidly as technology changes. Furthermore, the removal of this computer system related restriction allows for the inclusion of multiple GPUs as shown in Figure 9, which provides a rapid increase in graphics subsystem performance.

In one embodiment, the DGS bridge 720 functions to distribute the PCI Express bus 415 to each GPU in a round robin manner. For example, the overall bandwidth of a 16-lane PCI Express bus 415 can be assigned to the GPUs in a round-robin fashion when the GPUs execute and complete portions of the overall graphics execution workload. Alternatively, in an embodiment, the bridge 720 can implement an arbitration mechanism whereby the bus 415 can be assigned to the GPUs according to its needs.

Figure 10 shows a diagram illustrating the improvement in computational efficiency when adding an additional GPUs to a DGS 910 in accordance with an embodiment of the present invention. As shown in Figure 10, the addition of additional GPUs results in a rapid increase in the computing power of the DGS 910. For example, the transition from a single GPU DGS to a dual GPU DGS resulted in a nearly 100% improvement in calculus. It should be noted that this boosting calculus capability is not 100% due to the need for some additional overhead to ensure proper coordinated execution of the graphics processing workload.

Figure 11 illustrates an AGP-based patching card for mounting a GPU 1101 in accordance with an embodiment of the present invention. The GPU 1101 includes a graphics processor 1105, a graphics memory 1106, and an AGP edge connection 1107. The GPU 1101 therefore includes a typical GPU that can be taken in a typical retail market. Such a GPU can be used off-the-shelf by a DGS system in accordance with an embodiment of the present invention. The DGS rack can include an AGP edge connection slot to accept the edge connection to the GPU 1101.

For example, a user can purchase the GPU 1101 instead of an old GPU. This upgrade can be accomplished by simply removing the legacy GPU from the DGS and simply plugging in the new GPU 1101. This removal or replacement can be accomplished by requiring the user to open or otherwise enter the rack of the computer system.

Similarly, for example, the user can purchase the GPU 1101 to supplement and remove the existing GPU installed in the DGS. This allows the user to immediately improve the performance of the user's graphics subsystem by using the aforementioned DGS cooperative graphics instruction execution features.

Figure 12 illustrates a PCI Express-based adapter card for mounting GPU 1201 in accordance with an embodiment of the present invention. The GPU 1201 is substantially similar to the GPU 1101. The GPU 1201 includes a graphics processor 1205, a graphics memory 1206, and a PCI Express connection 1207 that is different from the AGP edge connection 1107 of FIG. In addition, the GPU 1201 has one or more separate power connectors 1208 to directly connect power to the GPU 1201. This power connector 1208 has become increasingly common in current high performance GPUs. The DGS rack can include a PCI Express connection slot to accept the PCI Express connection GPU 1201 and can also include appropriate slots for the power connector 1208.

It should be noted that in an embodiment, a DGS can accept different types of plug-in GPUs. For example, the DGS rack can include provisions for accepting AGP-based GPUs and/or PCI Express-based GPUs.

Figure 13 illustrates a block diagram depicting the internal components of a multi-GPU (graphics processor) graphics system 1300 in accordance with one embodiment of the present invention. The multi-GPU graphics system includes a plurality of GPUs 901-904 for executing graphics instructions for a computer system. A GPU output multiplexer 1302 and a control unit including a frame sync master component 1301 and individual clock control units 1311-1313 are coupled to the GPUs 901-904. The multi-GPU graphics system 1300 can be used to implement a collaborative GPU execution process of a DGS.

In the present invention, the frame synchronization master component 1301 and the individual clock control units 1311-1313 are provided to control the GPUs 901-904 and the output multiplexer 1302, and thus the GPUs 901-904 cooperatively execute the computer system. Graphical instructions. The function of the clock control units 1311-1313 is to activate or deactivate individual GPUs 901-904. The function of the frame synchronization master component 1301 is to synchronize the calculated 3D graphics frames established by the individual GPUs 901-904. The output multiplexer 1302 combines the outputs of the individual GPUs 901-904 to establish a final GPU output stream 1330. The memory master component 1320 (e.g., bridge 420 of FIG. 4) controls access to the memory 1321 (e.g., system memory 402 of FIG. 4).

Accordingly, the multi-GPU graphics system 1300 illustrates an exemplary configuration in which a coordinated execution between multiple GPUs (e.g., GPUs 901-904) can be implemented and controlled in accordance with an embodiment of the present invention. It should be noted that while system 1300 illustrates an exemplary configuration, other configurations of precision coordinated execution between multiple GPUs are also possible.

Figure 14 illustrates a diagram depicting the operational range available for a multi-GPU graphics system 1300 in accordance with an embodiment of the present invention. The graphics system 1300 can be used in both low power mode and high power mode. For example, when implementing a low power mode, the controller unit turns off one or more of the GPUs 901-904. This saves power but also reduces the peak performance of the graphics system 1300. When implementing a high power mode, the controller unit activates additional GPUs to provide additional computational efficiency. This increase in performance peaks, however, also increases the power consumption.

This ability to implement different power and performance modes of operation allows a GPU graphics system 1300 to operate at several different power/performance locations. This feature is graphically depicted in FIG. 14 as the operating envelope 1401 of the GPU graphics system 1300, which is much larger than the envelope 1402 of a list of prior art GPU architectures.

Figure 15 illustrates a diagram depicting the manner in which each of the GPUs 901-904 executes the individual graphics instruction workload. For example, in one embodiment, a sequence of computational workloads is assigned to the GPUs 901-904 (e.g., frame 1, frame 2 up to frame N+N). The sequence frame can be allocated to the GPUs 901-904 in a time-interleaved manner, such that the frame can be substantially executed in parallel and can be combined by the output multiplexer into a snooze for interrupting the GPU output stream, such as Line segment 1501 is shown. In this manner, the GPUs execute individual graphics instruction workloads for each of the GPUs 901-904 in parallel.

It should be noted that while the multi-GPU graphics system 1300 can perform functions on a DGS connected to one of the computer systems, the multi-GPU graphics system 1300 can also be directly built into a rack of a computer system (eg, directly incorporated into a table) In the upper computer system).

In one embodiment, each of the GPUs 901-904 has its own clock, and thus the clock distribution and the GPU-to-GPU skew between the wafers or systems are not as severe as other designs. This can greatly reduce the cost and complexity of the wafer or board configuration. Each GPU is responsible for establishing a portion of the output stream 1330 (e.g., frame, frame, etc.) with its neighboring GPUs. In one embodiment, the GPUs 901-904 are generally executed at a frame rate that is slightly faster than an application (eg, a 3D calculus application) to eliminate frame discontinuity of the composite image sequence (frame stuttering). ). As shown in Figure 13, the output multiplexer 1302 combines these frames to establish the final N frame/second. This greatly expands the fill rate and frame rate performance of the system 1300 without the need to redesign the GPU core or use "bleeding edge" semiconductor processes and ultra-high frequencies. In one embodiment, the GPUs array share memory, so the overall system cost is much lower than other structures. The GPU-to-GPU time difference, frame allocation, and output multiplexer 1302 are managed by the frame synchronization master component 1301.

In this manner, the system 1300 architecture provides several benefits. For example, for an AC-tethered ultra-high performance graphics implementation such as workstation and desktop applications, the GPU core can be reused or a super size of the on-chip chip solution can be used (super- Scaled) On-chip design can achieve ultra-high performance. Similarly, the same basic re-targetable GPU building component provides graphics performance for ultra-low power graphics solutions such as portable applications such as mobile phones, personal digital assistants, and mobile computers. . This feature will yield a market timeliness and NRE (non-repetitive engineering) cost advantage when building GPU generation products for extreme performance and extreme mobile graphics solutions. The greatly reduced clock provides comparable fill rates and frame rates, thus establishing performance but with much lower power consumption. For example, as previously discussed, the individual GPU-clock-per-GPU feature allows unused GPUs to be dynamically enabled or disabled depending on the designation of an application. A similar 2D interface and DVD or mpeg playback would only require activating a portion of the overall system 1300, thereby greatly reducing power consumption.

It should be noted that even though the graphics system 1300 has been described in the context of a DGS rack-based system, the graphics system 1300 architecture can be implemented in a wide range of computer system platforms, including, for example, desktop computers, workstations. , mobile PCs, mobile phones, personal digital assistants, chipsets, and more.

Referring now to Figures 16 through 21, there are shown a plurality of pictures of a DGS in accordance with an embodiment of the present invention. Figure 16 shows a side view of a DGS in accordance with one embodiment of the present invention. Figure 17 shows a front view of the DGS. Figure 18 shows a picture of the DGS removing the frame cover. This image shows two internal GPU cards connected to the DGS rack. Figure 19 shows a picture of the DGS rack cover being closed. Figure 20 shows a DGS image connected to a notebook system via a PCI Express line. Figure 21 shows a picture of the display that the DGS drives the notebook system.

Broadly speaking, this document explains the following things. A separate graphics system (DGS) is disclosed herein for executing a 3D graphics command of a computer system, a DGS unit, and a scalable DGS. The split graphics system includes a GPU for executing 3D graphics instructions and a DGS system rack for housing the GPU. A sequence of busbar connectors is coupled to the GPU and the DGS rack. The sequence bus bar connector is for removably connecting the DGS and the GPU to the computer system. The GPU of the DGS accesses the computer system through the serial bus connector to execute 3D graphics commands of the computer system.

Broadly speaking, this document discloses a scalable scaled graphics system (DGS). The DGS includes a sequence of bus bars for connecting a plurality of GPUs to a bus. A sequence of bus bar connectors is connected to the sequence bus bar bridge. A system rack is coupled to the sequence bus bridge and the serial bus connector and is configured to house the GPUs. The sequence bus bar connector is for removably connecting to a computer system. The GPUs access the computer system through the serial bus bridge and the serial bus connector to cooperatively execute 3D graphics commands of the computer system.

Broadly speaking, this document reveals a DGS (Separate Graphics System) unit. The DGS unit includes a system rack for housing a GPU for executing graphics instructions and a GPU mounting unit coupled to the system chassis and for accepting a GPU. a sequence of busbar connectors connected to the rack and connected to the GPU mounting unit, wherein the serial busbar connector is configured to removably connect the GPU to a computer system to enable the GPU to pass through the sequence bus The connector accesses the computer system and executes 3D graphics commands of the computer system. A power supply is coupled to the system rack to provide power independent of the computer system to the GPU.

Broadly speaking, this document discloses a separate graphics system (DGS) for executing 3D graphics instructions of a computer system. The split graphics system includes a GPU for executing 3D graphics instructions and a DGS system chassis for housing the GPU. A sequence of busbar connectors is coupled to the GPU and the DGS rack. The sequence bus bar connector is for removably connecting the DGS and the GPU to the computer system. The GPU of the DGS accesses the computer system through the serial bus connector and executes 3D graphics commands of the computer system. ,

The foregoing description of the specific embodiments of the invention has in the The illustrations are not intended to be exhaustive or to limit the invention to the precise form of the disclosure, and it is obvious that many modifications and variations are possible. The embodiment was chosen and described in order to best explain the embodiment of the invention, The scope of the invention should be limited only by the scope of the appended claims and their equivalents.

100,300,400,500. . . computer system

101,301,401. . . Central processing unit (CPU)

102,302. . . System memory

110,310,410,710,910. . . Separate Graphics System (DGS)

115,415. . . Busbar

120,320,420,720. . . Bridge

201. . . monitor

202. . . Display adapter line

330,730,901,902,904,1101,1105,1201,1205. . . Graphics processor (GPU)

421. . . Disk drive

422. . . DVD player

424. . . North Bridge

425. . . South Bridge

601,602. . . Connector

721. . . Power Supplier

722. . . Thermal management system

723. . . Sound management system

801. . . Cooling fan (HSF)

802. . . Power supply fan (PSF)

803. . . power supply

911-914. . . connection

1106,1206. . . Graphics memory

1107. . . AGP edge connection

1207. . . PCI Express connection

1208. . . Power connector

1300. . . Multi-GPU graphics system

1301. . . Frame synchronization master

1311-1313. . . Clock control unit

1320. . . Memory master

1321. . . Memory

1330. . . GPU output stream

1401,1402. . . Operating envelope

1501. . . Line segment

The invention is illustrated by way of example, and not limitation, in the FIG

Figure 1 illustrates a computer system in accordance with an embodiment of the present invention.

Figure 2 illustrates a DGS in accordance with an embodiment of the present invention in which the DGS is coupled to drive a display.

Figure 3 illustrates a DGS in accordance with an embodiment of the present invention in which the DGS is configured to utilize a display directly connected to a computer system.

Figure 4 illustrates some of the components of a computer system and a busbar in accordance with one embodiment of the present invention.

Figure 5 illustrates some of the components of a computer system in accordance with one embodiment of the present invention.

Figure 6 illustrates a diagram depicting the manner in which a DGS is coupled to a computer system via a PCI Express connector in accordance with an embodiment of the present invention.

Figure 7 illustrates the internal components of a DGS in accordance with one embodiment of the present invention.

Figure 8 illustrates an exemplary configuration of internal components of a DGS in accordance with an embodiment of the present invention.

Figure 9 illustrates a scalable DGS in accordance with an embodiment of the present invention.

Figure 10 shows a diagram illustrating the improvement in computational efficiency when additional GPUs are added to a DGS in accordance with an embodiment of the present invention.

Figure 11 illustrates an AGP-based card-mounted GPU in accordance with an embodiment of the present invention.

Figure 12 illustrates a PCI Express based card-mounted GPU in accordance with an embodiment of the present invention.

Figure 13 illustrates a block diagram depicting the internal components of a multi-GPU (graphics processor unit) graphics system in accordance with one embodiment of the present invention.

Figure 14 shows a diagram depicting the operational range that can be achieved by a multi-GPU graphics system in accordance with one aspect of the present invention.

Figure 15 shows a diagram depicting how each GPU executes the individual graphics instruction workload.

Figure 16 shows a side view of a DGS in accordance with one embodiment of the present invention.

Figure 17 shows a front view of a DGS in accordance with one embodiment of the present invention.

Figure 18 shows the appearance of a DGS that removes the frame cover in accordance with one embodiment of the present invention.

Figure 19 shows an appearance of the closed mid-rack cover of the DGS in accordance with an embodiment of the present invention.

Figure 20 illustrates an appearance of a DGS connected to a notebook computer system via a PCI Express line in accordance with an embodiment of the present invention.

Figure 21 illustrates an appearance of a DGS that drives a display of the notebook computer system in accordance with an embodiment of the present invention.

101. . . CPU

100. . . computer system

102. . . System memory

120. . . Bridge

110. . . Separate graphics system

Claims (66)

A separate graphics system includes: a graphics processing unit (GPU) for executing 3D graphics instructions; a system rack for housing the GPU, wherein the system rack includes a power supply for supplying power Having the GPU independent of an external computer system; and a sequence of busbar connectors coupled to the GPU and the system rack, wherein the serial busbar connector is configured to removably connect the GPU to the accommodating An external computer system in an external computer system rack, and wherein the GPU accesses the external computer system through the serial bus connector to execute the 3D graphics command for the external computer system, and the 3D graphics command The results of the execution are passed back to the external computer system, and wherein the GPU can drive a display coupled to the external computer system independent of a computer system GPU. The split graphics system of claim 1, wherein the serial bus connector is a PCI Express connector. The split graphics system of claim 1, wherein the GPU is removably coupled to the sequence bus connector and the system rack. A separate graphic system as described in claim 1, wherein the The GPU is a plug-in GPU that is coupled to the serial bus connector. The split graphics system of claim 1, wherein the GPU is configured to execute the 3D graphics instructions from the external computer system to drive a display coupled to the GPU. The separate graphics system of claim 1, further comprising: a plurality of GPUs coupled to the system rack and the serial bus connector, and configured to cooperatively execute from the external computer system The 3D graphics instructions. The split graphics system of claim 1, further comprising: a thermal management system coupled to the system rack to cool the GPU independent of the external computer system. The separate graphics system of claim 1, wherein the GPU can be dynamically turned on or off according to an application specification. The split graphics system of claim 1, wherein the GPU can drive a display that is directly coupled to a computer system GPU. A method for a separate graphics system, comprising: executing a 3D graphics instruction using a GPU; The GPU is housed in a system rack, wherein the system rack includes a power supply for supplying power to the GPU independent of an external computer system; by using the GPU through a serial bus connector And accessing the external computer system to execute the 3D graphics command for the external computer system, wherein the serial bus connector is coupled to the GPU and the system chassis, and wherein the serial bus connector is Removably connecting the GPU to the external computer system; and transmitting the result of execution of the 3D graphics instruction back to the external computer system, wherein the GPU is drivably coupled to the external computer system independent of a computer system GPU a monitor. The method of claim 10, wherein the serial bus connector is a PCI Express connector. The method of claim 10, wherein the GPU is removably coupled to the sequence bus connector and the system rack. The method of claim 10, wherein the GPU is a plug-in GPU coupled to the serial bus connector. The method of claim 10, wherein the GPU system The 3D graphics instructions from the external computer system are executed to drive a display coupled to the GPU. The method of claim 10, further comprising: cooperatively executing 3D graphics instructions from the external computer system by using a plurality of GPUs coupled to the system chassis and the serial bus connector. The method of claim 10, further comprising: cooling the GPU independent of the external computer system by using a thermal management system coupled to the system rack. A computer system configured for a separate graphics computing system, comprising: a computer system in a first rack; a GPU for executing 3D graphics commands; and a second rack housing the GPU The second rack includes a power supply for supplying power to the GPU independent of the computer system, and wherein the second rack includes a first GPU slot and a second GPU slot, and the second rack a GPU is coupled to the first GPU slot; and a sequence of busbar connectors coupled to the GPU and the second chassis, wherein the serial busbar connector is for removably connecting The GPU to the computer system, and wherein the GPU accesses the computer system through the serial bus connector to execute the 3D graphics command for the computer system, and the result of execution of the 3D graphics command is transmitted back to the computer A system, and wherein the GPU can drive a display coupled to the computer system independent of a computer system GPU. The system of claim 17 wherein the GPU is to execute the 3D graphics instructions from the computer system to drive a display coupled to the GPU. The system of claim 17, further comprising: a plurality of GPUs coupled to the second chassis and the serial bus connector, and cooperatively executing the 3D graphics instructions from the computer system. The system of claim 17, wherein the serial bus connector allows the GPU to be dynamically coupled to the computer system. The system of claim 17, wherein the GPU is a multi-GPU add-on graphics card. The system of claim 21, wherein the second GPU slot is operable to receive an additional GPU, wherein the additional GPU is more than one GPU attached graphics card. A separate graphics system (DGS) unit includes: a system rack for accommodating a GPU for executing 3D graphics instructions; a GPU mounting unit coupled to the system rack and Removably receiving the GPU; a sequence of busbar connectors coupled to the chassis and coupled to the GPU mounting unit, wherein the serial busbar connector is configured to removably connect the GPU To a computer system, such that the GPU accesses the computer system through the serial bus connector and executes the 3D graphics command for the computer system, and wherein the serial bus bar connector is operable to hot plug the GPU to The computer system, and wherein the serial bus bar connector is operable to enable the GPU to communicate via a serial bus of the computer system; and a power supply coupled to the system rack to supply power to the computer independent of the computer The GPU of the system. The DGS unit of claim 23, wherein the system rack includes a removable housing for containing the GPU and enabling access to the GPU. For example, the DGS unit mentioned in the 23rd patent application scope is more coupled. A heat dissipation unit coupled to the frame is used to cool the GPU, wherein the cooling is provided independently of the computer system. The DGS unit of claim 23, wherein the serial bus connector is a PCI Express connector for connecting to the computer system via a PCI Express line. The DGS unit of claim 23, wherein the GPU mounting unit is to be removably coupled to the GPU and to connect the GPU to the serial bus connector and the system rack. The DGS unit of claim 27, wherein the GPU installation unit is configured to accept an AGP-based card mounted GPU. The DGS unit of claim 27, wherein the GPU mounting unit is configured to accept a PCI-express based card mounted GPU. The DGS unit of claim 27, wherein the GPU mounting unit is configured to hot plug a plug-in GPU. The DGS unit of claim 23, wherein the GPU Used to execute the 3D graphics instructions from the computer system to drive a display coupled to one of the computer systems. The DGS unit of claim 23, further comprising: a display connector for coupling to a display and enabling the GPU to execute the 3D graphics command from the computer system to drive the display. The DGS unit of claim 23, wherein the GPU installation unit is configured to receive a plurality of GPUs and couple the GPU to the serial bus connector to enable the GPU to cooperatively execute from the computer system The 3D graphics instructions. A separate graphics system (DGS) housing includes: a hinged system rack having an upper half and a lower half for housing a GPU for executing 3D graphics commands; a GPU connection And coupled to the system rack and for removably receiving the GPU; a sequence of busbar connectors coupled to the rack and coupled to the GPU connector, wherein the serial busbar connector is Removably connecting the GPU to a computer system such that the GPU accesses the computer system through the serial bus connector and performs The 3D graphics command of the computer system, and wherein the sequence bus bar connector is operable to hot-plug the GPU to the computer system, and wherein the sequence bus bar connector is operative to enable the GPU to pass the One of the computer systems is in communication with the serial bus; a power supply coupled to the system rack to supply power to the GPU independent of the computer system; and a heat dissipation unit coupled to the rack to cool the GPU, Wherein the cooling is independent of the computer system. The DGS enclosure of claim 34, wherein the system rack includes a removable housing for containing the GPU and enabling access to the GPU. The DGS cover of claim 34, wherein the serial bus connector is a PCI Express connector for connecting to the computer system via a PCI Express line. A DGS enclosure as claimed in claim 34, wherein the GPU mounting unit is for removably coupling to the GPU and connecting the GPU to the serial busbar connector and the system rack. The DGS cover of claim 37, wherein the GPU mounting unit is for hot plugging a card mounted GPU. The DGS cover of claim 34, wherein the GPU is configured to execute the 3D graphics command from the computer system to drive a display coupled to the computer system. The DGS cover of claim 34, further comprising: a display connector for coupling to a display and enabling the GPU to execute the 3D graphics command from the computer system to drive the display. The DGS enclosure of claim 34, wherein the GPU installation unit is configured to receive a plurality of GPUs and couple the GPU to the serial busbar connector to enable the GPU to cooperatively execute from the computer system The 3D graphics instructions. A separate graphics system (DGS) unit includes: a system rack for accommodating a GPU for executing 3D graphics instructions; a GPU connector coupled to the system rack and for removable Receiving the GPU; a PCI Express connector coupled to the chassis and coupled to the GPU connector, wherein the PCI Express connector is configured to removably connect the GPU to a computer system to enable the GPU Accessing the computer system through the serial bus connector and executing the 3D graphics command for the computer system, and wherein the PCI Express connector is operable to hot plug the GPU to the computer system, and wherein the PCI Express connection The device is operable to enable the GPU to communicate via a PCI Express bus of the computer system; a power supply coupled to the system rack to supply power to the GPU independent of the computer system; a heat dissipation unit coupled Up to the rack to cool the GPU, wherein the cooling is provided independently of the computer system; and a GPU mounting unit for receiving a plurality of GPUs and coupling the GPU to the PCI Express connector to enable the GPU to cooperate The 3D graphics instructions from the computer system are executed. The DGS unit of claim 42, further comprising an acoustic management system for controlling the heat dissipation unit and the power supply to limit noise generated by the DGS unit. A scalable separate graphics system comprising: a sequence of bus bridges for coupling a plurality of GPUs to a sequence of busses; a sequence of busbar connectors coupled to the sequence of bus bars; a system rack coupled to the sequence bus bridge and the a serial bus connector for accommodating the GPU, wherein the serial bus connector is for removably connecting to a computer system, and wherein the GPU is connected to the serial bus and the serial bus Accessing the computer system to cooperatively execute 3D graphics instructions from the computer system, and wherein the GPU is operative to perform 3D graphics instructions in cooperation with a GPU of the computer system, and wherein the system is hosted by the system The execution result of the 3D graphics instruction executed by the GPU in the shelf is transmitted back to the computer system. The scalable horizontal graphics system of claim 44, wherein the serial bus bridge is connected to the computer system through a PCI Express bus and connected to the plurality of PCI Express bus bars. Each of the GPUs to the computer system. The scalable split graphics system of claim 45, wherein the PCI Express bus between the serial bus bridge and the computer system is at least one 16-channel PCI Express bus connection. . The scalable split graphics system of claim 45, wherein the serial bus bridge is coupled to each of the plurality of GPUs via at least one 16-channel PCI Express bus connection. The scalable horizontal graphics system of claim 44, wherein the serial bus bridge is configured to couple at least one new GPU and at least one of the coupled bus bridges The GPU enables one of the computer systems to improve in 3D calculus performance, wherein the new GPU and the existing GPU cooperatively execute graphics commands from the computer system. The scalable detachable graphics system of claim 48, wherein the new GPU and the existing GPU are card-mounted GPUs. A scalable, discrete graphics system as described in claim 44, wherein the GPU is operative to execute the 3D graphics instructions for the computer system to drive a display coupled to the computer system. The scalable and discrete graphics system of claim 44, further comprising: a power supply coupled to the system chassis to provide power to the GPU independent of the computer system. The scalable split graphics system of claim 44, wherein the scalable split graphics system is coupled to a handheld device. A method for a scalable split graphics system, comprising: accessing a plurality of GPUs through a sequence of busbars by using a sequence of busbars; accessing a sequence of busbars coupled to the sequence of busbar bridges a connector; and cooperatively executing 3D graphics instructions from a computer system, wherein the GPU accesses the computer system through the serial bus bridge and the serial bus connector, and wherein the serial bus connector is used Removably coupled to the computer system, wherein the GPU is housed in a system rack and the GPU is operative to perform 3D graphics instructions in cooperation with a GPU of the computer system, and wherein the 3D graphics instructions The results of the execution are passed back to the computer system. The method of claim 53, wherein the serial bus bridge is connected to the computer system through a PCI Express bus and connected to each of the plurality of GPUs through the PCI Express bus. To the computer system. The method of claim 54, wherein the PCI Express bus between the sequence bus bridge and the computer system is connected to at least one 16-channel PCI Express bus. The method of claim 54, wherein the sequence is confluent The row bridge is coupled to each of the plurality of GPUs via at least one 16 channel PCI Express bus connection. The scaled split graphics system of claim 53, wherein the serial bus bridge is configured to couple at least one new GPU and at least one existing GPU coupled to the serial bus bridge And enabling one of the computer systems to improve the 3D calculus performance, wherein the new GPU and the existing GPU cooperatively execute graphics commands from the computer system. The method of claim 57, wherein the new GPU and the existing GPU are card-mounted GPUs. The method of claim 53, wherein the GPU is configured to execute the 3D graphics instructions for the computer system to drive a display coupled to the computer system. The method of claim 53, further comprising: providing power to the GPU independent of the computer system by using a power supply coupled to the system rack. A system for implementing scalable scaleable graphics, comprising: a computer system; a PCI Express bridge for coupling a plurality of GPUs to a PCI Express bus; a PCI Express connector coupled to the PCI Express bridge; and a system rack coupled to the PCI Express bridge and the PCI Express a connector for accommodating the GPU, wherein the PCI Express connector is for removably connecting to the computer system, and wherein the GPU accesses the computer through the PCI Express bridge and the PCI Express connector The system cooperatively executes 3D graphics instructions from the computer system, and wherein the results of execution of the 3D graphics instructions executed by the GPU housed in the system rack are transmitted back to the computer system. The system of claim 61, wherein the PCI Express bridge is configured to connect to the computer system through a PCI Express bus and connect each of the plurality of GPUs through the PCI Express bus. To the computer system. The system of claim 61, wherein the PCI Express bridge is configured to enable the computer system by coupling at least one new GPU and at least one existing GPU coupled to the PCI Express bridge. A 3D calculus performance upward scaling, wherein the new GPU and the existing GPU are cooperatively executed from the computer system Graphical instructions. The system of claim 61, further comprising: a power supply coupled to the system rack to provide power to the GPU independent of the computer system. The system of claim 61, wherein the PCI Express bridge allows the GPU to be dynamically coupled to the computer system. The system of claim 61, wherein the GPU is implemented as a multi-GPU graphics card.