TWI400364B - 形成積體電路之感應器結構的方法及積體電路之感應器結構 - Google Patents
形成積體電路之感應器結構的方法及積體電路之感應器結構 Download PDFInfo
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Description
本發明係關於感應器結構,特別是關於形成積體電路之感應器結構。
可將磁性材料用來製造電感及變壓器裝置等的微電子裝置。電感及變壓器結構可被用於諸如電壓轉換器、晶片內建及構裝內建電壓轉換器、射頻高頻電路、雷達應用、及電磁干擾(EMI)雜訊降低電路等的微電子電路。為了得到在諸如高頻工作時的最大電感值,應將磁通量耗損最小化。
本發明說明了形成微電子裝置之方法及相關聯的結構。那些方法可包含下列步驟:在一基材上形成一磁性材料,其中該磁性材料包含錸、鈷、鐵、及磷;以及在低於大約攝氏330度的一溫度下將該磁性材料退火,其中該被退火的磁性材料之矯頑力低於大約1厄斯特。
在下文的詳細說明中,將參照以圖示出可實施本發明的特定實施例之各附圖。將以使熟悉此項技術者足以實施本發明的細節說明這些實施例。我們當可了解:本發明的各實施例雖然是不同的,但不必然是互斥的。例如,可在不脫離本發明的精神及範圍下,將本發明中參照一實施例而說明的一特定的特徵、結構、或特性實施於其他實施例中。此外,我們當可了解:可在不脫離本發明的精神及範圍下,修改所揭示的每一實施例內之個別元件的位置或配置。因此,不應以限制之方式理解下文中之詳細說明,且只由被適當詮釋的最後之申請專利範圍以及該等申請專利範圍應享有之完整等效物範圍界定本發明之範圍。在所有該等數個圖式中,相似的代號將參照到相同的或類似的功能。
現在將說明用來形成一微電子結構之方法及相關聯的結構。那些方法可包含下列步驟:在一基材上形成一磁性材料,其中該磁性材料包含錸、鈷、鐵、及磷;以及在低於大約攝氏330度的一溫度下將該磁性材料退火,其中該被退火的磁性材料之矯頑力低於大約1厄斯特。本發明之方法可製造諸如電感及變壓器結構等的微電子裝置,此類微電子裝置呈現低矯頑力,且可耐受高達大約攝氏330度的溫度,因而可提高裝置的性能、以及與互補金屬氧化物半導體(Complementary Metal Oxide Semiconductor;簡稱CMOS)處理溫度間之相容性。
第1a-1g圖示出用來形成諸如電感結構等的微電子結構的一方法之一實施例。第1a圖示出一基材100的一部分之一橫斷面圖。可由諸如(但不限於)矽、絕緣層上覆矽(silicon-on-insulator)、鍺、銻化銦(indium antimonide)、碲化鉛(lead telluride)、砷化銦(indium arsenide)、磷化銦(indiumphosphide)、砷化鎵(gallium arsenide)、銻化鎵(gallium antimonide)、或以上各材料的組合等的材料構成基材100。
基材100可進一步包含此項技術中習知的微電子封裝材料及結構。在一實施例中,基材100可包含一起構成一微處理器的電晶體及其他裝置。在一實施例中,基材100可包含在單一晶粒上一起構成多個微處理器核心之裝置。在一實施例中,該基材可包含其中包含多層金屬化層之CMOS裝置。
可在基材100上形成第一層的磁性材料102(第1b圖)。在一實施例中,磁性材料102可包含高頻非晶質(amorphous)磁性材料。在一實施例中,磁性材料102可包含鈷、錸、磷、及鐵。該第一層的磁性材料102可包含大約0.1微米至大約30微米的一厚度103。
可利用諸如兩個或更多個電流密度下之電鍍、反脈衝電鍍(pulse reverse electroplating)、及(或)脈衝電鍍(pulse electroplating)等的電沈積(electro-deposition)技術形成該第一層的磁性材料102。在一實施例中,可被用於電沈積製程的電鍍浴可包含諸如氯化鈷(cobalt chloride)等的鈷鹽,諸如亞磷酸(phosphorous acid)等的磷源、諸如過錸酸鉀(potassium perrhenate)或過錸酸鈉(sodium perrhenate)等的錸源、以及諸如磷酸(phosphoric acid)及碳酸鈷(cobalt carbonate)等的其他必要成分。在一實施例中,該亞磷酸可包含每公升大約30公克至每公升大約65公克之濃度,該磷酸可包含每公升大約50公克之濃度,該六水氯化鈷可包含每公升大約181公克之濃度,該碳酸鈷可包含每公升大約39.4公克之濃度,且該過錸酸鉀可包含每公升大約0.7公克之濃度。在一實施例中,該電鍍浴可包含六水硫酸鈷(CoSO4
‧6H2
O)及六水氯化鈷(CoCl2
‧6H2
O)中之至少一者。
在一實施例中,可先在諸如一20奈米厚的鈦層及接續的一0.1~0.2微米厚的銅晶種層(seed layer)或一0.3微米厚的鈷晶種層等的一晶種層(圖中未示出)之上產生一光阻材料的圖案,然後以該磁性材料102填滿露出的區域,而執行該電鍍製程。在一實施例中,可在諸如基材100等的一平坦表面上形成一0.1微米厚的銅晶種層。亦可使用無電鍍(electroless plating)製程在基材100上形成磁性材料102,其中可將硼加入化學劑中,因而不再需要一晶種層。
被電沈積之磁性材料102可呈現高電阻係數及低矯頑力。因此,磁性材料102可包含低渦流損失(eddy current loss)低磁滯損失(hysteresis loss)。在一實施例中,可利用簡單直流(direct Current;簡稱DC)電鍍之外的一方法實現低矯頑力,這是因為在某些例子中,平面直流電鍍薄膜可能呈現垂直非等向性(anisotropy),且因而呈現極低的磁導率(permeability)及高矯頑力值。
在一實施例中,可形成具有交替成分的一多層結構,而實現包含面內(in-plane)非等向性及低矯頑力之一磁性材料。可使用兩個電流密度下之反脈衝電鍍及(或)脈衝電鍍而產生該多層結構。第2a圖示出一反脈衝波形的一例子,該反脈衝波形包含一正向電流密度203、一反向電流密度205、一正向時間209、2次的關閉時間211、以及一反向時間207。該等特定的電流密度及脈衝時間將根據特定應用而變動。第1c圖示出於形成包含諸如鈷磷錸(CoPRe)等的一磁性材料(諸如磁性材料102)時的此種反脈衝電鍍製程之效果。
在正向時間209期間,可形成磁性材料102之一初始部分115。在反向時間207期間,可移除該被電鍍的磁性材料之一部分104,且該移除製程可留下一高磷濃度區106及一低磷濃度/百分率區108。形成交替的高磷濃度區106及低磷濃度區108之該製程可形成一多層結構110(第1e圖),且可重複該製程,直到可得到所需總厚度的磁性材料102為止。或者,可使用兩個或更多個電流密度下之脈衝電鍍製程以形成該高及低磷濃度層。在一實施例中,磁性材料102的總厚度可包含大約0.5微米至大約30微米。在一實施例中,可形成一第一奈米層的材料,然後可在該第一奈米層的材料上形成一第二奈米層的材料,其中該第一奈米層及該第二奈米層中之一奈米層之磷百分率大於該第一奈米層及該第二奈米層中之另一奈米層的磷的百分率。具有高磷含量之該奈米層可具有或可不具有高至足以使該材料不具有磁性之磷含量。
因此,一反脈衝電鍍製程可能導致包含一多層結構110的一磁性材料102之形成,其中該多層結構110包含交替的高磷濃度/百分率層及低磷濃度/百分率層。在一實施例中,高磷百分率層106可包含小於大約5奈米的一厚度,且低磷百分率層108可包含小於或等於40奈米的一厚度。在一實施例中,多層結構110可包含一多層結構110,且該高及低磷百分率層106、108可包含高及低磷百分率奈米層106、108。
諸如鐵磁性磁料(ferromagnetic material)等的磁性材料102可在一被施加的磁場去除之後仍保持對該磁場之記憶,此種現象被稱為磁滯。矯頑力是在對該材料的磁化強度(magnetization)已被驅動到飽和之後將該磁化強度將低到零所需的被施加磁場之強度。對於電感而言,最好是有小的矯頑力,以便將損失最小化,但是通常難以實現。第2b-2c圖示出磁性材料102的磁滯曲線(magnetic hysteresis loop),其中磁性材料102包含第2a圖中之CoPRe及第2b圖中之CoPReFe的成分。
如圖所示,分別用於CoPRe及CoPReFe成分的第2b圖中之難磁化軸(hard axis)(將被用於電感之軸)213a及第2c圖中之難磁化軸213b是線性的,且具有一最小矯頑力。這些磁性材料102之成分的矯頑力是大約0.1~0.3厄斯特,因而將磁滯損失最小化。此外,磁性材料102具有耐受高溫的能力,因而使該磁性材料適用於CMOS製程。例如,CoP薄膜(諸如Co75.8
P24.2
)可包含在室溫下的大於大約1.4厄斯特之矯頑力、以及在大約攝氏300度溫度下退火之後的大於大約13厄斯特之矯頑力。
藉由加入錸(例如,藉由形成包含Co78.9
P19.9
Re1.0
或Co79.2
P19.4
Re1.4
之成分),可減少矯頑力,且磁性材料102可耐受諸如高達大約攝氏330度之退火溫度等的高溫,而且同時將矯頑力保持在小於大約0.3厄斯特。在另一實施例中,本發明之磁性材料102根據特定應用而可包含小於大約1厄斯特之矯頑力。因此,本發明之磁性材料102適用於CMOS製程,例如,適於諸如配合作為介電材料的聚醯亞胺(polyimide)之使用而使用本發明之磁性材料102。
此外,在某些例子中,可將磁性材料102的鐵濃度最佳化,以便將飽和磁通量增加到高達大約2.0特斯拉(Tesla),因而適用於諸如電壓轉換器等的大電流應用。亦將鐵加入磁性材料102時,將進一步有利於增加磁性材料102之電阻係數。在一實施例中,錸的濃度可包含磁性材料102的大約0.1至5.0原子百分率(atomic percent)。在一實施例中,可將磷的百分率保持在大於大約14%,而將磁性材料102的矯頑力最佳化。在另一實施例中,磷的原子百分率可包含大約8%至大約25%,且錸的原子百分率可包含大約0.1%至大約5%。可根據特定應用而改變並最佳化錸、鈷、磷、及鐵的特定濃度。
在另一實施例中,可將磁性材料102內之磷的濃度最佳化,以便得到磁性材料102的所需電阻係數,因而將較高頻下的渦流損失最小化。第2d圖示出包含CoPReFe的磁性材料102的電阻係數215與磷的原子百分率217間之一關係圖形。第2d圖示出磷百分率介於大約10至大約16原子百分率(可根據成分而將該原子百分率最佳化)的電阻係數大約是150微歐姆-厘米,而該電阻係數比諸如NiFe高導磁合金(permalloy)的電阻係數(通常是15-20毫歐姆-厘米)高了大約10倍,因而與高導磁合金相比時,渦流損失可被最小化。在一實施例中,當磷百分率大於大約14%時,該磁性材料的電阻係數包含大於大約150微歐姆-厘米。
磁性材料102之磁致伸縮係數(magnetostriction coefficient)包含大約0.5~1.5×10-6
,遠小於純鈷的磁致伸縮係數1.0×10-5
。第2e圖示出厚度大約為2微米的電鍍CoPRe磁性材料102的磁導率219與頻率221間之關係圖。在某些實施例中,磁性材料102在高達150MHz的頻率下之磁導率可包含大約700。在一實施例中,磁性材料102的電阻係數可包含大約100微歐姆-厘米至大約200微歐姆-厘米,且磁性材料102在自大約0至大約150MHz的頻率下之磁導率可包含大約600至大約800。
請再參閱第1e圖,可在被配置在磁性材料102與基材100之間的一薄介電層114上形成至少一導電結構112。在一實施例中,該至少一導電結構112可包含諸如一銅繞組結構等的一銅互連結構,該銅繞組結構在某些例子中可被用來作為電感繞組,且可包含大約1至大約10微米之一厚度116。該至少一導電結構112之特定厚度116將根據特定應用而變動。
在某些實施例中,可在至少一導電結構112(第1f圖)上及周圍形成諸如聚醯亞胺層118等的一介電層118。在一實施例中,可在上表面117上以及個別導電結構112間之空間119中形成介電層118。
在一實施例中,可在至少一導電結構112(第1g圖)上形成第二層的磁性材料120(該磁性材料120可包含與該第一層的磁性材料102類似之材料),以便形成一電感結構122。電感結構122可包含諸如各種電感及變壓器結構/裝置,且可被用於諸如晶片內建及構裝內建電壓轉換器、射頻高頻電路、雷達、及電磁干擾雜訊降低電路等的微電子電路。在一實施例中,電感結構122可包含一封裝基材(該封裝基材可包含一些次微米CMOS裝置)的一部分,且可包含高頻非晶質磁性材料及多層金屬化層。
在某些裝置中,為了得到電感磁通量的理論上之最大增加,必須使該等兩層的磁性材料102、120接觸,以便將磁通量耗損最小化至零。在高工作頻率下,先前技術的裝置之視在電感值(apparent inductance)可隨著頻率的減少而逐漸減少,這是因為可能有因在該磁性材料中流過的渦流之耗損。因此,小心設計的磁性通孔被用來將諸如電感結構122等的此種高頻電感結構之電感值最大化。
在沒有良好磁性連接之情形下,磁通量可能漏出,而造成裝置的電感值之顯著耗損。該磁性連接可包含一磁性通孔124,該磁性通孔124包含該第一層的磁性材料102與該第二磁性層120相互接觸而完成磁通量的迴路之區域。
在另一實施例中,磁性材料102可包含此項技術中習知的其他電感結構(圖中未示出)之一部分。本發明所述之磁性材料102、120不限於被用於電感結構122,而是可應用於此項技術中習知的任何類型之電感/變壓器/微電子結構。此外,可將磁性材料102、120用於諸如晶片內建及(或)構裝內建電壓轉換器、射頻高頻電路、雷達、及電磁干擾雜訊降低電路等的微電子電路。在一實施例中,磁性材料102、120可包含一封裝基材(該封裝基材可包含一些次微米CMOS裝置)的一部分,且可包含高頻非晶質磁性材料及多層金屬化層。
在第3圖所示之另一實施例中,在步驟302中,可在一基材上形成一磁性材料,其中該磁性材料包含錸、鈷、及磷。在步驟304中,可在低於大約攝氏330度的溫度下將該磁性材料退火,其中該被退火的磁性材料之矯頑力小於大約1厄斯特。在另一實施例中,該被退火及未被退火的磁性材料可包含小於大約0.3厄斯特之矯頑力。在另一實施例中,該被退火的磁性材料可包含實質上相同百分率的錸、鈷、及磷。在另一實施例中,該被退火的及未被退火的磁性材料可根據特定應用而額外地包含一部分的鐵。在另一實施例中,該磁性材料可額外地包含鐵。
本發明之效益包括能夠製作出具有可在高於大約30MHz的頻率下工作的磁性薄膜之高頻電感及變壓器。第二,兩層磁性材料的使用將導致電感值的顯著增加,因而需要磁性通孔。第三,難以使用傳統的濺鍍技術以沈積較厚的薄膜(5~10微米),因而本發明所述之電鍍方法有利於形成較厚的薄膜。
第四,本發明提出的該等新合金之電阻係數(~150微歐姆-厘米)實質上高於諸如NiFe(電阻係數~16微歐姆-厘米)及CoZrTa等的其他材料之電阻係數,因而造成高頻下的較小之渦流損失。第五,新合金CoPRe、CoPReFe在高達大約攝氏330度的溫度下可維持其優異的磁特性。
雖然前文之說明已指定了可被用於本發明的方法之某些步驟及材料,但是熟悉此項技術者當可了解:可作出許多修改及替代。因此,所有此類修改、改變、替代、及增添將被視為在最後的申請專利範圍所界定的本發明之精神及範圍內。此外,我們當可了解:諸如微電子結構等的微電子裝置之某些觀點是此項技術中習知的。因此,我們當可了解:本發明所提供的圖式只示出一例示微電子裝置中與本發明的實施有關之一些部分。因此,本發明不限於本說明書所述的結構。
100...基材
102,120...磁性材料
203...正向電流密度
205...反向電流密度
209...正向時間
211...關閉時間
207...反向時間
115...初始部分
104...部分
106...高磷濃度區
110...多層結構
215...電阻係數
217...磷的原子百分率
219...磁導率
221...頻率
114,118...介電層
112...導電結構
116...厚度
117...上表面
119...空間
122...電感結構
124...磁性通孔
雖然本說明書將以特別指出且清楚地要求被視為本發明的特徵之申請專利範圍作為總結,但是可參照前文中對本發明之說明且配合參閱各附圖,而更易於確定本發明之優點,在該等附圖中:
第1a-1g圖示出根據本發明的實施例之結構。
第2a-2e圖示出根據本發明的實施例之圖形。
第3圖示出根據本發明的實施例之流程圖。
100‧‧‧基材
102,120‧‧‧磁性材料
114,118‧‧‧介電層
112‧‧‧導電結構
122‧‧‧電感結構
124‧‧‧磁性通孔
Claims (20)
- 一種形成積體電路之感應器結構的方法,包含下列步驟:在一基材上形成一磁性材料,其中該磁性材料包含錸、鈷、及磷;以及在低於大約攝氏330度的一溫度下將該磁性材料退火,其中該被退火的磁性材料之矯頑力低於大約1厄斯特。
- 如申請專利範圍第1項之方法,其中形成該磁性材料之該步驟進一步包含下列步驟:藉由加入錸而減少該磁性材料之矯頑力。
- 如申請專利範圍第1項之方法,進一步包含下列步驟:使用一電鍍製程以形成該磁性材料,其中該電鍍製程之電鍍浴包含一鈷鹽、一錸鹽、及一磷來源。
- 如申請專利範圍第1項之方法,其中係以直流電鍍、反脈衝電鍍、及脈衝電鍍中之一者形成該磁性材料。
- 如申請專利範圍第1項之方法,其中藉由形成一第一奈米層的磁性材料,然後在該第一奈米層的磁性材料上形成一第二奈米層的材料,而形成該磁性材料。
- 如申請專利範圍第5項之方法,其中該第一奈米層及該第二奈米層中之一奈米層之磷百分率大於該第一奈米層及該第二奈米層中之另一奈米層的磷百分率。
- 如申請專利範圍第1項之方法,其中形成該磁性 材料之該步驟進一步包含下列步驟:交替配置可以是磁性或非磁性的具有高磷百分率材料之奈米層、以及具有低磷百分率磁性材料之奈米層,以便形成一多奈米層之磁性材料。
- 如申請專利範圍第1項之方法,其中該磁性材料包含大約0.1至大約5原子百分率之錸百分率。
- 如申請專利範圍第1項之方法,其中該磁性材料包含鐵,且其中該磁性材料之飽和磁通為大約2.0特斯拉及更小。
- 一種形成積體電路之感應器結構的方法,包含下列步驟:在一基材上形成其中包含錸、磷、及鈷之一磁性材料,其中該磁性材料包含一電感結構之一部分,且其中該磁性材料包含低於大約1厄斯特之矯頑力;以及在低於大約攝氏330度的一溫度下將該磁性材料退火,其中該被退火的磁性材料之矯頑力保持在低於大約1厄斯特。
- 如申請專利範圍第10項之方法,其中該磁性材料之磁導率在自大約0至大約150 MHz的頻率下為大約600至大約800。
- 如申請專利範圍第10項之方法,其中該磁性材料之電阻係數為大約100微歐姆-厘米至大約200微歐姆-厘米。
- 一種積體電路之感應器結構,包含: 在一基材上包含錸、磷、及鈷之一磁性材料,其中磷的原子百分率包含大約8%至大約25%,且錸的原子百分率包含大約0.1%至大約5%,且其中該磁性材料包含低於大約1厄斯特之矯頑力;以及其中該磁性材料包含一電感結構之一部分。
- 如申請專利範圍第13項之結構,其中該磁性材料包含由高磷百分率奈米層及低磷百分率奈米層構成的一系列之交替奈米層。
- 如申請專利範圍第14項之結構,其中該高磷百分率奈米層包含小於大約5奈米之厚度,且該低磷百分率奈米層包含大約40奈米或更小之厚度。
- 如申請專利範圍第13項之結構,其中該磁性材料包含大約0.5微米至大約30微米之厚度。
- 如申請專利範圍第13項之結構,其中該磁性材料包含鐵,且其中該磁性材料之飽和磁通量小於大約2.0特斯拉。
- 如申請專利範圍第13項之結構,其中該磁性材料之電阻係數為大約100微歐姆-厘米至大約200微歐姆-厘米,且其中該磁性材料之磁導率在自大約0至大約150 MHz的頻率下為大約600至大約800。
- 如申請專利範圍第13項之結構,其中該結構包含其中包含多層金屬化層互補金屬氧化物半導體(CMOS)結構的封裝結構之一部分。
- 如申請專利範圍第13項之結構,其中該電感結 構包含晶片內建及構裝內建電壓轉換器、射頻(RF)高頻電路、電磁干擾(EMI)雜訊降低電路、及雷達電路中之至少一者的一部分。
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US11/968,118 US8029922B2 (en) | 2007-12-31 | 2007-12-31 | Forming electroplated inductor structures for integrated circuits |
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US8884438B2 (en) * | 2008-07-02 | 2014-11-11 | Intel Corporation | Magnetic microinductors for integrated circuit packaging |
US9204581B2 (en) * | 2011-11-14 | 2015-12-01 | Mediatek Inc. | Method for performing chip level electromagnetic interference reduction, and associated apparatus |
US20140152410A1 (en) | 2012-12-03 | 2014-06-05 | Arizona Board of Regents, a body corporate of the State of Arizona Acting for and on behalf of Arizo | Integrated tunable inductors |
US9614079B2 (en) * | 2014-04-04 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | MOS devices with ultra-high dielectric constants and methods of forming the same |
US10043607B2 (en) | 2016-05-02 | 2018-08-07 | International Business Machines Corporation | Electrolessly formed high resistivity magnetic materials |
CN111628074B (zh) * | 2020-05-26 | 2022-07-26 | 中国人民解放军国防科技大学 | 一种低磁滞隧道结磁敏感体的制备方法 |
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JPS6025203A (ja) * | 1983-07-21 | 1985-02-08 | Tdk Corp | 垂直磁気記録媒体 |
US6124047A (en) * | 1997-07-29 | 2000-09-26 | Alps Electric Co., Ltd. | Soft magnetic film and a magnetic head of an MR/inductive composite type using such a soft magnetic film |
US20070007496A1 (en) * | 2004-06-29 | 2007-01-11 | Ng Wei B | Magnetic material, and a MEMS device using the magnetic material |
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US20080003698A1 (en) * | 2006-06-28 | 2008-01-03 | Park Chang-Min | Film having soft magnetic properties |
US20080075975A1 (en) * | 2006-09-26 | 2008-03-27 | General Electric Company | Magnetic cores for inductors and transformers and method of manufacture |
US7867787B2 (en) * | 2007-12-31 | 2011-01-11 | Intel Corporation | Forming inductor and transformer structures with magnetic materials using damascene processing for integrated circuits |
US8884438B2 (en) * | 2008-07-02 | 2014-11-11 | Intel Corporation | Magnetic microinductors for integrated circuit packaging |
US7911313B2 (en) * | 2008-07-02 | 2011-03-22 | Intel Corporation | Inductors for integrated circuit packages |
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JPS6025203A (ja) * | 1983-07-21 | 1985-02-08 | Tdk Corp | 垂直磁気記録媒体 |
US6124047A (en) * | 1997-07-29 | 2000-09-26 | Alps Electric Co., Ltd. | Soft magnetic film and a magnetic head of an MR/inductive composite type using such a soft magnetic film |
US20070007496A1 (en) * | 2004-06-29 | 2007-01-11 | Ng Wei B | Magnetic material, and a MEMS device using the magnetic material |
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US8029922B2 (en) | 2011-10-04 |
TW200944623A (en) | 2009-11-01 |
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WO2009088590A3 (en) | 2009-09-03 |
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