TWI399659B - Designed for Chip Design and Chip Products Designed for Chip Packaging and Board Design - Google Patents

Description

Wafer pin designation method and program product for common design of chip package and circuit board

The invention relates to a method for assigning pins of a wafer, in particular to a method for designating a chip pin for a common design of a chip package and a circuit board.

Process technology is becoming more and more sophisticated, and the accumulation of wafers is rapidly increasing, making the assignment of wafer pins increasingly difficult.

Currently, there are existing pin assignments, and the chip designer usually assigns pins according to the rule of thumb. When considering the factors between the price of the chip pin assignment (related to the package area) and the performance of the pin signal, the designer must Continuous testing can get better pin assignments, because the aforementioned chip package price is related to the package area, and the pin arrangement affects the quality of the pin signal. The factors that must be considered are complicated, so the design is often caused. Trouble with manual pin assignments. For example, the designer obtains the necessary design parameters and specifications (signal operating frequency, I/O characteristic requirements, power supply design, voltage level, etc.) of the chip pins, and then according to the design parameters and specifications one by one. Performing pin assignments and initially obtaining a package size that meets specifications requires a process that takes about a week. In addition to the above-mentioned existing pin assignments, in addition to the tests and adjustments that must be repeated in the process, the assigned pins do not properly consider the electrical characteristics of the signal (such as anti-jamming, crosstalk, etc.), and there is no way to cooperate with the printed circuit. The board's components are designed with pin assignments to improve board routing network complexity and routing quality, resulting in over-reliance on manpower, tedious design time, increased cost, and inability to collaborate with components of printed circuit boards. Pin assignments cause problems such as reduced winding performance.

In order to solve the technical problem that the existing pin assignment technology can not automatically coordinate the pin assignment with the components of the printed circuit board, resulting in inefficiency, time waste and design cost increase, the present invention proposes a new and automated manner. After pre-setting the relationship between the components of the chip and the printed circuit board and the necessary electrical characteristics, the pin assignment with good performance is automatically generated to achieve automation and circuit layout, signal performance, and package area optimization for the chip pins. The effect of the assignment.

In accordance with the foregoing technical problems, the present invention provides a method for designing a chip pin design for a chip package and a circuit board, the steps of which include: accepting a set pin specification and requirement: obtaining specifications and limits of a design target wafer, The specification and the limitation include a connection position configuration relationship between the design target wafer and a plurality of components of a printed circuit board, a signal integrity requirement of the chip, a signal pin name and quantity of the chip, and a number of power pins of the chip; Pin blocks: based on the specifications and limits to generate a plurality of pin blocks (PA _i ) that meet the specifications and limits, each pin block has a different number of signal pins and is mainly used to boost each pin The power pin or ground pin of the signal quality in the block; the construction and grouping of the pin module: according to the configuration relationship and the connection relationship between the components of the chip and the printed circuit board, a plurality of corresponding components are respectively generated a pin module, wherein the pin module includes one of the pins that meets the specifications and restrictions of the corresponding component The block and a power pin module, and each pin module is programmed according to the positional relationship of the corresponding components, and uses a preset boundary condition to limit the pin group grouping decision strategy (boundary-constrained pin- Block grouping strategy (BCPG) or a congestion-free pin-block grouping strategy (CFPG) arranges each pin module in a clockwise or counterclockwise manner around the wafer A pin assignment area of the four sides, and the pin modules corresponding to the four sides of the chip are grouped into four grouped pin modules, and each grouped pin module is respectively Placed in a pin assignment area corresponding to the four sides of the wafer, each grouped pin module and the corresponding pin assignment area each generate a size relationship parameter Ei, And the planar position configuration of the pin module: each grouped pin module is calculated according to the four size relationship parameters Ei to obtain a pin assignment area having a minimized package size, and then each grouping The pin module in a reconfigured algorithm fills an excess area of the pin assignment area beyond the minimized package size into a vacant area in a moving or cutting manner.

In the step of generating a plurality of pin blocks, the specification and the limitation are described and solved by an Integer Linear Programming (ILP) to generate the plurality of pin blocks (PA _i ). Among them, the formula of the integer linear program problem is as follows:

Where: p _j,k represents the pin type of each pin block (PA _i ) generated (1 represents a signal pin, 0 represents a power pin or a ground pin); Represents the number of signal pins of the pin block (PA _i ), and row and col represent the number of pins and the number of pins (signal pin number per pattern) of the pin block (PA _i ); Equation (4) specifies a signal pin capacity (C _k ) that limits the number of signal pins for each pin block (PA _i ) in each row; Equation (5) specifies a differential signal A differential signal constrain (D _j ) means that a differential signal pin of the pin block (PA _i ) as a differential application must be allocated in an adjacent position in the same column; 6) is the ratio of the signal pin to the ratio of the signal-to-return path pin (SRR _i ); the formula (7) is the ratio of the signal pin to the ratio as a shield pin. (ratio of signal-to-shielding pin, SSR _i ); and formula (8) is a type of return path pin (RPT _i ), the type of the path path pin and the loop Corresponding to the type of the reference plane of the printed circuit board (PCB) corresponding to the path pin, the reference The pattern of the face is included in a ground plane or a power plane of the printed circuit board.

Wherein, in the construction and grouping step of the pin module, the boundary condition limiting pin module grouping decision strategy (BCPG) uses a safe range:

φ ₁ ‧AVG _s ≦S _m ≦φ ₂ ‧AVG _s

Where: Sm is the size of a grouped pin-block; φ ₁ and φ ₂ are user-definable values; AVG _s = (Σ _n w _n )/4 is grouped The average size of the pin modules; and w _n is the width of each grouped pin module.

Wherein, in the construction and grouping step of the pin module, the wire jam blocking exclusion pin module grouping decision strategy (CFPG) uses a safe range:

ψ ₁ ‧ AVG _p ≦ TP _i ≦ψ ₂ ‧ AVG _p ... (10)

Where: TP _I is the total number of signal pins of the grouped pin module; ψ ₁ and ψ ₂ are user-defined parameters; AVG _p = (Σ _j p _j )/4 is each grouped pin module The average number of signal pins; p _j is the number of signal pins for each pin module.

Wherein, in the plane position configuration of the pin module, calculating the pin assignment area having a minimized package size according to the four size relationship parameters Ei is performed by expressing the specification and the limit as a linear problem. The linear problem is as follows:

Minimize:

And subject to:

W _min = H _min ; w _Core = h _Core (15)

Where: W _{min is} the width of the pin assignment area of the minimized package size; H _{min is} the height of the pin assignment area of the minimized package size; w ₂ , ₄ respectively represent the second side of the chip, The width of each of the pin modules corresponding to the fourth side; w _{1 i} , w _{3 i} respectively represent the width of each of the pin modules corresponding to the first side and the third side of the wafer, wherein i represents a different pin module; h ₁ and h ₃ respectively represent the heights of the respective pin modules corresponding to the first side and the third side of the wafer; h _{2 i} and h _{4 i} respectively represent the respective sides corresponding to the second side and the fourth side of the wafer. The height of the pin module, where i represents a different pin module; and w _Core , h _Core respectively represent the width and height of a core of the wafer at the center of the pin assignment area of the minimized package size.

The invention further provides a computer program product for designing a chip pin design for a chip package and a circuit board. When the computer is loaded into the computer program and executed, the chip package and the circuit board can be jointly designed. The chip pin designation method.

Therefore, the present invention has a complete consideration of the quality of the pin signal, the winding performance of the printed circuit board, and the package area in the pin assignment process. Therefore, the present invention can not only perform pin assignment with the component automation of the printed circuit board, but also The package area can also be optimized, so that the invention achieves the technical effect that can be designed together with the printed circuit board and has high efficiency, automation and design cost.

In order to make it easier to understand the technical content of the present invention, first consider a number of considerations for configuring the pins. Please refer to the first A and B diagrams. When a chip (10) is in a pin-out designation, the designer must consider the following important limitations and considerations:

1) Printed circuit board (PCB) component position configuration: Please refer to the first A picture, a printed circuit board (PCB) has many different components and connectors (numbered as And the wafer (10) includes pin modules corresponding to the components and connectors (numbered as The electrical connection is made to the components and the connector through the printed circuit board (PCB). One of the main causes of the parasitic inductance of the wafer (10) is the length of signal net between the wafer (10) and the component and the connector. Therefore, the wafer can be inferred. (10) The pin package configuration type determines part of the parasitic inductance, so that the pin of the chip (10) may cause severe transient switching noise (V _SSN ) to the overall circuit product, such as the following formula (1):

V _SSN =NL _tot (dl/dt)...(1)

Where: N is the number of switching of the number of switching drivers; L _tot is the equivalent inductance that the current must pass; and I is the current of the driving signal.

In order to shorten the length of the signal line network to reduce the aforementioned parasitic inductance problem, the pin configuration of the chip (10) must be allocated in an appropriate position, and the position of the components and connectors on the printed circuit board (PCB) is unchanged. Under the condition, by appropriately arranging the position of the pin module of the wafer (10) so that the different pin modules are close to the components or connectors to be connected in the printed circuit board (PCB), the signal can be effectively shortened. The length of the line network, such as the conversion of the second A picture to the second B picture, is an example.

2) Routability

When considering winding, the rigid board routing rule often limits the row number of the pin module of the chip (10), and the signal line network of the printed circuit board (PCB). Width and spacing, etc.

Please refer to the second figure, which is a cross-sectional view of a flip-chip package wafer (10) bonded to the printed circuit board (PCB); in a general 4-layer printed circuit board (PCB) process rule Only the upper (first layer) and lower (fourth layer) layers allow the signal network to be bypassed, and a second layer and a third layer sandwiched between the upper and lower layers are used as power supply and grounding plates. . The wafer (10) of the flip chip package comprises a wafer body (die, 11), a plurality of solder pieces (solder bumps, 12) electrically connected to the wafer body (11), and a package body of the wafer body ( 11) and a flip chip package structure (13) of each solder member (12), the flip chip package structure (13) comprising an upper cover (Mold cap, 131) and a chip package base (132), wherein the wafer is located on the wafer The solder member (12) on the outer edge of the body (11) is electrically connected via a via (Via) of the chip package base (132) and a solder ball (Solder ball, 133) fixed on an outer edge of the chip package base (132). Connecting, wherein the solder ball (133) placed on the chip package base (132) is inevitably used for connection with an upper signal line network (21) of the printed circuit board (PCB) because of the positional relationship. . Therefore, the solder member (12) in the middle of the wafer body (11) passes through the channel (Via) of the circuit bonding pad (132) and the chip package base (132) in a similar manner as described above. Other near central solder balls (133) are connected, and the solder member (12) in the middle of the wafer body (11) must be connected to the printed circuit board (PCB) via one of the printed circuit board (PCB) channels (22) One of the lower signal line networks (23) is connected. In addition to the foregoing, the manner in which the printed circuit board (PCB) and the wafer (10) are electrically connected is limited, and the third A and B drawings show a wafer (10) and the printed circuit board (PCB). The layout limitation example, the third A diagram and the third B diagram are respectively a top view of the upper layer of the printed circuit board (PCB) and a bottom view of the chip package base (132), wherein the printed circuit board (PCB) The upper layer includes a plurality of signal pads (211) and a plurality of grounding points (213). In this example, the limitation is as follows: each signal contact (211) has a size of 14 mils (1 mil = 25.4 um) and a signal. The pad pitch is 39.37 mils, the signal line width and the spacing are 5 mils, and only two signal lines can pass between the two signal contacts (211). The item size limit is shown in Figure B. In other words, based on the size limiting relationship of the foregoing example, it represents that the wafer (10) can only have three rows of pins connected to the upper layer of the printed circuit board (PCB), and because of this, if the wafer (10) has more A large number of wafer pins will cause a problem of lengthy congestion of the signal line network of the printed circuit board (PCB). Please refer to the fourth figure and Table 1, based on the foregoing problem, the maximum number of outer pin rows of the chip (10) (ie, the upper signal line network of the printed circuit board (PCB) The connected pins are limited to the package size (width x height) and the total number of pins (number of columns, number of rows) of the wafer (10) (Pin number (Row x Column) )) It doesn't matter, even if the package size is enlarged, it will not solve the dilemma of the number of pins, the arrangement and the limitation of the signal line network.

3) Signal Integrity considerations: In the example shown in Figures A and B, the current pin location is assigned a regular rule when the signal pins are arranged. When placed in the same row, it will have better matched impedance performance, but if the signal pins are placed in the same column, only some of the signal lines can have Better impedance matching. The aforementioned impedance matching has a significant influence on the overall performance of the wafer (10), especially in systems with high operating speeds, because it eliminates common mode noise and increases the quality of the signal. In addition, in order to achieve better signal integrity, the design must also consider the position between the signal pins and the power pins and ground pins, which will affect the placement of the pins. The return path inductance of the signal, and because the power pin and the ground pin can serve as a loop path for providing adjacent signal pins, the poor pin relationship position configuration will increase the current loop. The length of the current return loops increases the loop path inductance. In this way, in addition to the degradation of signal integrity, the problem of electromagnetic wave dissipation will also occur, and the mathematical model is similar to the above formula (1).

Considering the influence of crosstalk noise, the main influencing factor is mutual capacitance (C _m ) (S. Hall, G. Hall, and J. McCall. "High-Speed Digital System Design". Wiley-Interscience Publication, 2000.), because adjacent signal lines are injected between the signal lines. The induced noise (I _noise , _Cm ) is proportional to the mutual capacitance and is related to the rate in change of voltage of the driven signal pin, and the relationship is as follows (2) :

I _noise , _Cm =C _m (dV _driver /dt) (2)

According to the foregoing discussion, the optimal signal pin configuration method is that the signal pin is disposed beside the power pin or the ground pin, so that the signal pin is closely connected to a loop path (ie, adjacent to the pin). The voltage pin or the ground pin is coupled, and according to this method, the loop path inductance can be effectively reduced. In addition, if the signal pin is surrounded by the ground pin, the aforementioned mutual capacitance effect will also be improved, and the noise will be isolated.

Based on the limitations and considerations of the foregoing several chip pin assignment configurations, and in order to be able to automate the pin assignment of one of the pin patterns (PA _i ) of the wafer (10), the aforementioned limitations and considerations Written as an Integer Linear Programming (ILP) problem, by solving the ILP problem, the pin block (PA _i ) that meets the above limitations and considerations can be obtained. Among them, the formula (3)~(8) of the ILP problem is as follows:

Where p _j,k represents the pin type of each pin block (PA _i ) generated (1 represents the signal pin, 0 represents the power or ground pin); Represents the number of signal pins of the pin block (PA _i ), and row and col represent the number of pins and the number of pins included in the pin block (PA _i ).

Equation (4) specifies the signal pin capacity (C _k ), which limits the number of signal pins of each pin block (PA _i ) in each row. Generally speaking, the pin capacity is The average is 6, as described in Table 1.

Equation (5) specifies a differential signal constrain (D _j ). The differential signal pins that are used as differential for one of the pin blocks (PA _i ) must be assigned to adjacent positions in the same column (for example: p _{j,k +1} =1,iff p _{j , k} =1).

Equation (6) is the ratio of signal-to-return path pin (SRR _i ). The loop path pin has an important influence on signal integrity, so the designer must carefully Consider the numerical ratio of the SRR _{i for} each tile.

Equation (7) is the ratio of signal-to-shielding pin (SSR _i ). In order to isolate the problem of crosstalk, the designer must increase the SSR _i to allow more grounding. The foot is adjacent to the signal pin. When the value of SSR _i is reduced, it means that the designer has added a greater proportion of economic considerations, that is, filling in more signal pins in a certain area, which will inevitably affect the performance of crosstalk isolation. Obviously, the above two ratios SRR _i and SSR _i are the focus of the choice between the circuit performance and the price when the designer determines the pin position arrangement of the pin block (PAi).

Equation (8) is a type of return path pin (RPT _i ), the type of the loop path and the reference plane of the printed circuit board (PCB) corresponding to the loop path pin ( The type of the reference plane is related to the type of the reference plane included in a ground plane or a power plane of the printed circuit board (PCB). When the type of the loop path matches the type of the printed circuit board (PCB), the parasitic inductance drops.

Taking the printed circuit board (PCB) with the upper and lower layers of the above-mentioned windings as an example, examples of the limiting parameters for solving the ILP problem can be as follows in Table 2:

PA _i0 and PA _i1 in Table 2 above represent the first half (fore-half) and the back half (back-half) of each pin pattern (PA _i ).

Please refer to the fifth (1) to (6) diagrams, which are the six types of pin tiles (PA _i ) of the example described in Table 2 and their corresponding simplified impedance models, which are simplified. The impedance matching model (Z _L ) consists of a series resistor (R), a serial inductor (jω L), and a shunt capacitor (1/jω C), where Z _L =R+iω L+1/jω C. Taking the pin block 1 (PA ₁ ) as an example, each of the differential signal pins as the differential signal is surrounded by the ground pin, and the ground pins can be used as adjacent circuit path pins. The overall inductance is used as crosstalk noise between the isolated signal pin and the signal pin. Since the most important consideration in the design of the differential signal is the impedance matching characteristic of the signal winding network, the pin block 1 (PA ₁ ) of this example is on the printed circuit board (PCB) or the chip (10). The chip package base (132) achieves excellent network balance characteristics, as shown in the left panel of Figures A and B. Therefore, considering the performance point of view, the pin block 1 (PA ₁ ) reaches the pin map design of the optimized differential signal pin, and the corresponding impedance matching model is as shown in the fifth (1) to (6). The figure shows. The only omission of this pin block 1 (PA ₁ ) is that the signal pins that can be accommodated within the pin block (PAi) are limited.

In the most common case, if the return current of a signal pin flows through the ground plane of the printed circuit board (PCB), the signal pin should be coupled to the ground plane to make the loop path. The current is reduced and vice versa. Pins 4 (PA ₄ ) and 5 (PA ₅ ) in the fifth (1) to (6) diagrams are pin diagrams designed to achieve certain special-purpose wiring networks. The block, for example, because of the positional configuration of the power pin, allows the pin block 5 (PA ₅ ) to have superior power transfer characteristics than the pin block 4 (PA ₄ ). The pin block 5 (PA ₅ ) has better pin placement density and efficiency than the pin block 1 (PA ₄ ) compared to the pin block 1 (PA ₄ ), but uses a pin map Blocks 4, 5 (PA _{4, 5} ) will deteriorate the signal integrity on the printed circuit board (PCB) and the chip package base (132) because of poor impedance matching characteristics, which may be as in the third A As shown on the right side of Figure B, this allows the impedance matching model of the design using pin blocks 4, 5 (PA _{4, 5} ) to be responsible for other impedances from the printed circuit board (PCB) (Z _pcb ) or The impedance (Z _sub ) of the chip package pedestal (132), the two additional impedances may each include an equivalent resistance, an inductance, and a capacitance.

Compared with the above two pin blocks 4, 5 (PA ₄ , ₅ ), the pin blocks 2, 3 (PA _{2, 3} ) of Table 2 and the fifth (1) to (6) are referred to. A compromise between the pin signal quality and the package price between the pin blocks 4, 5 (PA _{4, 5} ) and the pin block 1 (PA ₁ ). Pin block 6 (PA ₆ ) is the most efficient and highest signal pin density pin (PA _i ) in the fifth (1) to (6) figure, which can be the most The pin size reduces the overall package area, but the main disadvantage of this pin block 6 (PA ₆ ) is that it ignores the signal integrity and allows the signal pin to be used only as test-in (test-out). Or a long pulse control signal such as a long pulse control signal, such as a signal pin that does not generate crosstalk. Therefore, Z _ext (Z _ex1~3 ) is used in the fifth (1) to (6) diagrams to indicate unwanted or unpredictable impedance in the corresponding pin block (PA _i ). These unwanted or unpredictable impedances Mainly from the printed circuit board (PCB) or the chip package base (132). In the fifth (1) to (6) diagram, AD_P0/AD_N0 represents a pair of differential signals for transmitting high-speed signals; AD represents a high-speed transmission of terminal-signed signals; in pin block 6 The SEL or TRAP represents the signal of a low speed or delayed pulse.

According to the general design conventions and the rule of thumb, the characteristics of the six pin blocks (PA _i ) obtained by solving the ILP problem described above can be expressed in Table 3 below. Therefore, based on the six pin tiles (PA _i ) proposed in this embodiment, the designer can use the six pin tiles (PA _i ) as the template for the pin location assignment according to the design requirements and uses. And matching the characteristic requirements (signal integrity, pin density, anti-interference characteristics, shielding effectiveness, etc.) of the particular bus bar wiring of the printed circuit board (PCB) or the chip package base (132), Select the appropriate pin tiles (PA _i ) to be aligned accordingly so that the validity of the pin assignments can be achieved.

The pin block (PA _i ) as described above is only an example, and its form is not limited to the above six modes, because the designer can select the required pin density, winding efficiency, signal integrity and other characteristics. Requires that the ILP problem is re-solved and the customized pin block (PA _i ) is used as the template specified by the pin. Therefore, the designation of the self-pin block (PA _i ) and the pin assignment work of the tile to the printed circuit board (PCB) and the chip package base (132) can be efficient and automated using the aforementioned method of the present invention. Complete the pin assignment work.

Hereinafter, various matters and methods required for the automatic assignment of the pin module corresponding to the position of the printed circuit board (PCB) component or the connector using the aforementioned pin block (PA _i ) will be further explained. After the designer completes the design of the pin block (PA _i ) according to the requirements of the electrical characteristics, the generated pin block (PA _i ) combination can be used to complete the connection with the connector or component as in the first A picture. Pin blocks, that is, using the completed pin tiles (PA _i ) as the basic elements of the pin modules, each pin module can internally contain a pin block (PA _i ). Wherein, since the package size of the wafer (10) is directly related to the shape and position arrangement of the pin module, the effective configuration of the pin module and the floorplanning for the pin module will be performed on the chip (10). ) The package size reduction is very helpful. For this reason, the present invention proposes a method for automatically performing the planar position configuration of the pin module using the aforementioned pin block (PA _i ), which is described in detail below:

A. Construction and grouping method of the pin module

In the current technology, the designer must spend half a day to one day to define the position layout of the chip (10) pin, because the current position of the pin layout is manually designed, so it is very It takes time and is not efficient. The present invention proposes to cooperate with known pin names, pin names, after initially determining the configuration position of the components or connectors of the printed circuit board (PCB), as compared to prior art techniques for assigning pins in a manual manner. The main chip pins, such as the pin-block placement sequence (order), the selected pin block (PA _i ), and the number of power pins, can be automated by assigning the necessary features to the main chip pins. The steps complete the assignment of the pins and the planar position configuration of the pin modules.

First, the placement order of the pin modules must first be confirmed: after the components or connectors on the printed circuit board (PCB) are determined, the chip (10) and the pin modules corresponding to the components or connectors can follow. Intuitive modes are placed in the order of clockwise or counterclockwise arrangement around each component or connector. Then, according to the electrical characteristics of the corresponding component or connector, select the appropriate pin block (PA _i ) to fill the pin module. Finally, depending on the known pin name and the selected pin block (PA _i ), the position of the signal pins in each pin module can be re-architected and assigned.

The number of power pins can be used to assist in the handling of power delivery issues. The strategy adopted by the present invention is to add a power-pin block that can serve as the printed circuit. A power channel for various power requirements of a board (PCB). Designers are free to define the design conditions required for the power pins so that individual signal pins meet their required power analysis results. In this way, when the pin module of the signal pin is configured, the power pin block of the power pin can be automatically disposed in the adjacent signal pin module, so that the signal can be completed. A full-featured pin module for the signal bus connection. The sixth figure cites an example in which the wafer (10) contains nine pin modules numbered #1~#9, which are used for nine different interfaces (components, connectors, ...). Connection, finally, using the aforementioned pin module placement sequence for a pin-block grouping strategy, the pin module grouping strategy is mainly for the chip (10) The pin modules are divided into four groups according to the four sides of the wafer (10). In order to further adjust the problem of the future winding complexity of the configured pins, and all the pin modules can be smoothly included into the package of the wafer (10), the present invention proposes two different pin modules. The grouping strategy is a boundary-constrained pin-block grouping strategy (BCPG) and a winding-blocking-removing pin module grouping decision strategy (congestion-free pin) -block grouping strategy, CFPG). The use of these two strategies may be selected or set according to the requirements of the chip design or the constraints that the designer wants to perform. For example, when designing the output pins of the chip set, Since the role of the chipset is in the action of the other components of the bridge connected to the motherboard, the location of other components on the motherboard is a major consideration, so in such a situation, the boundary conditions can be used to limit the grouping of the pins. Decision Strategy (BCPG), the seventh diagram is an example of using this boundary condition to limit the pin group grouping decision strategy (BCPG). As can be clearly seen from the seventh figure, the use of this strategy may shorten the winding path of the wafer pins and corresponding components, components or connectors, but it may cause a large difference in the distribution of winding density between the blocks. (a) and (b) of the seventh figure respectively show examples of sparse and dense winding conditions.

In addition, a safe range can be set for the use of the boundary condition limited pin module grouping decision strategy (BCPG):

φ ₁ ‧AVG _s ≦S _m ≦φ ₂ ‧AVG _s ...(9)

Where Sm is the size of a grouped pin-block; φ ₁ and φ ₂ are user-definable values; AVG _s =(Σ _n w _n )/4 is grouped The average size of the pin modules; w _n is the width of each grouped pin module. It can be known from the above formula (9) that the main consideration of adopting this strategy is the size of the pin module. After the pin sequence is arranged to match the pin configuration, each pin module will be grouped. The grouping of the plurality of pin modules is organized until the grouped pin modules are within the aforementioned security range. When using the BCPG strategy, each grouped pin module is reduced to the average size of the grouped pin modules, resulting in a minimum value of the E _i value for each side of the wafer (10) as shown in Figure 6. Using the BCPG strategy can effectively reduce the time required to reduce the package size of the package. Although the BCPG strategy can quickly obtain good size reduction results, it may cause the above-mentioned seventh figure (b) to be over-dense due to the neglect of the number of signal line pins of each pin module during the configuration process. The problem.

In the winding blocking exclusion pin module grouping decision strategy (CFPG) (hereinafter referred to as CFPG strategy), the main consideration is to achieve an average distribution of signal pins on the four sides of the wafer (10) In the assembled pin module, the problem of uneven distribution of signal pins on each grouped pin module is avoided, so that the printed circuit board (PCB) has better winding performance and can have more flexibility to make it important. The signal network achieves better impedance matching performance or more flexible adjustment of the position of the component or component. The eighth figure reveals an example of a grouped pin module using the CFPG strategy. Compared with the BCPG strategy, the number of signal pins in each grouped pin module can be more evenly distributed. The CFPG strategy is applicable to wafers that require high routability, such as field effect programmable gates and arrays (FPGAs). Because the location of the CFPG strategy for the pin module is not completely in accordance with the initial configuration of the components of the printed circuit board (PCB), the final location configuration of the components of the printed circuit board (PCB) may need to be performed with the CFPG. The actual placement of the output pins of the wafer (10) is adjusted. Similar to the BCPG, one of the CFPG strategies has the following safe range (10): ψ ₁ ‧ AVG _p ≦ TP _i ≦ψ ₂ ‧ AVG _p ... (10)

Where TP _I is the total number of signal pins of the grouped pin module; ψ ₁ and ψ ₂ are user-defined parameters; AVG _p = (Σ _j p _j )/4 is each grouped pin module The average number of signal pins; p _j is the number of signal pins for each pin module. Since the average number of signal pins is usually larger than the size of the grouped pin modules, the CFPG strategy must have a stricter safety range, such as ∣ψ ₁ -ψ ₂ ∣<∣φ ₁ -φ ₂ ∣, Achieve the same package range.

Because the pin module placement order will be considered in the BCPG strategy, this embodiment uses a first-fit heuristic algorithm to complete the grouping of the pin modules. The heuristic algorithm is An approximate solution algorithm for a bin-packing problem that sequentially arranges objects into a first bin and creates a new bin after the first bin is full .

When using the CFPG strategy, the main consideration is to evenly distribute the number of signal pins per module. Therefore, another heuristic algorithm can be used, such as a best-fit heuristic algorithm. The processing pin module is modularized, and the best fit heuristic algorithm ignores the order of the objects, but the objects are stuffed into the appropriate size box to minimize the redundant space in the box.

As mentioned above, various considerations regarding the pin block, such as signal integrity, power transfer conditions, winding performance, etc., need to be considered in the pin location configuration process. Therefore, after all the pin module positions have been configured, a rough pin assignment result has been completed, as shown in Figure 6. Meanwhile, the parameters E1 to E4 of the width and height of the more than or unfilled sections of the pin assignment areas of the four sides (sides 1 to 4) of the four sides (sides 1 to 4) of the wafer (10), respectively, may also be included. The results of the rough pin assignment are known, and the parameters E1 to E4 are used to perform planar position re-laying of each pin module to obtain the minimum package size, as will be detailed below.

B. Minimize package size and planar position configuration of the pin module

Referring to the sixth figure, all the necessary conditions and limitations of the present invention for minimizing the package size of the wafer (10) are formulated as a linear problem as follows:

Minimize:

And subject to:

W _min = H _min ; w _Core = h _Core (15)

Wherein, w _{1 i} , h ₁ , h _{2 i} , w ₂ , w _{3 i} , h ₃ , h _{4 i} , w ₄ can be obtained in the aforementioned grouping process, as shown in the sixth figure. The W _{min is} the width of the pin assignment area of the minimized package size; H _{min is} the height of the pin assignment area of the minimized package size; w ₂ , ₄ respectively represent the 2nd side of the chip, width of four sides corresponding to the respective pin module; w _{1 i,} w _{3 i} respectively represents the first side of the wafer, the width of the third side corresponding to the respective pin block, where i represents the different pin module; H ₁ and h ₃ respectively represent the heights of the respective pin modules corresponding to the first side and the third side of the wafer; h _{2 i} and h _{4 i} respectively represent the respective connections corresponding to the second side and the fourth side of the wafer; The height of the foot module, where i represents a different pin module; and w _Core , h _Core respectively represent the width and height of a core of the wafer at the center of the pin assignment area of the minimized package size.

The core (Core) indicated in the sixth figure represents the core of a ball grid array package (BGA). Basically, the power and ground pins are disposed at the center of the package, and the wafer body (11) is in close proximity. The power source and the grounding pin are disposed. Therefore, the heat generated by the chip body (11) can be transmitted to the power source and the grounding pin. However, adding more power and ground pins to the center of the package can improve heat dissipation, but it increases the core area and increases the overall package size.

The aforementioned formulas (13) and (14) are used to define the area of the core corresponding to the wafer body (11), that is, w _Core and h _Core . Equations (11), (12), and (15) limit the shape of the package to a square shape. Equation (16) is to ensure that the minimum package size can be filled in all the pin modules and the pin gaps are avoided as much as possible.

When the parameters E1 to E4 are determined, an excess area of the calculated minimum package size and an empty area can be determined. For example, the E3 in the left figure of the sixth figure is exceeded. Zone, and E4 is the vacant zone.

After the aforementioned minimization is completed, the planar position configuration of the pin module can be performed. The so-called patch module plane position reconfiguration means that the pin module in the excess area is cut and filled into the nearby vacant area, so that the pin module that exceeds the minimum package size can be completely inserted into the minimum package size. The following is an example of an algorithm program virtual code that performs the reconfiguration of the plane position of the pin module (with reference to the sixth figure):

Please refer to the ninth (a) ~ (d) figure, which is an example of the plane position configuration calculation of a grouped pin module, and the ninth (a) figure is the grouped after the minimized configuration. The preliminary configuration result of the pin module (numbered #1~#9) is that the lower side of the core is set to the first side (side 1), and the adjacent sides of the counterclockwise direction are sequentially set to the second side. Four sides, in this example, it consists of two out-of-range zones (numbered E2 and E3) occurring on the second and third sides, respectively, and two gap zones (numbered E1 and E4) occurring on the first side. And the fourth side. Based on the foregoing algorithm, the calculation process of reconfiguring the two grouped pin modules (numbers #1, #2) disposed on the first side in the plane position does not operate (the line 4 execution result of the virtual code) Because E1>0.

Please refer to the ninth (a) diagram. When performing the calculation of each grouped pin module initially configured on the second side of the core, the grouped pin module of number #3 is used because of the aforementioned algorithm. 5 and 6 judge the result, and move clockwise to the first empty space area. After completion, the next side will be reconfigured.

Referring to the ninth (b) diagram, since E4>E2, the excess area formed by the grouped pin module #7 will be cut and then placed on the fourth side (based on the virtual code lines 8, 9).

Finally, the calculation process of the grouped pin module #9 on the fourth side will be as the grouped pin module #7 (as shown in the ninth (C) figure), and finally get the ninth (d) Optimized configuration results for the graph.

C. Dealing with Package Size Migration Issues

In practical applications, designers often need to re-enlarge or reduce the size of the wafer product that completes the package pin assignment based on different requirements or reasons to change the pin configuration.

For example, the conversion process of intergenerational products for wafer products often requires additional arrangement of test pins to make the package size slightly larger, or the wafer product further considers the manufacturing cost and wafer execution efficiency, and is another effect of changing the package size of the wafer product. One of the causes. As the foregoing needs to expand the size of the chip package due to the execution efficiency, the conventional pin assignment method may take a lot of time to reassign the pin configuration position. However, in this embodiment, it is necessary to change the package size when the package size is increased. The type of the pin pattern, that is, changing the SN _i parameter, such as replacing the larger SN _i with a smaller SN _i to make the width of the pin blocks larger.

On the other hand, if the manufacturing cost is the main consideration to replace the signal integrity, or if the chip body (11) is reduced in size and the size of the package must be reduced, the parameter SN _i will be changed from low to high, while sacrificing signal quality. However, it can improve the efficiency of the pin assignment and reduce the size of the pin module.

In order to make the package size change more systematic, the present invention defines a migration factor (MF) for evaluating the row of the pin module when changing the pin block (PA _i ). The number (column(width)of the pin block) is as follows:

Where col is the number of rows of the pin block (PA _i ), and SNp and SNm are the number of pre-adjusted and modified signal pins included in each pin block (PA _i ), respectively. Signal-pin number per pattern), taking the six-pin tiles (PA _i ) mentioned in the foregoing embodiment as an example, and Table 4 below shows the calculation results of the MF parameters of the six-pin tiles (PA _i ). Where "+" represents a larger pin module and "-" represents a reduced pin module. Therefore, the number of rows (width) required by the pin module can be estimated by multiplying the total pin number of a group by the grouping pin module by a variable parameter (MF). Thus, the designer You can then decide (you can set the judgment condition to automatically determine the re-selection of the pin block) to use the pin pattern (PA _i , pin pattern).

In summary, please refer to the tenth figure, the flow of the design method of the chip pin designing the chip package and the circuit board jointly designed according to the present invention, the steps include: accepting the setting pin specifications and requirements (51), generating the plural The pin block (53), the construction and grouping of the pin module (55) and the plane position configuration of the pin module (57).

In the step of accepting the setting pin specification and requirement (51), since the present invention is a method for matching a component of a printed circuit board and automatically assigning a chip pin, first, a specification of a design target (ie, a wafer) must be obtained first. And restrictions allow subsequent automation to perform automated calculations and assignments based on design specifications. The specifications and limitations may include the positional configuration of the components of the printed circuit board, the requirements for signal integrity, the name and number of signal pins, the number of power pins, and the like.

In the step of generating a plurality of pin blocks (53), the design requirements and the limitation considerations of the step (51) are written as an ILP problem (such as the above formulas (3) to (8)) and solved to obtain a complex number. A pin block (PA _i ) that satisfies the set ILP problem.

In the construction and grouping (55) step of the pin module, since a pin block has a one-to-one correspondence with components of the printed circuit board, the step (51) completes the input wafer connection. When the foot is restricted, the positional relationship between the plurality of pin modules of the chip and the components of the printed circuit board is known, and the specific requirements and electrical characteristics of the different pin modules are limited. Therefore, this step (55) actually After step (53) completes the generation of each pin block, according to the number of signal lines required inside each pin module, and automatically select the appropriate pin block according to the quality requirements of the signal line, according to the required signal The number of lines is directly filled in to form each pin module, and each pin module is arranged in sequence and arranged around the wafer in a clockwise or counterclockwise manner according to the corresponding component positional relationship. At the same time, when filling the pin block into a pin module, it will also be filled into the pin module according to the number of power pins required by the pin module, forming each pin module and printing The power path required for the corresponding component on the board.

After the foregoing pin module architecture is completed, the completed pin modules are grouped, and the strategies that can be grouped include: the boundary condition limiting pin module grouping decision strategy (BCPG policy) and the winding Line Blocking Excludes Pin Module Grouping Decision Policy (CFPG Policy). As described above, the process of performing the grouping of the pin modules may be performed by grouping the BCPG policy or the CFPG policy according to design requirements, and dividing each pin module into four pin assignment areas respectively located in the chip. The grouped pin modules of the edges, and after the grouping is completed, the size relationship between each grouped pin module and the four edge pin assignment areas is obtained, and the four size relationship parameters Ei are respectively Where Ei is a positively represented pin module that exceeds the pin assignment area, and Ei is negative to represent a grouped pin module that exceeds the pin assignment area.

The plane position configuration (57) of the pin module is to calculate a pin assignment area having a minimized package size according to the four size relationship parameters Ei in each grouped pin module (according to the foregoing The judgment process of Equations 11~16). Each grouped pin module moves or cuts an excess area beyond the pin assignment area into an adjacent slot area in a reconfigured algorithm.

(10). . . Wafer

(11). . . Chip body

(12). . . Solder piece

(13). . . Flip chip package structure

(131). . . Upper cover

(132). . . Chip package base

(133). . . Solder ball

(twenty one). . . Upper signal line network

(211). . . Signal contact

(213). . . Grounding point

(twenty two). . . aisle

(twenty three). . . Lower signal line network

(PCB). . . A printed circuit board

(Via). . . aisle

(PA _i ). . . Pin block

The first A and B diagrams are schematic diagrams of the arrangement and winding relationship between the components on the printed circuit board and the wafer.

The second figure is a schematic cross-sectional view of the wafer and the printed circuit board.

The third and fourth drawings are schematic diagrams of windings on the printed circuit board and on the chip package base.

The fourth figure is a schematic view of the wafer package in a bottom view.

The fifth (1) to (6) diagrams are schematic diagrams of six types of pin blocks and corresponding equivalent circuit models.

The sixth figure is a schematic diagram of the size relationship and reconfiguration of the pin module.

The seventh figure is a winding diagram of a grouping decision strategy using a boundary condition to limit the pin module.

The eighth figure is a winding diagram of a grouping decision strategy using a wire loop blocking exclusion pin module.

The ninth A to D diagram is a schematic diagram of the action of the plane position configuration of the pin module.

The tenth figure is a flow chart of a design method of a chip pin design applied to a chip package and a circuit board.

Claims (8)

A method for designing a chip pin for a chip package and a circuit board, comprising: a step of accepting a pin condition of a chip set by a user, the pin condition of the chip comprising a pin module of the chip and a connection position configuration relationship of a plurality of components of a printed circuit board, a signal integrity requirement of the chip, a name and number of signal pins of the chip, and a number of power pins of the chip; a step of generating a plurality of pin blocks According to the pin condition of the chip, a plurality of pin blocks (PA _i ) satisfying the pin condition are generated, and each pin block has a different number of signal pins and is mainly used for lifting each pin block. Signal quality power pin or ground pin; the step of constructing and grouping a pin module is based on the connection position configuration relationship between the chip and the components of the printed circuit board, and generates a plurality of corresponding components a pin module, wherein the pin module includes one of the pin blocks and a power pin module that meet the specifications and restrictions of the corresponding component, And each pin module is programmed according to the positional relationship of the corresponding components, and uses a boundary condition to limit the pin group grouping decision strategy or a winding blocking exclusion pin module grouping decision strategy, and each connection The foot modules are arranged in a clockwise or counterclockwise manner on a pin assignment area around the four sides of the wafer, and the pin modules corresponding to the four sides of the wafer are grouped into four groups. a pin module, each grouped pin module is respectively placed in a pin assignment area corresponding to four sides of the chip, and each grouped pin module and the corresponding pin assignment area each generate a size Relational parameter Ei,i 1, 2, 3, 4; and a step of the planar position configuration of the pin module, the grouped pin modules are calculated according to the four size relationship parameters Ei to obtain a pin having a minimized package size Assigning an area, after which each grouped pin module fills an excess area of the pin assignment area exceeding the minimized package size into a adjacent vacancy area by a reconfiguring algorithm . The method for designing a chip pin for a chip package and a circuit board according to the first aspect of the patent application, in the step of generating a plurality of pin blocks, the pin condition of the chip is an integer. The linear program problem is described and solved to generate the plurality of pin tiles (PA _i ), wherein the formula for the integer linear program problem is as follows: Where: p _j,k represents the pin type of each pin block (PA _i ) generated, 1 represents a signal pin, and 0 represents a power pin or a ground pin; Represents the number of signal pins of the pin block (PA _i ), row and col represent the number of columns and the number of rows of pins included in the pin block (PA _i ); formula (4) specification one Signal pin capacity (C _k ), which limits the number of signal pins for each pin block (PA _i ) in each row; Equation (5) specifies a differential signal limit condition (D _j ), which refers to a The differential signal pin of the pin block (PA _i ) as a differential application must be allocated in an adjacent position in the same column; formula (6) is the ratio of a signal pin to a pin as a loop path (SRR) _i ); Equation (7) is the ratio of a signal pin to a shielded pin (SSR _i ); and Equation (8) is a loop path pin type (RPT _i ), the loop path pin The type is related to the type of the reference surface of the printed circuit board corresponding to the loop path pin, and the reference plane is a ground layer or a power layer. The method for designating a chip pin for a chip package and a circuit board design as described in claim 1 or 2, in the step of constructing and grouping the pin module, the boundary condition limiting pin The module grouping decision strategy uses a safe range: φ ₁ ̇ AVG _s ≦ S _m ≦ φ ₂ ̇ AVG _s where: Sm is the size of a group of pin modules; φ ₁ and φ ₂ are users The defined value; AVG _s = (Σ _n w _n ) / 4 is the average size of the grouped pin modules; and w _n is the width of each grouped pin module. The method for designing a chip pin for a chip package and a circuit board design as described in claim 1 or 2, in the step of constructing and grouping the pin module, the wire blocking is excluded The foot module grouping decision strategy uses a safe range: ψ ₁ ̇ AVG _p ≦ TP _i ≦ψ ₂ ̇ AVG _p ... (10) where: TP _I is the total number of signal pins of the grouped pin module ; ψ ₁ and ψ ₂ are user-defined parameters; AVG _p = (Σ _j p _j )/4 is the number of average signal pins for each grouped pin module; p _j is the signal for each pin module The number of pins. The method for designating a wafer pin for a chip package and a circuit board jointly designed as described in claim 1 or 2, in the step of arranging the planar position of the pin module, according to the four dimensional relationship parameters When the Ei calculation obtains the pin assignment area with a minimized package size, it is solved by a linear problem as follows: Minimize: And meet: W _min = H _min ; w _Core = h _Core (15) Where: W _{min is} the width of the pin assignment area of the minimized package size; H _{min is} the height of the pin assignment area of the minimized package size; w ₂ , ₄ respectively represent the second side of the chip, The width of each of the pin modules corresponding to the fourth side; w _{1 i} , w _{3 i} respectively represent the width of each of the pin modules corresponding to the first side and the third side of the wafer, wherein i represents a different pin module; h ₁ and h ₃ respectively represent the heights of the respective pin modules corresponding to the first side and the third side of the wafer; h _{2 i} and h _{4 i} respectively represent the respective sides corresponding to the second side and the fourth side of the wafer. The height of the pin module, where i represents a different pin module; and w _Core , h _Core respectively represent the width and height of a core of the wafer at the center of the pin assignment area of the minimized package size. The method for designating a chip pin for a chip package and a circuit board design as described in claim 3, in the step of configuring the planar position of the pin module, when calculating according to the four dimensional relationship parameters Ei When a pin assignment area with a minimized package size is obtained, it is solved using a linear problem as follows: Minimization: And meet: W _min = H _min ; w _Core = h _Core (15) Where: W _{min is} the width of the pin assignment area of the minimized package size; H _{min is} the height of the pin assignment area of the minimized package size; w ₂ , ₄ respectively represent the second side of the chip, The width of each of the pin modules corresponding to the fourth side; w _{1 i} , w _{3 i} respectively represent the width of each of the pin modules corresponding to the first side and the third side of the wafer, wherein i represents a different pin module; h ₁ and h ₃ respectively represent the heights of the respective pin modules corresponding to the first side and the third side of the wafer; h _{2 i} and h _{4 i} respectively represent the respective sides corresponding to the second side and the fourth side of the wafer. The height of the pin module, where i represents a different pin module; and w _Core , h _Core respectively represent the width and height of a core of the wafer at the center of the pin assignment area of the minimized package size. The method for designating a chip pin for a chip package and a circuit board design as described in claim 4, in the step of arranging the planar position of the pin module, when calculating according to the four dimensional relationship parameters Ei When a pin assignment area with a minimized package size is obtained, it is solved using a linear problem as follows: Minimization: And meet: W _min = H _min ; w _Core = h _Core (15) Where: W _{min is} the width of the pin assignment area of the minimized package size; H _{min is} the height of the pin assignment area of the minimized package size; w ₂ , ₄ respectively represent the second side of the chip, The width of each of the pin modules corresponding to the fourth side; w _{1 i} , w _{3 i} respectively represent the width of each of the pin modules corresponding to the first side and the third side of the wafer, wherein i represents a different pin module; h ₁ and h ₃ respectively represent the heights of the respective pin modules corresponding to the first side and the third side of the wafer; h _{2 i} and h _{4 i} respectively represent the respective sides corresponding to the second side and the fourth side of the wafer. The height of the pin module, where i represents a different pin module; and w _Core , h _Core respectively represent the width and height of a core of the wafer at the center of the pin assignment area of the minimized package size. A computer program product for designating a chip pin design for a chip package and a circuit board, when the computer loads the computer program and executes After the line, the method described in Patent Application No. 1 can be completed.