TWI397922B - Hardware silicon chip structure of the buffer - Google Patents

Description

Buffer structure of hardware

The present invention relates to the technical field of integrating a single wafer system, and more particularly to a buffer structure of a hardware.

When performing integrated circuit design or hardware design (Silicon Intellectual Property (SIP) design), a buffer (Buffer) is built in the circuit for real-time operation or reading and writing data operation. use. Depending on the application, the architecture of the buffers in the hardware will be somewhat different. The excellent buffer architecture allows the use of hardware and software to be flexible and easy to use, and the writing of software is not limited. The advanced buffer architecture can even reduce the hardware area to save. cost.

In the design of hardware and technology, "Source+Destination→Destination" and other similar computing systems are commonly used in the hardware method. Wherein, "Source+Destination→Destination" means that a source data is read from a memory, and a target data is read from the same memory or other memory, and the source data and the target data are added. Then, the result is written back to the memory in which the target data is originally stored, and the target data is overwritten by the addition result. Such operations are not limited to addition operations, and other operations such as subtraction, shift operations, or (OR) operations, and (AND) operations, mutual exclusion, or (XOR) are often used in hardware design. .

When designing the "Source+Destination→Destination" operation related hardware, the conventional technology stores the source data and the target data in two separate buffers, and the data is stored in the buffer of the target data after being calculated. Figure 1 is a schematic diagram of the use of a buffer in the prior art. As shown, buffer 110 is comprised of two 64x32 bit static random access memory (SRAM). When the buffer 110 is applied to color processing, the internal processing and storage data of the hardware processing of the color processing uses the color formats of Alpha (A), Red (R), Green (G), and Blue (B). Each is represented by 8 bits. That is, each pixel is represented by a set of ARGB, and the platform color representation of the actual application is also the same, so the architecture of the buffer 110 can be used just in conjunction with the ARGB8888 platform.

If this ARGB8888 storage format is used on different platforms, the architecture of the SRAM must be changed to meet the requirements of the application.

Another conventional platform color representation is the RGB565 format. In system memory, each pixel is represented by 16 bits, and each word is 32 bits and is an optimal access unit. That is, each block can store data of 2 pixels. When the system reads a block every Clock Cycle, but must write the value of two pixels into the buffer of the hardware, the architecture of the buffer of the hardware in Figure 1 It needs to be adjusted to the architecture of Figure 2. As shown in FIG. 2, the source buffer and the target buffer are each split into two different static random access memories to achieve the purpose of simultaneously accessing two pixels. When the system reads a block, the hardware is transformed by a simple circuit, the read value is split into two pixel values, and the odd and even pixels are stored in different static random stores. In the memory, it is used to achieve the function of accessing two pixels at the same time.

Although the buffer architecture of Figure 2 solves the problem of simultaneously accessing two pixels, the physical memory must be divided into four blocks, causing waste of storage space, adding some additional control circuits, and adding many hardware. cost. It can be seen from this that there is still room for improvement in the buffer structure of the conventional hardware.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a bumper structure for a hard body to avoid the waste of storage space created by the prior art.

Another object of the present invention is to provide a bumper structure for a hard body to reduce overall hardware cost.

According to a feature of the present invention, the present invention provides a buffer structure for a hardware, which includes a first memory, a second memory, and a write circuit. The first memory has a memory space of 2N m bits, and the first memory is divided into a first area and a second area, and the first area is from the 0th mth to the ( N-1) m-bit memory space, the second region is composed of a memory space from the Nth mth to the (2N-1) m-bit, where N, m Is a positive integer. The second memory has a memory space of 2N m bits, and the first memory is divided into a first area and a second area, and the first area is from the 0th mth to the A memory space of N-1) m bits, the second region being composed of a memory space of a position from the Nth mth to the (2N-1) mth. The write circuit is connected to the first memory and the second memory to perform a write operation on the first memory and the second memory. The writing circuit writes the even-numbered address data of the source data to the second area of the second memory, and the writing circuit writes the odd-numbered address data of the source data to the second memory of the first memory. a write circuit that writes an even address data of a target data to a first area of the first memory, the write circuit writes the odd address data of the target data to the first of the second memory region.

3 is a block diagram of a buffer structure of the hardware of the present invention, having a first memory 310, a second memory 320, and a write circuit 330.

The first memory 310 has a memory space of 2N m bits, and the first memory is divided into a first area and a second area, and the first area is from the 0th mth position to the first (N-1) m-bit memory space, the second region is composed of a memory space from the Nth mth to the (2N-1) mth bits, wherein N, m is a positive integer.

The second memory 320 has a memory space of 2N m bits, and the first memory is divided into a first area and a second area, and the first area is from the 0th mth to the (N-1) m-bit memory space, the second region is composed of a memory space of a position from the Nth mth to the (2N-1) mth.

The write circuit 330 is connected to the first memory 310 and the second memory 320 to perform a write operation on the first memory 310 and the second memory 320.

4 is a schematic diagram of the write circuit 330 of the present invention writing data into a memory. The write circuit 330 writes the even address data (SA0, . . . , SA62) of a source of data to the second region of the second memory 320. The write circuit 330 writes the odd address data (SA1, . . . , SA63) of the source material to the second region of the first memory 310. The write circuit 330 writes the even address data (DA0, . . . , DA62) of a target data to the first area of the first memory 310. The write circuit 330 writes the odd address data (DA1, . . . , DA63) of the target data to the first region of the second memory 320.

As shown in FIG. 4, the target data is placed in the first area of the first memory 310 and the first area of the second memory 320, respectively. The source data is placed in the second area of the first memory 310 by the odd address data (odd pixels), and the even address data (even pixels) is placed in the second memory 320. Two areas. This kind of placement method happens to place the pixels belonging to the same operation in different memories, so that the hardware can also process the operations and buffer accesses once every cycle during the execution of the operation. The best processing speed. The DA0 pixel data (target data) in FIG. 4 is placed in the first area of the first memory 310, and the SA0 pixel data (source data) is placed in the second area of the second memory 320, so that it can be taken out at the same time. Operation. The DA1 pixel (target data) and SA1 (source data) pixel resources are also placed in different memories.

Figure 5 is a schematic illustration of the system angle of the memory of the present invention. That is, the architecture of the first memory 310 and the second memory 320 is viewed from the viewpoint of data storage. As shown in FIG. 5, the target data is stored in a first area of the first memory 310 and a first area of the second memory 320. The source data is stored in the second area of the first memory 310 and the second area of the second memory 320. From the system point of view, the storage of the target data and the source data is very simple, and the main purpose is that the write circuit 330 of the present invention performs the address switching function, so that a software can treat the buffer of the hardware. There are only two separate memories, and the software does not require special handling. The solid line frame 510 in Figure 5 represents the target buffer seen by the system, and the dashed box 520 represents the source buffer.

Figure 6 is a circuit diagram of a write circuit of the present invention. The write circuit 330 includes first and fourth to fourth gates 610 to 640 and first to fourth multiplexers 650 to 680. The first multiplexer 650 is connected to an input bus of the first memory 310, and the second multiplexer 660 is connected to a data bus of the first memory 310. The first NAND 610 is connected to A write signal pin of the first memory 310 is connected to the uniform signal pin of the first memory 310. The third multiplexer 670 is connected to the address bus of the second memory 320. The fourth multiplexer 680 is connected to the data bus of the second memory 320. The third NAND 630 is connected to the address bus. A write signal pin of the second memory 320 is connected to the uniform signal pin of the second memory 320.

The first multiplexer 650 receives an odd address BufB_Addr_Odd of the source data and an even address BufA_Addr_Even of the target data to generate an input address signal of the first memory 310, and outputs the input address signal to the first memory. The input bus of the body SRAM_0_Addr. The second multiplexer 660 receives the odd address data BufB_Din_Odd of the source data and the even address data BufA_Din_Even of the target data to generate an input data signal of the first memory, and outputs the input data signal to the first memory. The data bus is SRAM_0_Din.

The third multiplexer receives 670 an even address of the source data BufB_Addr_Even and an odd address BufA_Addr_Odd of the target data to generate an input address signal of the second memory, and outputs the input address signal to the second memory. The input bus SRAM_1_Addr. The fourth multiplexer 680 receives an even address data BufB_Din_Even of the source data and an odd address data BufA_Din_Odd of the target data to generate an input data signal of the second memory, and outputs the input data signal to the second memory. The data bus SRAM_1_Din.

The first gate 610 receives a write signal BufB_WEn_Odd of the odd address of the source data and a write signal BufA_WEn_Even of the even address of the target data to generate a write signal of the first memory, and outputs The write signal pin SRAM_0_WEn to the first memory. The second gate 620 receives the coincidence signal BufB_CEn_Odd of the odd address of the source data and the uniform energy signal BufA_CEn_Even of the even address of the target data to generate the consistent energy signal of the first memory, and outputs the same to the first The enable signal pin of a memory is SRAM_0_CEn.

The third gate 630 receives a write signal BufB_WEn_Even of the even address of the source data and a write signal BufA_WEn_Odd of the odd address of the target data to generate a write signal of the second memory, and outputs The write signal pin SRAM_1_WEn to the second memory. The fourth gate 640 receives the uniform energy signal BufB_CEn_Even of the even-numbered address of the source data and the uniform energy signal BufA_CEn_Odd of the odd-numbered address of the target data to generate the consistent energy signal of the second memory, and outputs the same to the first The enable signal pin SRAM_1_CEn of a memory.

By the writing circuit 330 of the present invention, the address switching function is performed, so that the storage of the target data and the source data becomes simple, and the software can make the buffer of the hardware and the intellectual property as only two pieces. Separate memory. For the software, the technique of the present invention is transparent, that is, the software can quickly access the first memory 310 and the second memory 320 without any modification.

Figure 7 is a comparison of the prior art and the area of use of the present invention. As shown in FIG. 2, the conventional technique uses four 64x32 bit static random access memories to form a buffer. The technique of the present invention uses two 128x32 bit static random access memories to form a buffer. Figure 7 is a static random access memory using the techniques of the present invention to form a buffer which is synthesized in a TSMC 0.13 micron process. As can be seen from Figure 7, the buffer structure of the present invention can indeed save a lot of hardware area.

It is an object of the present invention to use only two separate memories to form a buffer for a hard body. When the color data is stored in the buffer, the write circuit 330 of the present invention is stored in a buffer of the hardware and the like in a special arrangement, and the arrangement can achieve color data when reading and writing data. Special read and write requirements for applications.

It can be seen from the above description that in order to support different color format storage methods on different platforms, the memory composition of the hardware buffer is changed to use four memory to access, but in fact, hard The buffer of the body's intellectual property is split into four memories to form a waste of space and increase the complexity of accessing the circuit. However, the present invention is based on the architecture of only two memories, and uses a simple circuit to put the data into the buffer of the hardware and the special rehearsal, which can save the hardware area and the software operation hardware. The complexity of the buffer of the intellectual property.

The above-mentioned embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments.

110. . . buffer

310. . . First memory

320. . . Second memory

330. . . Write circuit

510. . . Solid line frame

520. . . Dotted box

610~640. . . First to fourth gates

650~680. . . First to fourth multiplexers

Figure 1 is a schematic diagram of the use of a buffer in the prior art.

FIG. 2 is a schematic diagram of the structure of a buffer of a conventional hardware.

Fig. 3 is a block diagram showing the structure of the buffer of the hardware of the present invention.

4 is a schematic diagram of the write circuit of the present invention writing data into a memory.

Figure 5 is a schematic illustration of the system angle of the memory of the present invention.

Figure 6 is a circuit diagram of a write circuit of the present invention.

Figure 7 is a comparison of the prior art and the area of use of the present invention.

310. . . First memory

320. . . Second memory

330. . . Write circuit

Claims (10)

A buffer structure of a hardware, comprising: a first memory having a memory space of 2N m bits, the first memory being divided into a first area and a second area, The first region is composed of a memory space ranging from 0th mth to (N-1) mth, and the second region is from the Nth mth to the (2N-1) a m-bit memory space, wherein N and m are positive integers; a second memory having a 2N m-bit memory space, the second memory being divided into a third region and a fourth region, the third region being composed of a memory space from a 0th mth to a (N-1)th mth, the fourth region being the Nth mth position a memory space of (2N-1) m bits; and a write circuit connected to the first memory and the second memory for the first memory and the second memory Performing a write operation; wherein the write circuit writes an even address data of a source data to a fourth region of the second memory, the write circuit singular address of the source data Writing to the second area of the first memory, the writing circuit writes the even address data of a target data to the first area of the first memory, the writing circuit blocks the odd address data of the target data Write to the third area of the second memory. The snubber structure of claim 1, wherein the write circuit comprises a first NAND gate to a fourth gate and a first multiplexer to a fourth multiplexer, the first multiplexer connection An input bus to the first memory, the second multiplexer is connected to a data bus of the first memory, and the first gate is connected to a write signal pin of the first memory The second multiplexer is connected to the consistent signal pin of the first memory, the third multiplexer is connected to the address bus of the second memory, and the fourth multiplexer is connected to the second The data bus of the memory is connected to a write signal pin of the second memory, and the fourth gate is connected to the consistent signal pin of the second memory. The buffer structure of claim 2, wherein the first multiplexer receives an odd address of the source data and an even address of the target data to generate an input bit of the first memory. The address signal is output to the input bus of the first memory. The buffer structure of claim 2, wherein the second multiplexer receives the odd address data of the source data and the even address data of the target data to generate the first memory. The data signal is input and output to the data bus of the first memory. The buffer structure of claim 2, wherein the third multiplexer receives an even address of the source data and an odd address of the target data to generate an input bit of the second memory The address signal is output to the input bus of the second memory. The buffer structure of claim 2, wherein the fourth multiplexer receives the even address data of the source data and the odd address data of the target data to generate the second memory. The data signal is input and output to the data bus of the second memory. The buffer structure of claim 2, wherein the first gate receives a write signal of an odd address of the source data and a write signal of an even address of the target data, Generating a write signal of the first memory and outputting the write signal pin to the first memory. The buffer structure of claim 2, wherein the second gate receives the coincidence signal of the odd address of the source data and the uniform energy signal of the even address of the target data to generate the The uniform energy signal of the first memory is output to the enable signal pin of the first memory. The buffer structure of claim 2, wherein the third gate receives a write signal of an even address of the source data and a write signal of an odd address of the target data, A write signal of the second memory is generated and output to the write signal pin of the second memory. The buffer structure of claim 2, wherein the fourth gate receives the uniform energy signal of the even address of the source data and the consistent energy signal of the odd address of the target data, to generate the The uniform energy signal of the second memory is output to the enable signal pin of the first memory.