TWI397181B - Semiconductor device and method for fabricating the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal oxide semiconductor (MOS) transistor and a method of fabricating the same.

With the rapid development of semiconductor process technology, in order to improve the speed and performance of components, the size of the entire circuit components must be continuously reduced, and the accumulation of components must continue to increase. In the trend of increasing component integration requirements, changes in component characteristics such as leakage current, hot carrier effect or short channel effect (SCE) must be considered to avoid It has a serious impact on the reliability and performance of the integrated circuit.

Taking a MOS transistor as an example, FIG. 1 is a schematic cross-sectional view of a conventional MOS transistor. As shown in FIG. 1, the gate structure 102 is disposed on the substrate 100, and the spacers 104 are disposed on the sidewalls of the gate structure 102. An offset spacer 106 of the source drain extension (SDE) is formed between the gate structure 102 and the spacer 104 and between the spacer 104 and the substrate 100. The source region 108a and the drain region 108b are disposed in the substrate 100 outside the spacer 104, respectively. The source extension region 110a and the drain extension region 110b are disposed in the substrate 100 below the spacer 104, respectively. That is, the source extension 110a is between the source region 108a and the gate structure 102, and the drain extension 110b is between the drain region 108b and the gate structure 102. A salicide 112 is also disposed on the gate structure 102, the source region 108a, and the drain region 108b.

Considering that the concentration of the source extension region 110a and the drain extension region 110b affects device performance, the doping amount of the source extension region 110a and the drain extension region 110b must be heavy enough to ensure component performance and quality. However, heavily doped source extensions 110a and drain extensions 110b result in very high gate-induced drain leakage (GIDL) and severe hot carrier effects. Although the gate-induced drain leakage current and hot carrier effect can be slowed down by reducing the doping amount of the source drain extension, it will cause the overlap between the sheet resistance and the gate drain (gate- Drain overlap capacitance) rises and seriously affects component performance. Moreover, the spacers 104 must be thick enough to prevent the dopants of the source regions 108a and the drain regions 108b from diffusing into the source extension regions 110a and the drain extension regions 110b, and sufficient space must be left to diffuse the source drains. In order to sufficiently suppress the occurrence of electrical punch through and short channel effects. In addition, when a stress layer is formed on the substrate 100, the thick spacers 104 tend to cause the stress layer to be away from the channel region, thereby reducing the effect of the stress layer on the carrier mobility.

Therefore, how to effectively ensure the reliability of components of semiconductor components and improve the component performance of semiconductor components will be an extremely important issue at present.

The present invention provides a semiconductor device in which component performance can be improved.

The present invention provides a method of fabricating a semiconductor device that forms a skewed and curved source drain extension (SDE).

The present invention provides a semiconductor device including a substrate, a gate structure, a doped region, and a lightly doped region. The substrate has a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface, and a third surface. The second surface is lower than the first surface. The third surface connects the first surface to the second surface. The gate structure is disposed on the first surface. The doped regions are disposed in the substrate on both sides of the gate structure and under the second surface. The lightly doped regions are respectively disposed in the substrate between the gate structure and the doped region. Each of the lightly doped regions includes a first portion and a second portion that are connected to each other. The first portion is disposed below the second surface and the second portion is disposed below the third surface.

In an embodiment of the invention, the third surface is inclined to the first surface, and an angle between the extending direction of the first surface and the third surface is between 45° and 60°.

In an embodiment of the invention, the first surface is substantially parallel to the second surface.

In an embodiment of the invention, the height difference between the first surface and the second surface is between 250 To 600 Between, and the horizontal spacing between the first surface and the second surface is between 250 To 350 between.

In an embodiment of the invention, the length of the first portion of each of the lightly doped regions is between 50 To 150 Between, while the length of the second part is between 300 To 700 between.

In an embodiment of the invention, the semiconductor component further includes a spacer disposed on the sidewall of the gate structure and located on the lightly doped region. The thickness of the spacer is, for example, 50 To 200 between. The material of the spacer may be an oxide, an oxynitride, a nitrided oxide, a nitride or a combination of the above.

In an embodiment of the invention, the semiconductor device further includes a self-aligned metal telluride layer disposed on the gate structure and on the doped region.

In an embodiment of the invention, the semiconductor component further includes a stress layer disposed on the substrate. The stressor layer is, for example, a nitride film that provides compressive or tensile stress to the channel region.

In an embodiment of the invention, the semiconductor component further includes a well region disposed in the substrate, wherein the doped region and the lightly doped region are located in the well region.

In an embodiment of the invention, the semiconductor component further includes a bag-shaped (annular) implanted region disposed in the substrate under the gate structure, and each of the pocket-shaped (annular) implanted regions are adjacent to each of the blends Miscellaneous area. The pocket (annular) implanted region is, for example, a localized pocket (annular) implanted region or a multiple pocket (annular) implanted region.

The present invention further provides a method of fabricating a semiconductor device. First, a substrate is provided and a gate structure is formed on the substrate. A portion of the substrate is removed with the gate structure as a mask to form a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface, and a third surface. The second surface is lower than the first surface. The third surface connects the first surface to the second surface. A lightly doped region is formed in the substrate on both sides of the gate structure. Each of the lightly doped regions includes a first portion and a second portion that are connected to each other. The first portion is disposed below the second surface and the second portion is disposed below the third surface. A doped region is formed in the substrate, each doped region being under the second surface and adjacent to the lightly doped region, respectively.

In an embodiment of the invention, the third surface is inclined to the first surface, and an angle between the extending direction of the first surface and the third surface is between 45° and 60°.

In an embodiment of the invention, the first surface is substantially parallel to the second surface.

In an embodiment of the invention, the height difference between the first surface and the second surface is between 250 To 600 Between, and the horizontal spacing between the first surface and the second surface is between 250 To 350 between.

In an embodiment of the invention, the length of the first portion of each of the lightly doped regions is between 50 To 150 Between, while the length of the second part is between 300 To 700 between.

In an embodiment of the invention, the method further includes forming a first spacer on the sidewall of the gate structure and the lightly doped region. The thickness of the first spacer is, for example, 50 To 200 between.

In an embodiment of the invention, the method of forming the first spacer includes the following steps. First, a layer of spacer material is formed on the substrate. Next, a second spacer is formed on the sidewall of the gate structure, wherein the second spacer covers a portion of the spacer material layer on the lightly doped region. A portion of the spacer material layer is removed with the second spacer as a mask, and then the second spacer is removed.

In an embodiment of the invention, after removing a portion of the spacer material layer, the doped region is formed with the second spacer as a mask. A lightly doped region is formed after the formation of the spacer material layer and before the formation of the second spacer; or, after the removal of the second spacer, a lightly doped region is formed.

In an embodiment of the invention, the lightly doped region and the doped region are formed after the first spacer is formed. The lightly doped region and the doped region are formed, for example, by a single process or a two-step process.

In an embodiment of the invention, the method further includes forming a self-aligned metal telluride layer on the gate structure and the doped region.

In an embodiment of the invention, the method further includes forming a stress layer on the substrate, such as a nitride film that provides compressive stress or tensile stress to the channel region.

In an embodiment of the invention, prior to forming the gate structure, a well region is formed in the substrate, wherein the doped region and the lightly doped region are formed in the well region.

In an embodiment of the invention, the method further includes forming a pocket-shaped (annular) implanted region in the substrate under the gate structure, and each of the pocket-shaped (annular) implanted regions is adjacent to each of the blends Miscellaneous area. The bag-like (annular) implanted region is, for example, a partial pocket (annular) implanted region or a composite pouch (annular) implanted region. The above-described bag-shaped (annular) implanted region may be formed after forming the stepped upper surface, or after forming the lightly doped region, or after forming the spacer material layer and before forming the lightly doped region And formed.

Based on the above, the semiconductor device of the present invention has a tilted and curved lightly doped region as a source drain extension (SDE), which can help to alleviate the hot carrier effect without reducing the dopant concentration of the lightly doped region. Furthermore, since the lightly doped region has a sloped and curved profile, the overlap capacitance between the gate induced drain leakage current (GIDL) and the gate drain can be reduced.

Furthermore, the method of fabricating the semiconductor device of the present invention forms a lightly doped region that is oblique and curved, so that the diffusion of the lightly doped region is not affected by the diffusion of the doped region, and a thinner gap can be formed in the structure of the semiconductor device. wall. In this way, by forming a thinner spacer, the stress layer can be brought closer to the channel region, so that the component performance can be further improved.

The above described features and advantages of the present invention will be more apparent from the following description.

2 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention. It should be noted that the following embodiment shows the first conductivity type in the P type and the second conductivity type in the N type, but the invention is not limited thereto. Those skilled in the art will appreciate that the present invention can also replace the first conductivity type with an N type and the second conductivity type with a P type to form a semiconductor element.

Referring to FIG. 2, the semiconductor device of the present invention includes at least a substrate 200, a gate structure 204, a doped region 206, and a lightly doped region 208. A substrate 200 having a first conductivity type is provided, which may be a P-type germanium substrate, a P-type epi-silicon substrate, or an insulating layer-on-semiconductor (SOI) substrate. The substrate 200 has, for example, a stepped upper surface 201. The stepped upper surface 201 includes a first surface 201a, a second surface 201b, and a third surface 201c, wherein the third surface 201c connects the first surface 201a and the second surface 201b. The second surface 201b lower than the first surface 201a may be substantially parallel to the first surface 201a. When the first surface 201a and the second surface 201b are substantially flat surfaces, the third surface 201c may be inclined to the first surface 201a. That is, the third surface 201c is a slope between the first surface 201a and the second surface 201b, wherein the upper edge of the slope connects the first surface 201a, and the lower edge of the slope connects the second surface 201b. In an embodiment, the height difference D ₁ between the first surface 201a and the second surface 201b is between 250. To 600 between. In an embodiment, the horizontal spacing D ₂ between the first surface 201a and the second surface 201b is between 250. To 350 between. In an embodiment, the extending direction of the first surface 201a and the third surface 201c form an angle ψ between 45° and 60°.

In addition, the substrate 200 is also provided with a well region 202 having a first conductivity type, which is, for example, a P-well. In an embodiment, a localized bag-shaped (annular) implanted region or a multiple bag-shaped (annular) implanted region having a first conductivity type (such as a P-type) may be disposed in the well region. 202. The partial pocket (annular) implant region or the composite pocket (annular) implant region is disposed, for example, below the gate structure 204 and adjacent to each of the doped regions 206, respectively. The well zone 202 is, for example, a well having only a super steep retrograde (SSR) well. In another embodiment, the well region 202 can also be a combination of a very steep retreating well and a pocket (annular) implanted region.

The gate structure 204 is disposed on the first surface. The length of the gate structure 204 is, for example, the length corresponding to the first surface 201a. The gate structure 204 includes a gate 204a and a gate dielectric layer 204b, wherein the gate dielectric layer 204b is disposed between the gate 204a and the substrate 200. The length of the gate 204a can be as small as 90 nm or other smaller dimensions. The material of the gate 204a may be metal, doped polysilicon, silicon-germanium or a combination of polysilicon and metal. The effective oxide thickness (EOT) of the gate dielectric layer 204b is, for example, about 20 To 35 To suppress leakage current from the gate 204a. The material of the gate dielectric layer 204b may be an oxide, a nitrided oxide, an oxynitride or a high-k material, wherein the high dielectric constant material is, for example, hafnium (Hf). ), titanium oxide (TiO _x ), hafnium oxide (HfO _x ), hafnium oxynitride (HfSiON), hafnium oxide (HfAlO), or aluminum oxide (Al ₂ O ₃ ).

The doped regions 206 of the second conductivity type are disposed in the substrate 200 on both sides of the gate structure 204. The doped region 206 is disposed under the second surface 201b. The doped region 206 may be an N+ doped region to serve as a source and a drain of the semiconductor device, respectively.

The lightly doped region 208 of the second conductivity type is disposed in the substrate 200 between the gate structure 204 and the doped region 206. The lightly doped regions 208 having the same conductivity type as the doped regions 206 are electrically connected to the corresponding doped regions 206 on both sides of the gate structure 204, respectively, and thus serve as source drain extensions (SDE). Each of the lightly doped regions 208 includes a first portion 208a and a second portion 208b that are interconnected. The first portion 208a is disposed under the second surface 201b and adjacent to the third surface 201c. The second portion 208b is disposed under the third surface 201c. In an embodiment, the second portion 208b sometimes also extends slightly into the area below the first surface 201a. Since the total horizontal length of each lightly doped region 208 will depend on the length of the gate 204a, the distribution of the lightly doped region 208 can be shortened as the length of the gate 204a is reduced. Taking the length of the gate 204a as an example of about 90 nm, the horizontal distribution of each lightly doped region 208 is about 400. To 600 between. In an embodiment, the length L ₁ of the first portion 208a is between 50 To 150 between. In an embodiment, the length L ₂ of the second portion 208b is between 300 To 700 between. It is to be noted that since the third surface 201c is an inclined surface, the inclination angle of each lightly doped region 208 is controlled within a range of 45 to 60 to maintain the punch through characteristic of the element.

In general, the lateral electric field depends only on the surface doping characteristics of the lightly doped region 208. Since the lightly doped region 208 has a sloped and curved profile formed by the first portion 208a and the second portion 208b, the first portion 208a can provide a reserved space for the doped region 206 to diffuse. In the structure of the semiconductor device, the surface of the lightly doped region 208 under the first surface 201a is doped lightly, so that the doping amount of the lightly doped region 208 is not reduced and the lightly doped region is not affected. In the case of 208 resistors, the hot carrier effect, the overlap capacitance between the gate bucks and the gate induced drain leakage current (GIDL) are effectively reduced. In detail, since the doping concentration in the overlap region between the gate and the drain is significantly reduced, the hot carrier effect, the gate-induced drain leakage current (GIDL), and the overlap capacitance between the gate and drain are also Will decrease. Moreover, the diffusion of the lightly doped region 208 under the gate structure 204 is independent of the diffusion of the doped region 206, and thus the doping concentration of the doped region 206 can be sufficiently heavy and deep enough.

In addition, the semiconductor device of the present invention may further include a spacer 210, a self-aligned metal telluride layer 212, and a stress layer 214. The spacer 210 is disposed on the sidewall of the gate structure 204 and is located on the lightly doped region 208. The spacer 210 has, for example, a curved profile corresponding to the contour of the sidewall of the gate structure 204, the third surface 201c, and a portion of the second surface 201b. In other words, the spacer 210 can isolate the sidewall of the gate structure 204 from the outside and cover a portion of the substrate 200 in which the lightly doped region 208 is formed. The material of the spacer 210 includes an oxide, an oxynitride, a nitrided oxide, a nitride, or a combination of the above. In an embodiment, the thickness 210a of the spacer 210 is approximately 50. To 200 between.

The self-aligned metal telluride layer 212 is disposed on the gate structure 204 and on the doped region 206. The material of the self-aligned metal telluride layer 212 is, for example, nickel telluride (NiSi _x ) or cobalt telluride (CoSi _x ). In an embodiment, a contact window (not shown) may be formed on the gate structure 204 and the doped region 206. Since the self-aligned metal telluride layer 212 is disposed, the resistance at the interface may be lowered.

The stressor layer 214 is disposed on the gate structure 204 and on the substrate 200. The stressor layer 214 can be a nitride film that provides compressive or tensile stress to the channel region. In one embodiment, a nitride film that causes tensile stress in the channel region is used for the NMOS, and a nitride film that causes compressive stress in the channel region is used for the PMOS. For a 90 nm technology node, the thickness of the stressor layer 214 will fall, for example, at 400. To 1000 In the range. In general, the thickness 210a of the spacer 210 is one of the main keys affecting the short channel effect. By thinning the thickness 210a of the spacer 210 to 50 To 200 In the range, the distance between the stress layer 214 and the channel region is shortened, thereby improving the component performance improved by the stress layer 214.

In particular, since the diffusion of the lightly doped region 208 under the gate structure 204 is independent of the diffusion of the doped region 206, the doping concentration of the doped region 206 may be heavy enough and deep enough to facilitate self-alignment. Formation of metal telluride layer 212. Furthermore, the spacer 210 can be thinned because the lightly doped region 208 has the first portion 208a. Since the thinner spacer 210 and the substrate 200 having the recessed surface help to provide the stressor layer 214 closer to the channel region under the gate structure 204, carrier mobility can be improved and component performance can be improved.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described using a cross-sectional schematic view. The process described below is only for the purpose of illustrating the process of the present invention in forming a semiconductor device as shown in FIG. 2, so that those skilled in the art can implement it, but are not intended to limit the scope of the present invention.

3A to 3E are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 3A, a substrate 300 having a first conductivity type is provided, which may be a P-type germanium substrate, a P-type epitaxial germanium substrate, or an insulating layer overlying a P-type semiconductor (SOI) substrate. A well area 302 of a first conductivity type is formed in the substrate 300, wherein the well area 302 is, for example, a P-type well area. In an embodiment, well zone 302 may be a profile that forms a very steep back-off (SSR) well.

Referring to FIG. 3B, a dielectric layer 304, a conductor layer 306, and a patterned hard mask layer 308 are sequentially formed on the substrate 300. The material of the dielectric layer 304 may be an oxide, a nitrided oxide, an oxynitride or a high-k material, wherein the high dielectric constant material is, for example, hafnium (Hf). And titanium oxide (TiO _x ), hafnium oxide (HfO _x ), hafnium oxynitride (HfSiON), hafnium oxide (HfAlO), or aluminum oxide (Al ₂ O ₃ ). The material of the conductor layer 306 may be metal, doped polysilicon, silicon-germanium or a combination of polysilicon and metal. Using the patterned hard mask layer 308 as a mask, a portion of the dielectric layer 304 and a portion of the conductor layer 306 are removed to define a gate structure 310 on the substrate 300. The patterned dielectric layer 304 acts as a gate dielectric layer and the patterned conductor layer 306 acts as a gate. In one embodiment, the length of the gate can be 90 nm or other smaller size, and the effective oxide thickness (EOT) of the gate dielectric layer can be about 20 To 35 Between to prevent the occurrence of leakage current.

Thereafter, a portion of the substrate 300 is removed to form a stepped upper surface 301. The method of removing a portion of the substrate 300 is performed by, for example, using a gate structure 310 as a mask to perform a sloped silicon etching process. In one embodiment, the tilt etch process can be wet etch using a suitable formulation comprising a plurality of acids. In another embodiment, the tilt 矽 etch process can also be plasma etch using a suitable combination of gases including CHF ₃ , CF ₄ , Ar, O ₂ . The stepped upper surface 301 is formed to include a first surface 301a, a second surface 301b, and a third surface 301c, wherein the third surface 301c connects the first surface 301a and the second surface 301b. The first surface 301a is, for example, a position corresponding to the gate structure 310. The second surface 301b that is lower than the first surface 301a may be substantially parallel to the first surface 301a. When the first surface 301a and the second surface 301b are substantially flat surfaces, the third surface 301c may be inclined to the first surface 301a. That is, the third surface 301c is a slope between the first surface 301a and the second surface 301b, wherein the upper edge of the slope connects the first surface 301a, and the lower edge of the slope connects the second surface 301b. In an embodiment, the height difference D ₁ between the first surface 301a and the second surface 301b is between 250. To 600 between. In an embodiment, the horizontal spacing D ₂ between the first surface 301a and the second surface 301b is between 250. To 350 between. In an embodiment, the extending direction of the first surface 301a and the third surface 301c form an angle ψ between 45° and 60°.

Referring to FIG. 3C, the patterned hard mask layer 308 is removed. Next, a spacer material layer 312 is formed on the substrate 300. The spacer material layer 312 is, for example, a gate structure 310, a second surface 301b, and a third surface 301c. In an embodiment, the thickness of the spacer material layer 312 is approximately 50 To 200 between. The material of the spacer material layer 312 includes an oxide, an oxynitride, a nitrided oxide, a nitride, or a combination of the above. The method of forming the spacer material layer 312 may be by a deposition process or a rapid thermal process (RTP), such as an in-situ steam generation (ISSG) oxidation process.

Accordingly, an implant process 314 is performed to form a second conductivity type (N-type) lightly doped region 316 on the substrate 300 on either side of the gate structure 310. The lightly doped region 316 is, for example, a bond in the substrate 300 as a source drain extension (SDE). The lightly doped region 316 may be formed using vertical implantation or implanted using a tilt angle and using low energy to form a shallow source drain extension (SDE) junction depth and use A sufficient dose is applied to reduce the sheet resistance. In one embodiment, when the gate length is about 90 nm and the spacer material layer 312 has a thickness of about 100 The implantation process 314 can be performed using an energy of 10 to 15 KeV and a dose of 5e ¹⁴ to 3e ¹⁵ cm ^-2 , and the dopant can be implanted with an inclination angle of 5 to 10 degrees. In an embodiment, when the component size is further reduced and the thickness of the spacer material layer 312 is thinned to 40 to 80 At the time, the energy of the implant process 314 can be reduced to 2-7 KeV.

It is noted that the implant process 314 can also be performed after the gate structure 310 is formed and before the spacer material layer 312 is formed. Taking a 90 nm technology node as an example, the implantation process 314 can be performed using a dose of 2 to 5 KeV and a dose of 5e ¹⁴ to 1e ¹⁵ cm ^-2 , and the dopant can be implanted vertically with a tilt angle of 0°. When the component size is further reduced, less energy is required to perform the implant process 314, and an energy of about 0.1 to 1 KeV can be used.

In addition, in an embodiment, after forming the stepped upper surface 301 or after forming the lightly doped region 316, a partial pouch of the first conductivity type (eg, P type) may be formed in the well region 302 (ring Implanted area or composite pocket (annular) implanted area. In another embodiment, a pocket (annular) implant region may also be formed in the well region 302 after forming the spacer material layer 312 and before forming the lightly doped region 316. That is, the well zone 302 can be a well with only a very steep retreat (SSR) well, or a combination of a very steep retreating well and a pocket (annular) implanted zone. A partial pocket (annular) implant region or a composite pocket (annular) implant region is formed, for example, under the gate structure 310, respectively, and adjacent to each of the doped regions that are pre-formed thereafter. The above-mentioned bag-shaped (annular) region may be formed by vertical implantation or by implantation at an inclination angle of 7 to 45 degrees.

Referring to FIG. 3D, a spacer 318 is formed on the sidewall of the gate structure 310. The spacers 318 cover a portion of the spacer material layer 312 to define subsequently formed pre-formed source and drain regions. The spacer 318 is used as a mask to remove a portion of the spacer material layer 312. The remaining spacer material layer 312 forms a spacer 312a, and each spacer 312a is disposed between the spacer 318 and the sidewall of the gate structure 310, respectively. The implant process 320 is performed to form doped regions 322 of the second conductivity type in the outer substrate 300 of the spacers 318, respectively. The doped region 322 is formed under the second surface 301b and electrically connected to the lightly doped region 316. The doped region 322 is, for example, an N+ doped region to serve as a source region and a drain region, respectively. After the spacers 318 are formed, the implant process 320 can be performed in a vertically implanted manner using energy above the implant process 314. The deep and heavy doped regions 322 can help reduce sheet resistance and make subsequent metal deuteration processes easier. In one embodiment, for a 90 nm technology node, implant process 320 can be performed using an energy of 10-20 KeV and a dose of 1e ¹⁵ ~ 3e ¹⁵ cm ^-2 .

Referring to FIG. 3E, a tempering process can also be performed to activate the dopant. In the 90nm technology node, the tempering process can be a general immersion (soak) tempering process or a spike tempering process. For smaller components, other advanced tempering techniques can be used, such as flash or laser tempering.

Thereafter, the spacers 318 are removed and a self-aligned metal telluride layer 324 is formed over the gate structures 310 and the doped regions 322. The material of the self-aligned metal telluride layer 324 may be nickel telluride (NiSi _x ) or cobalt telluride (CoSi _x ). In an embodiment, the self-aligned metal telluride layer 324 may be formed before or after the spacers 318 are removed. Next, a stress layer 326 is formed on the substrate 300 to complete the semiconductor element of the present invention. The stressor layer 326 can be a nitride film that provides compressive or tensile stress to the channel region. In this embodiment, the stressor layer 326 induces tensile stress in the channel region of the NMOS. In another embodiment, a nitride film that causes compressive stress in the channel region can serve as a stress layer for the PMOS. For a 90 nm technology node, the thickness of the stressor layer 326 is, for example, about 400. To 1000 between. It should be noted that the forming method and the forming sequence of the above-described self-aligned metal telluride layer 324, stress layer 326 and the like are well known to those skilled in the art, and thus the details thereof will not be described herein.

Referring again to FIG. 3E, each lightly doped region 316 disposed in the substrate 300 between the gate structure 310 and the doped region 322 includes an associated first portion 316a and second portion 316b to form a sloped and curved profile. . The first portion 316a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 316b is disposed under the third surface 301c, and the second portion 316b may further have a small portion extending below the first surface 301a. When the gate length is about 90 nm, the horizontal distribution of each lightly doped region 316 is, for example, about 400. To 600 between. In an embodiment, the length L ₁ of the first portion 316a is between 50 To 150 between. In an embodiment, the length L ₂ of the second portion 316b is between 300 To 700 between. It is to be noted that since the third surface 301c is an inclined surface, the inclination angle of each lightly doped region 316 is controlled within a range of 45 to 60 to maintain the breakdown characteristics of the element. The slanted and curved lightly doped region 316 has a lighter doping concentration on the surface, thereby reducing the hot carrier effect and reducing the gate-induced drain leakage without increasing the source-drain extension (SDE) resistance. The overlap capacitance between the current (GIDL) and the gate drain. During the tempering process, since the lightly doped region 316 has a sloped and curved profile, the diffusion of the lightly doped region 316 under the gate structure 310 is independent of the diffusion of the doped region 322, while the doped region 322 The doping concentration can be heavy enough and deep enough to facilitate the metal deuteration process. Moreover, since the spacer 312a is thin and conforms to the shape of the substrate 300, the stress layer 326 is closer to the channel region, and the component performance can be effectively improved.

4A through 4C are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with another embodiment of the present invention. It should be noted that the manufacturing flow shown in FIGS. 4A to 4C is the step subsequent to FIG. 3B. In FIGS. 4A to 4C, the same members as those in FIG. 3B are denoted by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 4A, the patterned hard mask layer 308 is removed. Next, a spacer 402 and a spacer 404 are formed on the sidewall of the gate structure 310 and the partial substrate 300. The curved spacers 402 can be formed using a disposable spacer 404. The spacers 402 are disposed between the spacers 404 and the sidewalls of the gate structure 310, respectively. The spacers 402 and the spacers 404 cover the third surface 301c and cover a portion of the second surface 301b, so the spacers 402 and the spacers 404 can be utilized to define the subsequently preformed source and drain regions.

Next, an implant process 406 is performed to form doped regions 408 of the second conductivity type in the outer substrate 300 of the spacers 404, respectively. The doped regions 408 formed under the second surface 301b are, for example, N+ doped regions to serve as a source region and a drain region, respectively. Implantation process 406 can be performed in a vertically implanted manner using energy above the source-drain extension (SDE). In one embodiment, for a 90 nm technology node, implant process 406 can be performed using a dose of 10-20 KeV and a dose of 1e ¹⁵ ~ 3e ¹⁵ cm ^-2 .

Referring to Figure 4B, the spacers 404 are removed. The implant process 410 is performed to form a second conductivity type (N-type) lightly doped region 412 in the substrate 300 on both sides of the gate structure 310. The lightly doped region 412 can be formed using vertical implantation or implanted using low energy and implanted at an oblique angle. In one embodiment, when the gate length is about 90 nm and the spacer 402 has a thickness of about 100 The implantation process 410 can be performed using an energy of 10 to 15 KeV and a dose of 5e ¹⁴ to 3e ¹⁵ cm ^-2 , and the dopant can be implanted with an inclination angle of 5 to 10 degrees. In an embodiment, when the component size is further reduced and the thickness of the spacer 402 is thinned to 40 to 80 At the time, the energy of the implant process 410 can be reduced to 2-7 KeV.

Referring to FIG. 4C, a tempering process can also be performed to activate the dopant. Thereafter, a self-aligned metal telluride layer 416 is formed over the gate structure 310 and the doped region 408. Next, a stress layer 418 is formed on the substrate 300 to complete the semiconductor element of the present invention. As shown in FIG. 4C, each lightly doped region 412 disposed in the substrate 300 between the gate structure 310 and the doped region 408 includes a first portion 412a and a second portion 412b, wherein the first portion 412a is coupled to the second portion 412b. . The first portion 412a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 412b is disposed under the third surface 301c, and the second portion 412b may further have a small portion extending below the first surface 301a. When the length of the gate is about 90 nm, the horizontal distribution of each lightly doped region 412 may be between about 400. To 600 between. In an embodiment, the length L ₁ of the first portion 412a is between 50 To 150 between. In an embodiment, the length L ₂ of the second portion 412b is between 300 To 700 between. Specifically, since the third surface 301c is an inclined surface, the inclination angle of each of the lightly doped regions 412 can be controlled within a range of 45 to 60 to maintain the breakdown characteristics of the element.

5A to 5C are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with still another embodiment of the present invention. It should be noted that the manufacturing flow shown in FIGS. 5A to 5C is the step subsequent to FIG. 3B. In FIGS. 5A to 5C, the same members as those in FIG. 3B are denoted by the same reference numerals and the description thereof will be omitted.

Referring to FIG. 5A, the patterned hard mask layer 308 is removed. Next, a spacer 502 and a spacer 504 are formed on the sidewall of the gate structure 310 and the partial substrate 300. The spacer 502 having a curved profile is formed, for example, by a disposable spacer 504. The spacers 502 are disposed between the spacers 504 and the sidewalls of the gate structure 310, respectively. The spacers 502 and spacers 504 cover the third surface 301c and cover a portion of the second surface 301b, and can be used to define subsequent pre-formed source drain extensions (SDEs), source regions, and drain regions.

Referring to FIG. 5B-1, the spacer 504 is removed. An implant process 506 is performed to form a second conductivity type (N-type) lightly doped region 508 and a doped region 509a in the substrate 300 on both sides of the gate structure 310. The lightly doped region 508 is formed, for example, under the spacer 502, and the doped region 509a is formed, for example, on the outer side of the spacer 502.

Referring to FIG. 5B-2, in another embodiment, the implantation process 507 can be selectively performed using low energy to form a second conductivity type (N type) in the substrate 300 on both sides of the gate structure 310. The region 509b is doped to make the source drain (SD) diffusion region deeper. The doping region 509b is formed, for example, in the range of the doping region 509a. It is noted that the present invention does not impose any limitation on the order in which the implant process 506 and the implant process 507 are performed, that is, the order in which the implant process 506 and the implant process 507 are performed may be reversed.

In view of the above, the shallow source drain extension (SDE) region and the source drain (SD) diffusion region may be formed simultaneously using a suitable implantation process using a suitable energy, or a double implantation process to implant the dopant. The substrate 300 was implanted twice. In one embodiment, as shown in FIG. 5B-1, in a single implantation process to simultaneously form the lightly doped region 508 and the doped region 509a, the lightly doped region is covered by the spacer 502 over the substrate 300. 508 will form a shallow junction; due to the absence of shadowing of the spacers 502, the doped regions 509a will form a deeper junction. With a technology node of 90 nm and the thickness of the spacer 502 is about 100 For example, a single implantation process can be performed using an energy of about ¹⁵ KeV and a dose of 1e ¹⁵ to 3e ¹⁵ cm ^-2 , and the doping is implanted using a tilt angle of 5° to 10°, so that it can be simultaneously formed. The required joint profile.

In one embodiment, during the two-step implantation process to form the lightly doped region 508 and the doped regions 509a, 509b, the lightly doped region 508 and the doped region 509a may be simultaneously formed by the implantation process 506 ( As shown in Fig. 5B.1; and due to the shielding effect of the spacers 502, the additional implantation of the lower energy 507 only increases the doping concentration of the doped regions 509b (as shown in Fig. 5B-2). With a technology node of 90 nm and the thickness of the spacer 502 is about 100 For example, the implantation process 506 can be performed using an energy of about ¹⁵ KeV and a dose of 1e ¹⁵ to 3e ¹⁵ cm ^-2 while forming the lightly doped region 508 and the doped region 509a, wherein a tilt angle of 5° to 10° is used. To implant the dopant. Under the same conditions as above, the implantation process 507 can be performed using an energy of about 5 to 10 KeV and a dose of 1e ¹⁵ to 3e ¹⁵ cm ^-2 to increase the doping concentration of the doping region 509b.

Referring to FIG. 5C, after the implant process 506 is performed or after the implant process 507 is performed, a tempering process can also be performed to activate the dopant, thereby forming the doped region 509. Thereafter, a self-aligned metal telluride layer 510 is formed over the gate structure 310 and the doped region 509. Next, a stress layer 512 is formed on the substrate 300 to complete the semiconductor element of the present invention. As shown in FIG. 5C, each lightly doped region 508 disposed in the substrate 300 between the gate structure 310 and the doped region 509 includes a first portion 508a and a second portion 508b, wherein the first portion 508a is coupled to the second portion 508b. . The first portion 508a is disposed under the second surface 301b and adjacent to the third surface 301c. The second portion 508b is disposed under the third surface 301c and optionally includes a small portion of the region extending below the first surface 301a. When the length of the gate is about 90 nm, the horizontal distribution of each lightly doped region 508 is, for example, about 400. To 600 between. In an embodiment, the length L ₁ of the first portion 508a is between 50 To 150 between. In an embodiment, the length L ₂ of the second portion 508b is between 300 To 700 between. Specifically, since the third surface 301c is an inclined surface, the inclination angle of each lightly doped region 508 can be controlled within a range of 45 to 60 to maintain the breakdown characteristics of the element.

In order to confirm that the semiconductor device of the present invention can effectively improve the device performance, the characteristics of the experimental example will be described next. The following description of the experimental examples is merely for explaining the structural configuration of the semiconductor device of the present invention for the lateral electric field. The effects are not intended to limit the scope of the invention.

Experimental example

FIG. 6 is a graph showing the transverse electric field distribution corresponding to different positions in the channel region parallel to the first surface of the NMOS according to the conventional NMOS and the experimental example of the present invention.

As shown in FIG. 6, the transverse electric field distribution of the conventional NMOS and the NMOS proposed by the present invention in the channel region close to the interface between the gate structure and the germanium substrate are respectively simulated. The NMOS of the conventional NMOS and the NMOS of the experimental example of the present invention has a gate length of about 90 nm. In the case where the same bias voltage is supplied to two elements, respectively, the transverse electric field distribution of the conventional NMOS is much higher than the transverse electric field distribution of the NMOS of the experimental example of the present invention. Since the transverse electric field significantly affects the hot carrier effect, conventional NMOSs with higher transverse electric fields experience severe hot carrier effects, resulting in reduced component performance. It can be seen that the NMOS structure proposed by the present invention has a lower transverse electric field value, thereby achieving the effect of improving the performance of the component.

In summary, the semiconductor device of the present invention includes a lightly doped region having a first portion and a second portion, and the obliquely and curved lightly doped region can reduce the hot carrier without reducing the dopant concentration of the lightly doped region. effect. Moreover, by making the lightly doped region have an inclined and curved profile, it is also possible to reduce leakage current such as gate-induced drain leakage current (GIDL) and overlap capacitance between gate and drain.

Further, the method of fabricating the semiconductor device of the present invention utilizes a disposable spacer to form a sloped and curved lightly doped region, which can be easily integrated into an existing process. Therefore, the process is simple without increasing the manufacturing cost, and the formed components also have better performance. Furthermore, the method of manufacturing a semiconductor device of the present invention can be applied to all MOS device structures, even if the device size is reduced to MOS devices having a size of 90 nm or less.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300. . . Base

102, 204, 310. . . Gate structure

104, 210, 312a, 318, 402, 404, 502, 504. . . Clearance wall

106. . . Offset spacer

108a. . . Source area

108b. . . Bungee area

110a. . . Source extension

110b. . . Bungee extension

112. . . Self-aligned metal telluride

201, 301. . . Stepped upper surface

201a, 301a. . . First surface

201b, 301b. . . Second surface

201c, 301c. . . Third surface

202, 302. . . Well area

204a. . . Gate

204b. . . Gate dielectric layer

206, 322, 408, 509, 509a, 509b. . . Doped region

208, 316, 412, 508. . . Lightly doped area

208a, 316a, 412a, 508a. . . first part

208b, 316b, 412b, 508b. . . the second part

210a. . . thickness

212, 324, 416, 510. . . Self-aligned metal telluride layer

214, 326, 418, 512. . . Stress layer

304. . . Dielectric layer

306. . . Conductor layer

308. . . Patterned hard mask layer

312. . . Gap material layer

314, 520, 406, 410, 506, 507. . . Implantation process

D ₁ . . . Height difference

D ₂ . . . Horizontal spacing

L ₁ , L ₂ . . . length

Hey. . . Angle

1 is a schematic cross-sectional view of a conventional MOS transistor.

2 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

3A to 3E are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with an embodiment of the present invention.

4A through 4C are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with another embodiment of the present invention.

5A to 5C are schematic cross-sectional views showing a manufacturing process of a semiconductor device in accordance with still another embodiment of the present invention.

FIG. 6 is a graph showing the transverse electric field distribution corresponding to different positions in the channel region parallel to the first surface of the NMOS according to the conventional NMOS and the experimental example of the present invention.

200. . . Base

201. . . Stepped upper surface

201a. . . First surface

201b. . . Second surface

201c. . . Third surface

202. . . Well area

204. . . Gate structure

204a. . . Gate

204b. . . Gate dielectric layer

206. . . Doped region

208. . . Lightly doped area

208a. . . first part

208b. . . the second part

210. . . Clearance wall

210a. . . thickness

212. . . Self-aligned metal telluride layer

214. . . Stress layer

D ₁ . . . Height difference

D ₂ . . . Horizontal spacing

L ₁ , L ₂ . . . length

Hey. . . Angle

Claims (20)

A semiconductor device comprising: a substrate having a stepped upper surface, wherein the stepped upper surface includes a first surface, a second surface lower than the first surface, and the first surface and the second surface a third surface; a gate structure disposed on the first surface; two doped regions disposed in the substrate on both sides of the gate structure and under the second surface; and two lightly doped The regions are respectively disposed in the substrate between the gate structure and the doped regions, wherein each of the lightly doped regions comprises: a first portion under the second surface, and the doped regions are not Overlapping; and a second portion connecting the first portion and located below the third surface. The semiconductor device of claim 1, wherein the third surface is inclined to the first surface, and an angle between the extending direction of the first surface and the third surface is between 45° and 60°. between. The semiconductor component of claim 1, wherein the first surface is substantially parallel to the second surface. The semiconductor device of claim 1, wherein a height difference between the first surface and the second surface is between 250 Å and 600 Å, and between the first surface and the second surface The horizontal spacing is between 250 Å and 350 Å. The semiconductor component of claim 1, wherein The length of the first portion of each of the lightly doped regions is between 50 Å and 150 Å, and the length of the second portion is between 300 Å and 700 Å. The semiconductor device of claim 1, further comprising a spacer disposed on the sidewall of the gate structure and located on the lightly doped regions, the spacer having a thickness of 50 Å to 200 Å between. The semiconductor device according to claim 1, further comprising a stress layer disposed on the substrate. The semiconductor component of claim 1, further comprising a two-pocket (annular) implanted region disposed in the substrate under the gate structure, each of the pocket-shaped (annular) implanted regions Adjacent to each of the doped regions, wherein the pocket (annular) implant regions are localized pocket (annular) implant regions or multiple pocket (annular) implants Area. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a gate structure on the substrate; removing a portion of the substrate to form a first-order upper surface, wherein the stepped upper surface includes a first surface, lower than a second surface of the first surface, connecting the first surface and a third surface of the second surface; forming two lightly doped regions in the substrate on both sides of the gate structure, wherein each of the lightly doped regions The impurity region includes: a first portion formed under the second surface; and a second portion connecting the first portion and formed under the third surface; and forming two doped regions in the substrate, The doped regions are located in the second table The lightly doped regions are subsurface and respectively adjacent to each other, wherein the first portion of each of the lightly doped regions does not overlap with the doped regions. The method of manufacturing a semiconductor device according to claim 9, wherein the third surface is inclined to the first surface, and an angle between the extending direction of the first surface and the third surface is between 45° and Between 60°. The method of fabricating a semiconductor device according to claim 9, wherein the first surface is substantially parallel to the second surface. The method of manufacturing a semiconductor device according to claim 9, wherein a height difference between the first surface and the second surface is between 250 Å and 600 Å, and the first surface and the second surface The horizontal spacing between the surfaces is between 250 Å and 350 Å. The method of fabricating a semiconductor device according to claim 9, wherein the length of the first portion of each of the lightly doped regions is between 50 Å and 150 Å, and the length of the second portion is between 300 Between Å and 700 Å. The method of manufacturing the semiconductor device of claim 9, further comprising forming a first spacer on the sidewall of the gate structure and the lightly doped regions, the thickness of the first spacer being between Between 50 Å and 200 Å. The method of fabricating a semiconductor device according to claim 14, wherein the method of forming the first spacer comprises: forming a spacer material layer on the substrate; forming a second on the sidewall of the gate structure Gap, where the first The second spacer covers a portion of the spacer material layer on the lightly doped regions; the portion of the spacer material layer is removed by the second spacer as a mask; and the second spacer is removed. The method of fabricating a semiconductor device according to claim 15, wherein the doping regions are formed by using the second spacer as a mask after removing a portion of the spacer material layer. The method of fabricating a semiconductor device according to claim 15, wherein the lightly doped regions are formed before the second spacer is formed or after the second spacer is removed. The method of fabricating a semiconductor device according to claim 14, wherein the lightly doped regions and the doped regions are formed by a single process or a two-step process after the first spacers are formed. The method for fabricating a semiconductor device according to claim 9, further comprising forming a stress layer on the substrate. The method for fabricating a semiconductor device according to claim 9 is further included in the gate after forming the stepped upper surface or after forming the lightly doped regions or before forming the lightly doped regions a two-pocket (annular) implanted region is formed in the base under the pole structure, and each of the pocket-shaped (annular) implanted regions is adjacent to each of the doped regions, wherein the pockets (rings) The implanted area is a localized pocket (annular) implanted area or a multiple pocket (annular) implanted area.