TWI396434B - Unit cell and clamp circuit of an image sensor - Google Patents

Description

Pixel unit and clamp circuit of image sensor

The present invention relates to a complementary metal oxide semiconductor (CMOS) image sensor, and more particularly to a CMOS image sensor that can increase the photosensitive area.

A complementary metal oxide semiconductor (CMOS) image sensor is an electronic device for capturing images that converts light intensity into electrical charge, converts it to a voltage, and reads it out. The first figure shows a pixel unit of a conventional four-cell (4T) image sensor, which comprises a photodiode D and four transistors - M _tx , M _rst , M _sf , M _sel . When the reset transistor _Mrst is turned on by the reset signal R, a voltage reset can be performed. The source follower M _sf can be used to buffer or amplify the integrated optical signal of the photodiode D. When the transfer transistor M _tx is turned on by the transfer signal T, it can be used to transfer the accumulated optical signal of the photodiode D. When the selection transistor M _sel is turned on by the word line signal WL, the optical signal is allowed to be read from the bit line BL.

Conventional 4T pixel cells take up a considerable amount of wafer area and are therefore not suitable for modern high-density CMOS image sensors. In view of this, it is urgent to propose a novel CMOS image sensor for effectively reducing the area of the CMOS image sensor or increasing the photosensitive area.

In view of the above, one of the objects of embodiments of the present invention is to provide a complementary metal oxide semiconductor (CMOS) image sensor having the function of a conventional 4T pixel unit, but omitting the selection of a transistor, thereby increasing the photosensitive area. Still further, in accordance with another feature of an embodiment of the present invention, a clamp is used to improve the dark sun phenomenon that occurs when detecting intense light.

A pixel unit of an image sensor according to an embodiment of the invention includes a transfer gate, a source follower, a reset transistor, and a photodetector. The reset transistor is controlled by a word line switch and the output is connected to a floating diffusion (FD) to control the source follower. The photodetector transmits an optical signal to the bit line by transmitting a gate and a source follower. In an embodiment, the first power source generates a second power source via the power switch to provide power to the reset transistor and the source follower. In another embodiment, the first power source provides power to the source follower, and the first power source generates a second power source via the regulator, which provides power to the reset transistor via the second power switch.

A clamp circuit of an image sensor according to an embodiment of the invention includes a first power source, a second power source, a clamper, and a bias transistor. The second power source generates the first power source by the power switch. The clamp is controlled by the clamp voltage. A biasing transistor and a clamp are connected in series between the second power source and ground. Wherein, the node between the clamp and the bias transistor is electrically connected to the one-dimensional line. In another embodiment, the second power source generates the first power source by a regulator. In addition, a second power switch is included to periodically sample and hold the first power source to provide to the regulator. The clamp is controlled by the clamping voltage, which is obtained by adjusting the second power source. In yet another embodiment, a replica element is further included, the constituent elements of which correspond to a clamper and a biasing transistor, the internal node of the replica element providing a feedback voltage. In addition, a comparator is included that compares a reference voltage with the feedback voltage to provide a clamp voltage to the clamp.

20‧‧‧ pixel unit

21‧‧‧ character line switch

22‧‧‧Power switch

23‧‧‧Constant current source

30‧‧‧pixel unit

31‧‧‧Regulator

32‧‧‧Power switch

33‧‧‧Constant current source

40‧‧‧pixel unit

41‧‧‧Copying components

42‧‧‧ comparator

43‧‧‧Multiplexer (MUX)

44‧‧‧ Bandgap current source

D‧‧‧Photoelectric diode

M _rst ‧‧‧Reset transistor

M _sf ‧‧‧Source follower

M _tx ‧‧‧Transmission transistor

M _sel ‧‧‧Selected crystal

R‧‧‧Reset signal

T‧‧‧ transmit signal

BL‧‧‧ bit line

WL‧‧‧ character line

RST‧‧‧Reset transistor

SF‧‧‧Source follower

TX‧‧‧Transmission gate

FD‧‧‧Floating diffusion zone

PD‧‧‧Photodetector (photodiode)

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

AVDD‧‧‧first power supply

PVDD‧‧‧second power supply

CDS‧‧‧ Associated Double Sampling

CLAMP‧‧‧ clamp

CLAMP_ADJ‧‧‧Clamp adjustment resistor

CLAMP_EN‧‧‧Clamp enable switch

BIAS‧‧‧bias transistor

BIAS_SH‧‧‧ bias switch

FDVDD‧‧‧second power supply

FDVDD_ADJ‧‧‧Second power adjustment resistor

FDVDD_SH‧‧‧Second power switch

The first figure shows a pixel unit of a conventional four-cell (4T) image sensor.

Figure 2A shows a complementary metal oxide semiconductor (CMOS) image sensor of the first embodiment of the present invention.

The second B diagram shows the main signal waveform of the second A picture.

The third figure shows a CMOS image sensor of a second embodiment of the present invention.

The fourth figure shows a CMOS image sensor of a third embodiment of the present invention.

Figure 2A shows a complementary metal oxide semiconductor (CMOS) image sensor of the first embodiment of the present invention. For ease of explanation, only the main circuit architectures associated with embodiments of the present invention are shown.

In the present embodiment, each of the pixel units 20 includes a photodetector (eg, a photodiode) PD, a transfer gate TX, a reset transistor RST, and a source follower SF. Compared with the conventional four-cell (4T) pixel unit, the present embodiment omits the selection of the transistor, thereby increasing the photosensitive area, but still functions as a conventional 4T pixel unit. Wherein, the drain D of the reset transistor (eg, N-type MOS transistor) RST is electrically connected to the drain D of the source follower (eg, N-type MOS transistor) SF; the source of the reset transistor RST S is electrically connected to the gate of the source follower SF (ie, the floating diffusion FD); the gate G of the reset transistor RST is connected to the word line, which is connected by the word line switch 21 Controlled; the anode of the photodiode PD is grounded, and the cathode is electrically connected to the floating diffusion FD by the transfer gate TX; the source S of the source follower SF is connected to the bit line, and then Further connected to a correlated double sampling (CDS) circuit.

In this embodiment, the first power source AVDD generates a second power source PVDD via a power switch 22, which can be controlled to switch to a high level or a low level. The second power supply PVDD supplies power to the reset transistor RST and the drain D of the source follower SF.

The second B diagram shows the main signal waveform of the second A picture. First, at times t1 and t2 In between, the second power source PVDD is turned off to be at a low level, and all columns of the reset transistor RST are turned on by the column word line switches 21 of all columns, thereby making the gates G of all the source followers SF Is discharged to a low level. Subsequently, the second power source PVDD is turned on to a high level. Then, between time t3 and time t4, the reset transistor RST and the transfer gate TX of the column to be read are turned on to reset the corresponding photodiode PD. Subsequently, the photodiode PD is subjected to photodetection.

Between time t5 and t6, the reset transistor RST of the column to be read is turned on to reset the floating diffusion FD, and the first sample hold (sample/hold) is performed by the correlated double sampling (CDS) circuit. . Next, between time t7 and t8, the transfer gate TX of the column to be read is turned on, and the detection voltage of the photodiode PD is transmitted to the correlated double sampling (CDS) circuit for the second sample hold. By correlating double sampling (CDS), the difference between each pixel can be compensated for. According to the above operation control, the photodetection voltage of each column can be sequentially read as in the conventional 4T pixel unit, but the selection transistor of the conventional 4T pixel unit is not required.

When the pixel unit 20 (or the conventional pixel unit) detects the strong light (for example, sunlight), the floating diffusion region FD may be discharged before the transfer gate TX is turned on, causing a subsequent reading error, so that the original pole The bright area will be partially darkened, generally called the dark sun or black sun phenomenon.

In order to improve the darkening problem, the embodiment further includes a clamp (for example, an N-type MOS transistor) CLAMP, which is connected in series with a bias transistor (for example, an N-type MOS transistor) BIAS between the second power source PVDD and the ground. And the node between the clamper CLAMP and the bias transistor BIAS is electrically connected to the bit line (that is, the source S of the source follower SF). In addition, a clamp enable switch CLAMP_EN can be connected in series, when it is closed, the clamp function is turned on; when it is open, the clamp function is turned off. The above clamp CLAMP can also be used in combination with a conventional pixel unit, for example, 4T pixel unit.

The gate G of the clamp CLAMP is connected to the clamp adjustment resistor CLAMP_ADJ to receive the clamp voltage, and the current flowing through the clamp adjustment resistor CLAMP_ADJ is supplied from the constant current source 23. Since the voltage drop across the clamp adjustment resistor CLAMP_ADJ is a fixed value, the darkening phenomenon can be avoided when the pixel unit 20 is read.

The pixel unit 20 of the first embodiment described above is required to discharge before reading each column, which causes power consumption, and the frame rate cannot be improved. Further, with the clamp CLAMP of the first embodiment described above, when the first power source AVDD is varied, the clamp voltage received by the gate of the clamper CLAMP is a fixed value. In other words, the clamp CLAMP cannot dynamically track the fluctuation of the first power supply AVDD.

In view of this, the second embodiment of the present invention proposes a complementary metal oxide semiconductor (CMOS) image sensor for improving the above problems. As in the first embodiment, the pixel unit 30 and the clamp CLAMP of the present embodiment can also be used independently.

The pixel unit 30 of the present embodiment has the same constituent elements as the pixel unit 20 of the previous embodiment, except that in the present embodiment, the first power source AVDD is generated by the regulator 31 to generate the second power source FDVDD. In the present embodiment, the regulator 31 includes an operational amplifier having an inverting input connected to the output, and the non-inverting input receiving the regulated voltage provided by the second power regulating resistor FDVDD_ADJ. Furthermore, the adjustment voltage is sampled and held according to the frame period via the second power switch FDVDD_SH. Thereby, since the regulator 31 samples the first power source AVDD at a fixed time, the generated second power source FDVDD can track the fluctuation of the first power source AVDD. Further, since the regulator 31 is maintained at a fixed value during the same frame period, no noise is generated due to the fluctuation of the first power source AVDD.

In the present embodiment, the second power source FDVDD is supplied with power to the drain D of the reset transistor RST via the power switch 32, so that the floating transistor FD is reset when the reset transistor RST is turned on during the reset period. It is the level of the second power supply FDVDD. In addition, the first power supply AVDD provides power to the drain D of the source follower SF. Compared with the previous embodiment, this embodiment does not need to discharge the entire image sensor array before each reading; instead, it only needs to be turned on by the word line switch 21 for the column to be read. The transistor RST is supplied with power to the reset transistor RST by the power switch 32. Therefore, power is saved and the frame rate is increased.

The circuit configuration of the clamp CLAMP of this embodiment is similar to that of the previous embodiment. The difference is that the gate G of the clamp CLAMP of the embodiment receives the second power supply FDVDD and is adjusted via the clamp adjustment resistor CLAMP_ADJ. Clamping voltage. The current flowing through the clamp adjustment resistor CLAMP_ADJ is supplied from the constant current source 33 via a mirror. Since the second power supply FDVDD of the embodiment can follow the fluctuation of the first power supply AVDD, the clamp voltage of the clamp CLAMP of the embodiment can also follow the fluctuation of the first power supply AVDD. In addition, this embodiment also uses a bias switch BIAS_SH, which is sampled and held according to the frame period. Its operation and function are similar to the aforementioned second power switch FDVDD_SH.

The fourth figure shows a complementary metal oxide semiconductor (CMOS) image sensor of a third embodiment of the present invention. The pixel unit 40 and the clamper CLAMP of the present embodiment can be used independently. This embodiment is similar to the second embodiment, except that in the present embodiment, the corresponding replica element 41 is added to the clamper CLAMP, the clamp enable switch CLAMP_EN and the bias transistor BIAS, and then compared. The comparator 42 compares a reference voltage with a feedback voltage of a node inside the replica element 41 (for example, a node voltage between the clamper CLAMP and the clamp enable switch CLAMP_EN). Thereby, the difference between the clamps CLAMP of each row can be compensated. In the present embodiment, the inverting input of the comparator 42 receives the feedback voltage, while the non-inverting input inputs the precision voltage generated by the bandgap current source 44 via the multiplexer (MUX) 43. (also That is, the voltage drop across the resistor).

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

21‧‧‧ character line switch

30‧‧‧pixel unit

31‧‧‧Regulator

32‧‧‧Power switch

33‧‧‧Constant current source

BL‧‧‧ bit line

WL‧‧‧ character line

RST‧‧‧Reset transistor

SF‧‧‧Source follower

TX‧‧‧Transmission gate

FD‧‧‧Floating diffusion zone

PD‧‧‧Photodetector (photodiode)

S‧‧‧ source

D‧‧‧汲

G‧‧‧ gate

AVDD‧‧‧first power supply

CDS‧‧‧ Associated Double Sampling

CLAMP‧‧‧ clamp

CLAMP_ADJ‧‧‧Clamp adjustment resistor

CLAMP_EN‧‧‧Clamp enable switch

BIAS‧‧‧bias transistor

BIAS_SH‧‧‧ bias switch

FDVDD‧‧‧second power supply

FDVDD_ADJ‧‧‧Second power adjustment resistor

FDVDD_SH‧‧‧Second power switch

Claims (22)

A pixel unit of an image sensor, comprising: a transfer gate; a source follower; a reset transistor controlled by a word line switch, the output of the reset transistor being connected to the floating diffusion region ( FD) for controlling the source follower; and a photodetector for transmitting an optical signal to the bit line by the transfer gate and the source follower; wherein a first power source is generated via a power switch a second power source for supplying power to the reset transistor and the source follower. The pixel unit of the image sensor of claim 1, wherein the image sensor is a complementary metal oxide semiconductor (CMOS) image sensor. The pixel unit of the image sensor according to claim 1, wherein the photodetector is a photodiode. The pixel unit of the image sensor of claim 1, wherein the reset transistor and the source follower are N-type MOS transistors. The pixel unit of the image sensor of claim 4, wherein the reset transistor has a drain electrically connected to the drain of the source follower and is connected to the second power source; a source of the transistor is electrically connected to the gate of the source follower and the floating diffusion; the gate of the reset transistor is connected to a word line, which is controlled by the word line switch; The anode of the photodetector is grounded, and the cathode is electrically connected to the floating diffusion region by the transfer gate; the source of the source follower is connected to the bit line, and then connected to an associated double sampling (CDS) circuit . A pixel unit of an image sensor, comprising: a transfer gate; a source follower; a reset transistor controlled by a word line switch, the output of the reset transistor being coupled to a floating diffusion (FD) to control the source follower And a photodetector for transmitting an optical signal to the bit line by the transfer gate and the source follower; wherein a first power source supplies power to the source follower; the first power source is a regulator generates a second power source that is variable with the first power source, and supplies power to the reset transistor via a second power switch, when a plurality of the pixel units are connected in series, by selectively Controlling the level of the second power source and selectively turning on the reset transistor and the transfer gate to be read to reset the corresponding photodetector for photodetection. The pixel unit of the image sensor of claim 6, wherein the image sensor is a complementary metal oxide semiconductor (CMOS) image sensor. The pixel unit of the image sensor of claim 6, wherein the photodetector is a photodiode. The pixel unit of the image sensor of claim 6, wherein the reset transistor and the source follower are N-type MOS transistors. The pixel unit of the image sensor of claim 9, wherein the reset transistor is electrically connected to the output of the second power switch; the source of the reset transistor is electrically connected to The gate of the source follower and the floating diffusion; the gate of the reset transistor is connected to the word line, which is controlled by the word line switch; the anode of the photodetector is grounded, and the cathode is Electrically connecting to the floating diffusion region by the transfer gate; the source of the source follower is connected to the bit line, and then connected to an associated double sampling (CDS) circuit; the drain of the source follower Connected to the first power source. A clamp circuit for an image sensor, comprising: a first power source and a second power source, wherein the second power source generates the first power source by a power switch; and a clamp device controlled by a clamp a bit voltage; and a constant current source; a clamp adjustment resistor connected to the clamp, and a current flowing through the clamp adjustment resistor is provided by the constant current source; and a bias transistor, and the The clamp is connected in series between the second power source and the ground; wherein the node between the clamp and the bias transistor is electrically connected to the one bit line. The clamp circuit of the image sensor according to claim 11, wherein the clamp is an N-type MOS transistor, and the gate receives the clamp voltage. The clamp circuit of the image sensor of claim 12, wherein the clamp adjustment resistor is electrically connected to the gate of the clamp. The clamp circuit of the image sensor of claim 11, further comprising a clamp enable switch connected in series to the clamp and the bias transistor, when the clamp enable switch is closed When the clamp function of the clamp is turned on, when the clamp enable switch is turned off, the clamp function of the clamp is turned off. A clamp circuit of an image sensor includes: a first power source and a second power source, wherein the second power source generates the first power source by a regulator; and a second power switch periodically The first power source is sampled and held for supply to the regulator; a clamper is controlled by a clamp voltage obtained by adjusting the second power source; and a certain current source; a clamp adjustment resistor connected to the clamp, and a current flowing through the clamp adjustment resistor is provided by the constant current source through a mirror; and a bias transistor, and the clamp The device is connected in series between the second power source and the ground; wherein a node between the clamp and the bias transistor is electrically connected to a one-dimensional line. The clamp circuit of the image sensor according to claim 15, wherein the clamp is an N-type MOS transistor, and the gate receives the clamp voltage. The clamp circuit of the image sensor of claim 16, wherein the clamp adjustment resistor is electrically connected to the gate of the clamp. The clamp circuit of the image sensor of claim 15, further comprising a clamp enable switch connected in series with the clamp and the bias transistor, when the clamp enable switch is closed When the clamp function of the clamp is turned on, when the clamp enable switch is turned off, the clamp function of the clamp is turned off. A clamp circuit of an image sensor includes: a first power source and a second power source, wherein the second power source generates the first power source by a regulator; and a second power switch periodically a first power source is sampled and held for supply to the regulator; a clamper is controlled by a clamp voltage; a biasing transistor is coupled in series with the clamper between the second power source and the ground; a replica component having a component corresponding to the clamp and the bias transistor, an internal node of the replica component providing a feedback voltage; and a comparator comparing a reference voltage and the feedback voltage for The clamping voltage is provided to the clamp; wherein a node between the clamp and the bias transistor is electrically connected to a bit line. The clamp circuit of the image sensor according to claim 19, wherein the clamp is an N-type MOS transistor, and the gate receives the clamp voltage. The clamp circuit of the image sensor according to claim 20, wherein the reference voltage is generated by a bandgap current source flowing through the resistor. The clamp circuit of the image sensor according to claim 19, further comprising a clamp enable switch connected in series to the clamp and the bias transistor, when the clamp enable switch is closed When the clamp function of the clamp is turned on, when the clamp enable switch is turned off, the clamp function of the clamp is turned off.