TWI394168B - Memory test method - Google Patents

Description

Memory test method

The invention relates to a method for testing a memory, in particular to test a memory using a built-in controller with a test function.

Flash memory is currently the most popular storage medium and is widely used in embedded systems. Flash memory is a solid, non-volatile, rewritable memory that operates like a mixture of random access memory and hard disk. Just like DRAM, flash memory stores data bits in memory units, but when the power is turned off, the data remains on the memory. Due to its high speed, long-lasting, and low voltage requirements, flash memory is ideal. Used in many devices, such as digital cameras, mobile phones, printers, palmtops, pagers, and tape recorders.

Referring to the first figure, a schematic diagram of a conventional memory test system. As shown in the first figure, the memory test system 1 includes a test computer 10 and a sorting board 20, wherein the test computer 10 is connected to the screening board 20 through a transmission interface, and the transmission interface can be a universal serial bus ( Universal Serial Bus, USB) interface. The screening board 20 includes a controller 30 and a memory 40. Typically, the controller 30 is a control chip or a control module having a control chip. The test computer 10 issues a test command and test data, which is received by the controller 30 and written to the memory 40, or the memory 40 is read by the controller 30 and transmitted back to the test computer 10, and the test computer 10 performs data comparison to confirm the memory. It is normal and records the test results, including the address of the damaged block and the total number of damaged blocks.

Referring to the second figure, a flow chart of a memory test of a conventional technique. As shown in the second figure, the test of the memory starts with step S10, and then proceeds to step S12. In step S12, the test computer issues a test command, and proceeds to step S14. In step S14, the test computer generates test data and transmits it to the controller, and proceeds to step S16. In step S16, the controller writes the test data into the memory, and proceeds to step S18. In step S18, the test computer issues a read command, and proceeds to step S20. In step S20, the controller reads the stored data in the memory and transmits it to the test computer, and proceeds to step S22. In step S22, the test computer pairs the test data and the received stored data, and proceeds to step S24. In step S24, the computer record comparison result is tested, and the process proceeds to step S26. In step S26, if the test of all the memories is completed, the process proceeds to step S30, and the operation is ended, otherwise the process returns to step 14.

The above test operations are classified into low-order comparison methods according to the classification of test data, and rely heavily on the test program of the test computer and the efficiency of the test computer, because the test system is on the memory when writing and reading data. The access operation is quite frequent. In addition to the generation of test data and the comparison of data after reading the memory data, it is necessary to test a large amount of arithmetic processing of the computer. Therefore, the industry does not want to find a satisfactory balance between how to balance the correctness of screening and the efficiency of scanning.

However, the disadvantage of performing a memory scan test in a low-order alignment mode is that the central processing unit of the test computer is often in a highly loaded state and has frequent access to the memory.

Another type of test method is the high-order comparison method. The test file is written into the memory through the controller through the test computer, and then stored and stored from the memory. The file is compared with the test file. In this way, the memory is read and written by the access of a specific file in a systematic logical point of view. The data of the file is divided and written into the memory and read and compared for comparison, so that the memory can be tested. Whether it is normal, and the access frequency to the memory has been greatly reduced relative to the low-order comparison method.

However, the high-order comparison test relies entirely on the test computer, so although it is beneficial to develop a highly efficient test program for screening tests and easy to understand the comparison results, it is impossible to accurately grasp the low-order comparison method. The function of the memory block status.

Especially in recent years, the volume of memory wafers has been shrinking, internal circuit design has become increasingly complex and requires fast operation, so the stability of memory particles has become a major challenge for the semiconductor industry. If the characteristics of the memory cannot be known in advance, the quality and credibility of the particles are often degraded. How to save the stability of memory particles into an important factor with a certain degree of accuracy in a way that saves time and reduces costs. In particular, the large capacity, high density, and complexity of the unit structure of flash memory have led to a significant increase in the uncertainty of screening. Coupled with the minimal volume of process technology, even in the individual cells on the same wafer, different electrical characteristics may occur at different locations. If it is handled in a non-discriminatory manner, it will inevitably lead to a sharp drop in yield.

Therefore, there is a need for a memory testing method that enables faster, more accurate, and more efficient screening tests of memory to meet the needs of memory testing.

The main object of the present invention is to provide a method for testing a memory, which is based on a test procedure of an automatic comparison method, and uses a computing power of a controller for a memory, such as a flash memory, to receive a test from a test computer. When the command is generated, the data of the random number or the specific format is generated, the data is written, read, and compared directly to the flash memory, and the test result is transmitted back to the test computer, thereby greatly reducing the test computer to the memory. The load of data input and output speeds up the testing of memory.

Another object of the present invention is to provide a method for testing a memory. The test computer is only responsible for transmitting a proprietary command (Proprietary Command) and a partially programmed low-order comparison function data to the controller, and then starting the test flow, and the controller Automatically erases all the blocks of the memory (Erase), then writes the data to all the pages of each block, and the written data is generated by the controller through the algorithm. come out. When reading the data of all the data pages of each block for comparison processing, the controller compares the read data with the previously written data through an algorithm to determine whether the memory block is normal. Therefore, the main test work is performed by the controller, which greatly reduces the data load of the transmission interface, reduces the computational load of the test computer, and improves the overall memory test efficiency.

It should be noted that in the process of low-order alignment, different algorithms are used to write, read, and compare the memory of different addresses through the algorithm, but the present invention does not use monotonous and fixed. The format data is used to filter the flash memory test, but the comparison method provided by the filter program in the test computer is used. Compared with the existing screening mode, the present invention has the same The mastery of low-order alignments, while using high-order comparisons to quickly understand the situation of comparison. The invention has the advantages of using the minimum load of the central processing unit of the test computer, the minimum data transmission and the short test time to complete the complicated test scanning work.

Therefore, all the disadvantages of the above-mentioned prior art can be solved by the test method of the memory provided by the present invention.

The embodiments of the present invention will be described in more detail below with reference to the drawings and the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

Referring to the third figure, a schematic diagram of a test method for the memory of the present invention. As shown in the third figure, the memory test system 2 includes a test computer 10 and a screening board 50, wherein the screening board 50 includes a controller 51 and a memory 60 to be tested. The controller 51 includes an interface circuit 52, a microprocessor (MCU) 54, a random access memory (RAM) 55, a read only memory (ROM) 56, and a logic circuit 58. The interface circuit 52 is responsible for receiving data of the test computer 10 or The data is transmitted to the test computer 10, the microprocessor 54 controls the processing program of the entire controller, the random access memory 55 provides access to the temporary data, and the logic circuit 58 mainly processes the data access to the memory 60, and only reads The memory 56 is used to store the code programmed by the test computer 10, including the algorithm for generating the test data, the comparison processing of the data, and the record test result.

Referring to the fourth figure, a flow chart of a test method for the memory of the present invention. As shown in the fourth figure, the test method of the present invention starts from step S100, and then proceeds to step S110. In step S110, the test computer preparation program The code proceeds to step S120. In step S120, the test computer transmits the program code and the setting data to the controller, and proceeds to step S130. In step S130, the controller erases the target block of the memory, and proceeds to step S140. In step S140, the controller writes the test data into the memory, and proceeds to step S150. In step S150, the controller reads the stored data stored in the memory, and proceeds to step S160. In step S160, the controller compares the test data with the received stored data, and proceeds to step S170. In step S170, the comparison result is recorded, and the flow proceeds to step S180. In step S180, if the test of all the blocks of the memory is not completed, the process returns to step S130, and if the test of all the blocks of the memory is completed, the process proceeds to step S190. In step S190, a memory test file is generated and transmitted to the test computer, and the process proceeds to step S200. In step S200, the operation is ended.

The code of step S110 may include an algorithm for generating test data, such as test data for low-order comparison mode, and the code may include comparison operation for low-order comparison mode, thereby accurately determining whether individual blocks are used. Normal, and because the operation is mainly performed by the logic circuit of the controller, it greatly saves the workload of the test computer, and speeds up the overall test speed and improves the test efficiency.

The code of step S110 may further include an algorithm for generating test data, such as a test file used in the high-order comparison mode, for dividing and mass writing the memory to greatly reduce the access frequency to the memory.

The memory test file of step S190 includes marking the block as a good block when the comparison is correct, and marking the block as a damaged block when the comparison is incorrect, thereby generating including displaying a good block and damage. The test table column for the block.

In summary, the method provided by the present invention can greatly reduce the frequency of access to the memory, save the workload of the test computer, and speed up the overall test speed and improve the test efficiency.

The above is only a preferred embodiment for explaining the present invention, and is not intended to limit the present invention in any way, and any modifications or alterations to the present invention made in the spirit of the same invention. All should still be included in the scope of the intention of the present invention.

1‧‧‧Memory Test System

2‧‧‧Memory Test System

10‧‧‧Test computer

20‧‧‧Screening board

30‧‧‧ Controller

40‧‧‧ memory

50‧‧‧ screening board

51‧‧‧ Controller

52‧‧‧Interface circuit

54‧‧‧Microprocessor (MCU)

55‧‧‧ Random Access Memory (RAM)

56‧‧‧Read-only memory (ROM)

58‧‧‧Logical Circuit

60‧‧‧ memory

S10~S30‧‧‧Steps

S110~S200‧‧‧Steps

The first figure is a schematic diagram showing a memory test system of a conventional technique.

The second figure is a flow chart showing the memory test of the conventional technique.

The third figure is a schematic diagram showing a test method of the memory of the present invention.

The fourth figure is a flow chart showing a test method of the memory of the present invention.

2‧‧‧Memory Test System

10‧‧‧Test computer

50‧‧‧ screening board

51‧‧‧ Controller

52‧‧‧Interface circuit

54‧‧‧Microprocessor (MCU)

55‧‧‧ Random Access Memory (RAM)

56‧‧‧Read-only memory (ROM)

58‧‧‧Logical Circuit

60‧‧‧ memory

Claims (7)

A method for testing a memory for testing a data writing and reading of a memory. The testing method of the memory includes the following steps: Step A: A test computer prepares a code, the code includes Generating an algorithm for testing data, a data comparison operation, and a recording operation of a test result, and then proceeding to step B; step B: the test computer transmits the code to a controller, the controller including an interface circuit, a microprocessor, a random access memory, a read-only memory, and a logic circuit, wherein the interface circuit receives the code and the set data and transmits the data to the read-only memory, the logic circuit processes the memory Data access, then proceeds to step C; step C: the logic circuit of the controller erases a target block of the memory, proceeds to step D; step D: the logic circuit of the controller writes the test data Going to the target block of the memory, proceeding to step E; step E: the logic circuit of the controller reads a stored data stored in the target block of the memory, In step F; step F: the logic circuit of the controller compares the test data with the stored data, and proceeds to step G; step G: the controller records a comparison result, and proceeds to step H; step H : If the test of all the blocks of the memory is not completed, return to step C. If the test of all the blocks of the memory is completed, proceed to step I; step I: generate a memory test file and transmit to the test computer In Go to step J; and step J: end the operation. The method for testing a memory according to claim 1, wherein the microprocessor captures the code in the read-only memory to control the logic circuit to execute the algorithm to generate the test data, The data access operation of the memory, the comparison operation of the data, and the recording operation of the test result. According to the test method of the memory of claim 1, wherein the comparison result of the step G records the target block as a good block when the test data is correctly aligned with the stored data, and The target block is recorded as a damaged block when the test data is incorrectly compared with the stored data. The method for testing a memory according to claim 1, wherein the random access memory provides a data temporary storage space to the controller. The method for testing a memory according to claim 1, wherein the memory test file of the step I includes the comparison result of the step G. The method of testing a memory according to claim 1, wherein the interface circuit comprises a USB interface circuit. The method of testing a memory according to claim 1, wherein the memory comprises a flash memory.