TWI390629B - Use of dry film photoresists in through-silicon via applications - Google Patents

Use of dry film photoresists in through-silicon via applications Download PDF

Info

Publication number
TWI390629B
TWI390629B TW97135816A TW97135816A TWI390629B TW I390629 B TWI390629 B TW I390629B TW 97135816 A TW97135816 A TW 97135816A TW 97135816 A TW97135816 A TW 97135816A TW I390629 B TWI390629 B TW I390629B
Authority
TW
Taiwan
Prior art keywords
wafer
photoresist
dry film
film photoresist
metal layer
Prior art date
Application number
TW97135816A
Other languages
Chinese (zh)
Other versions
TW201013774A (en
Inventor
Bin Hong Tsai
Pedro Jorge
Chester Balut
Original Assignee
Du Pont
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Du Pont filed Critical Du Pont
Priority to TW97135816A priority Critical patent/TWI390629B/en
Publication of TW201013774A publication Critical patent/TW201013774A/en
Application granted granted Critical
Publication of TWI390629B publication Critical patent/TWI390629B/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Description

乾膜光阻於矽穿孔應用中之用途Dry film photoresist for use in enamel perforation applications

本發明係關於乾膜光阻於矽穿孔(TSV)應用中之用途。This invention relates to the use of dry film photoresist in the application of sputum perforation (TSV).

乾膜光阻已經長期使用在製造印刷電路板(PCBs)中。例如,WO 2008/004784 A1揭示一種用於製造印刷電路板之方法及由此獲得之印刷電路板。該方法包含下列步驟:(a)將一包含光敏劑的乾膜粘合在該銅箔上,及接著曝光與顯影該乾膜,從而形成一用於形成點電路的乾膜開口;(b)藉由進行無電解或電解電鍍而形成一銅電鍍層,及隨後剝除該鍍銅層以外的乾膜,從而形成一點電路,其係第一金屬層;(c)進一步地將一包含光敏劑的乾膜粘合在該點電路上,及曝光與顯影該乾膜,從而形成一外部電路;及(d)藉由進行無電解或電解電鍍以形成一第二金屬層,其係用以改善該點電路與外部電路之傳導性。Dry film photoresists have long been used in the manufacture of printed circuit boards (PCBs). For example, WO 2008/004784 A1 discloses a method for manufacturing a printed circuit board and a printed circuit board obtained thereby. The method comprises the steps of: (a) bonding a dry film comprising a photosensitizer to the copper foil, and subsequently exposing and developing the dry film to form a dry film opening for forming a dot circuit; (b) Forming a copper plating layer by electroless or electrolytic plating, and subsequently stripping the dry film other than the copper plating layer, thereby forming a circuit which is a first metal layer; (c) further comprising a photosensitizer a dry film adhered to the dot circuit, and exposing and developing the dry film to form an external circuit; and (d) forming a second metal layer by performing electroless or electrolytic plating, which is used to improve The conductivity of the point circuit and the external circuit.

US 2007/0095466 A1揭示一種製造多層印刷線路板的方法,係將一感光性乾膜附著在一具有一薄膜導電層的層間樹脂絕緣層上,進行光曝光與顯影以形成一電鍍阻層及其後在不具有該電鍍阻層的部分上形成導電電路,其特徵在於該感光性乾膜在其任一表面上具有含氮雜環化合物層。US 2007/0095466 A1 discloses a method for manufacturing a multilayer printed wiring board by attaching a photosensitive dry film to an interlayer resin insulating layer having a thin film conductive layer, performing light exposure and development to form a plating resist layer and Then, a conductive circuit is formed on the portion not having the plating resist layer, characterized in that the photosensitive dry film has a nitrogen-containing heterocyclic compound layer on any surface thereof.

迄今為止,先前技術尚未提議將乾膜光阻應用於封裝積體電路。To date, prior art has not proposed the application of dry film photoresist to packaged integrated circuits.

由於電氣/電子產品的傾向小型化、高功能性與安裝可靠性,三維(3D)堆疊封裝已經成為關注的焦點,因為其不只提供增加的記憶體容量也提供提高安裝密度與安裝區域的利用效率之優點。3D堆疊封裝係下一代封裝技術之潛力性方案且已持續發展中。3D堆疊封裝可縮短連接線的平均長度,因而戲劇性地減少電晶體封裝密度、晶片尺寸及功率消耗,並且導致低的生產成本。此外,3D堆疊封裝使得不同系統可整合於一多相基板中。Due to the trend toward miniaturization, high functionality and installation reliability of electrical/electronic products, three-dimensional (3D) stacked packages have become the focus of attention because they not only provide increased memory capacity but also increase mounting density and utilization efficiency of the mounting area. The advantages. 3D stacked packages are potential solutions for next-generation packaging technologies and are continuing to evolve. The 3D stacked package can shorten the average length of the connection lines, thus dramatically reducing the transistor package density, wafer size and power consumption, and resulting in low production costs. In addition, the 3D stacked package allows different systems to be integrated into a multi-phase substrate.

矽穿孔(TSV)技術係一種最受熟悉本技藝者注意之3D堆疊封裝。TSV技術形成一其內形成有矽穿孔之晶片。因此,此類型的多種晶片係經由該等矽穿孔而彼此物理性及電性連接。傳統上,TSV技術涉及一種「濕式」方法,其中使用液體光阻組合物。US 2008/0079121 A1揭示一種用於在半導體晶圓中形成矽穿孔的方法,其包括下列步驟:在一晶圓中界定一凹槽,該晶圓可形成複數個半導體晶片;將液體聚合物施加在該晶圓上以填充該凹槽;經由使該聚合物圖案化而在該凹槽的側壁上形成一絕緣層;在其側壁上形成一金屬層;及背面研磨該晶圓之背面而露出填充在該凹槽中的金屬層。The Twisted Hole (TSV) technology is a 3D stacked package that is most noticed by those skilled in the art. The TSV technology forms a wafer in which a perforated hole is formed. Therefore, a plurality of types of wafers of this type are physically and electrically connected to each other via the turns of the crucibles. Traditionally, TSV technology has involved a "wet" process in which a liquid photoresist composition is used. US 2008/0079121 A1 discloses a method for forming germanium vias in a semiconductor wafer, comprising the steps of: defining a recess in a wafer, the wafer can form a plurality of semiconductor wafers; applying a liquid polymer Filling the groove on the wafer; forming an insulating layer on the sidewall of the groove by patterning the polymer; forming a metal layer on the sidewall thereof; and polishing the back surface of the wafer to expose A metal layer filled in the recess.

涉及「濕式」方法之TSV技術存在若干問題。例如,當蝕刻期間形成互連之通道或溝槽時,蝕刻期間難以控制該通道或該溝槽之深度。當蝕刻進行後暫時被中止,蝕刻對用於互連之通道或溝槽底部之多孔氧化矽造成毀壞,其導致通道底部之泄漏電流及較高介電常數。雖然涉及「濕式」方法之TSV技術可形成一通道或一溝槽,但該技術無法提供用於該通道或該溝槽的保護。此外,「超載」情況經常發生。There are several problems with the TSV technology involving the "wet" approach. For example, when a channel or trench of an interconnect is formed during etching, it is difficult to control the depth of the channel or the trench during etching. When the etching is temporarily aborted, the etching destroys the porous yttrium oxide at the bottom of the channel or trench for interconnection, which results in leakage current at the bottom of the channel and a higher dielectric constant. Although the TSV technology involving the "wet" method can form a channel or a trench, this technique does not provide protection for the channel or the trench. In addition, "overloading" often occurs.

深RIE方法(以下簡稱「DRIE方法」)係一種通常在晶圓上提供用於通道形成之路徑之方法。一種經常使用的DRIE方法係Bosch方法。藉由小心地控制蝕刻與鈍化條件,可在溫和條件下進行以蝕刻由光阻微影蝕刻所產生之遮罩。然而,有些光阻,由於彼等在Bosch方法期間不足的選擇性,顯示不欲之結果及產生不良品質的通道。The deep RIE method (hereinafter referred to as "DRIE method") is a method of providing a path for channel formation on a wafer. One commonly used DRIE method is the Bosch method. By carefully controlling the etching and passivation conditions, the mask produced by photoresist photolithography etching can be performed under mild conditions. However, some of the photoresists, due to their lack of selectivity during the Bosch process, show undesirable results and channels of poor quality.

仍然需要發展一種不具有該等上述問題的用於3D堆疊封裝之TSV方法。There is still a need to develop a TSV method for 3D stacked packages that does not have such problems as described above.

本發明提供一種用於在一晶圓中形成矽穿孔的方法,其包括下列步驟:提供一晶圓,在該晶圓上層壓一乾膜光阻,通過一遮罩使該乾膜光阻曝光至一光源以形成未曝光的光阻區域與曝光的光阻區域,使該乾膜光阻顯影以露出該等未曝光光阻區域底下部分,使用一DRIE方法蝕刻該等露出之晶圓底下部分以在該晶圓中形成矽穿孔,及以一光阻移除劑從該晶圓移除該等曝光的光阻區域。本發明亦提供一種用於在一晶圓中保護矽穿孔之方法,及一種用於在一晶圓中電鍍矽穿孔的方法,該等之特徵亦係使用乾膜光阻。The present invention provides a method for forming germanium vias in a wafer, comprising the steps of: providing a wafer on which a dry film photoresist is laminated, and exposing the dry film photoresist to a mask through a mask a light source to form an unexposed photoresist region and an exposed photoresist region, to develop the dry film photoresist to expose portions of the underlying portions of the unexposed photoresist regions, and to etch the exposed portions of the underlying portions of the wafer using a DRIE method A germanium via is formed in the wafer, and the exposed photoresist regions are removed from the wafer with a photoresist remover. The present invention also provides a method for protecting ruthenium perforations in a wafer, and a method for electroplating ruthenium perforations in a wafer, the features of which are also the use of dry film photoresist.

在一態樣中,本發明提供一種用於在一晶圓中形成矽穿孔之方法,其包括下列步驟:In one aspect, the present invention provides a method for forming a ruthenium perforation in a wafer, comprising the steps of:

(a1)提供一晶圓,(a1) providing a wafer,

(b1)在該晶圓上層壓一乾膜光阻,(b1) laminating a dry film photoresist on the wafer,

(c1)通過一遮罩使該乾膜光阻曝光至一光源以形成未曝光的光阻區域與曝光的光阻區域,(c1) exposing the dry film photoresist to a light source through a mask to form an unexposed photoresist region and an exposed photoresist region,

(d1)使該乾膜光阻顯影以露出該等未曝光光阻區域底下部分,(d1) developing the dry film photoresist to expose portions of the underlying portions of the unexposed photoresist regions,

(e1)使用一DRIE方法乾蝕刻該等露出的該晶圓底下部分以在該晶圓中形成矽穿孔,及(e1) dry etching the exposed under portions of the wafer using a DRIE method to form germanium vias in the wafer, and

(f1)以一光阻移除劑從該晶圓移除該等曝光的光阻區域。(f1) removing the exposed photoresist regions from the wafer with a photoresist remover.

在本發明之一較佳實施例中,在步驟(e1)之前,該晶圓上之乾膜光阻進行顯影後烘烤。較佳地,該顯影後烘烤係於一溫度為約60℃至約130℃之烘箱中使該晶圓上之乾膜光阻烘烤約5分鐘至約30分鐘。較佳地,步驟(e1)係使用氣體例如SF6 及C4 F8 進行。In a preferred embodiment of the invention, the dry film photoresist on the wafer is post-developed and baked prior to step (e1). Preferably, the post-development bake is performed by baking the dry film photoresist on the wafer in an oven at a temperature of from about 60 ° C to about 130 ° C for from about 5 minutes to about 30 minutes. Preferably, step (e1) is carried out using a gas such as SF 6 and C 4 F 8 .

在進一步態樣中,本發明提供一種保護晶圓中之矽穿孔之方法,其包括下列步驟:In a further aspect, the present invention provides a method of protecting a helium perforation in a wafer, comprising the steps of:

(a2)提供一具有矽穿孔的晶圓,(a2) providing a wafer having a perforated hole,

(b2)在該晶圓上電鍍一金屬層,(b2) plating a metal layer on the wafer,

(c2)在該晶圓上層壓一乾膜光阻,(c2) laminating a dry film photoresist on the wafer,

(d2)通過一遮罩使該乾膜光阻曝光至光源以在該晶圓的該等通道上形成曝光的光阻區域,及在該晶圓的其他區域上形成未曝光的光阻區域,(d2) exposing the dry film photoresist to a light source through a mask to form an exposed photoresist region on the channels of the wafer, and forming an unexposed photoresist region on other regions of the wafer,

(e2)使該乾膜光阻顯影以露出該等未曝光光阻區域底下部分,(e2) developing the dry film photoresist to expose portions of the underlying portions of the unexposed photoresist regions,

(f2)以一蝕刻溶液蝕刻該晶圓之該等露出的底下部分以保護該等矽穿孔及在該晶圓上形成所需圖案,及(f2) etching the exposed underlying portions of the wafer with an etching solution to protect the germanium vias and form a desired pattern on the wafer, and

(g2)以一光阻移除劑從該晶圓移除該等曝光的光阻區域。(g2) removing the exposed photoresist regions from the wafer with a photoresist remover.

較佳地,步驟(b2)係藉由在該晶圓上沉澱一薄金屬層,及隨後在該晶圓之該薄金屬層上電鍍一金屬層而進行。Preferably, step (b2) is performed by depositing a thin metal layer on the wafer and subsequently plating a metal layer on the thin metal layer of the wafer.

較佳地,該晶圓之背面亦藉由在該晶圓之背面上層壓一乾膜光阻及將該乾膜光阻曝光至一光源以在該晶圓之該背面上形成曝光的光阻區域而予以保護。Preferably, the back side of the wafer is also formed by laminating a dry film photoresist on the back surface of the wafer and exposing the dry film photoresist to a light source to form an exposed photoresist region on the back surface of the wafer. And protect it.

在更進一步態樣中,本發明提供一種電鍍晶圓中矽穿孔之方法,其包括下列步驟:In still further aspects, the present invention provides a method of ruthenium perforation in an electroplated wafer, comprising the steps of:

(a3)提供一具有矽穿孔的晶圓,(a3) providing a wafer having a perforated hole,

(b3)在該晶圓上沉澱一薄金屬層,(b3) depositing a thin metal layer on the wafer,

(c3)在該晶圓之薄金屬層上層壓一乾膜光阻,(c3) laminating a dry film photoresist on the thin metal layer of the wafer,

(d3)通過一遮罩使該乾膜光阻曝光至光源以在該晶圓的該等通道上形成未曝光的光阻區域,及在該晶圓的其他區域上形成曝光的光阻區域,(d3) exposing the dry film photoresist to a light source through a mask to form an unexposed photoresist region on the channels of the wafer, and forming an exposed photoresist region on other regions of the wafer,

(e3)使該乾膜光阻顯影以露出底下部分之該晶圓之該等通道,(e3) developing the dry film photoresist to expose the channels of the underlying portion of the wafer,

(f3)以一金屬電鍍該晶圓之通道直到其被填滿,及(f3) plating the channel of the wafer with a metal until it is filled, and

(g3)以一光阻移除劑從該晶圓移除該等曝光的光阻區域。(g3) removing the exposed photoresist regions from the wafer with a photoresist remover.

任何可用於製造電子元件之晶圓均可應用於本發明。例如,該晶圓可由銦氧化錫(ITO)玻璃、矽、二氧化矽、氮化矽、GaN、藍寶石、InGaN、AlInGaP、或陶器構成。Any wafer that can be used to fabricate electronic components can be used in the present invention. For example, the wafer may be composed of indium tin oxide (ITO) glass, germanium, germanium dioxide, tantalum nitride, GaN, sapphire, InGaN, AlInGaP, or ceramics.

任何已知的負型乾膜光阻皆可用於本發明之方法中。本發明中可使用包括感光性丙烯酸酯之負型乾膜光阻;例如,由E.I. Du Pont De Nemours and Company所製造及銷售的MPFTM 系列。由E.I.Du Pont De Nemours and Company製造與銷售的該等乾膜光阻,MPFTM MX5000系列(15、20、30、40、50微米厚)、MPFTM MXA 100(10、15、25微米厚)及MPFTM WBR2000係較佳的。Any known negative dry film photoresist can be used in the method of the present invention. May be used in the present invention include a negative type photosensitive dry film resist of an acrylate; e.g. by EI Du Pont De Nemours and Company manufactured and sold by MPF TM series. A EIDu Pont De Nemours and Company of manufacture and sale of such a dry film photoresist, MPF TM MX5000 series (15,20,30,40,50 microns thick), MPF TM MXA 100 (10,15,25 microns thick) and MPF TM WBR2000 preferred system.

步驟(b2)、(b3)與(f3)中可使用任何所需金屬。較佳地,該金屬係銅。Any desired metal can be used in steps (b2), (b3) and (f3). Preferably, the metal is copper.

在步驟(c1)、(d2)與(d3)中,該遮罩可帶有任何所需圖案。該等圖案界定出欲曝光至光源之該乾膜光阻之區域。該光源可為例如紅外線、寬帶紫外線、深紫外線、超紫外線、e-光束及x射線。In steps (c1), (d2) and (d3), the mask may carry any desired pattern. The patterns define areas of the dry film photoresist to be exposed to the light source. The light source may be, for example, infrared light, broadband ultraviolet light, deep ultraviolet light, ultra ultraviolet light, e-light beam, and x-ray.

步驟(d1)、(e2)與(e3)係藉由使用鹼性或中性顯影液而進行。任何已知的鹼性或中性顯影液均可應用於本發明步驟(d1)、(e2)與(e3)中。較佳地,於步驟(d1)、(e2)、(e3)係使用具有0.1至1.5v/v%濃度的鹼性碳酸鈉水溶液進行。The steps (d1), (e2) and (e3) are carried out by using an alkaline or neutral developing solution. Any known alkaline or neutral developing solution can be applied to the steps (d1), (e2) and (e3) of the present invention. Preferably, the steps (d1), (e2), and (e3) are carried out using an aqueous alkaline sodium carbonate solution having a concentration of 0.1 to 1.5 v/v%.

在步驟(e1)中,該DRIE方法較佳地係Bosch方法。較佳地,步驟(e1)係在下列條件下使用一STS多功ASE DRIE蝕刻系統進行(感應耦合電漿(ICP)源功率與偏功率分別設定為900W與15W。用於鈍化步驟的ICP源功率與偏功率分別固定為800W與0W)。步驟(f2)使用一蝕刻溶液進行,例如,H3 PO4 、H2 SO4 、及CuCl2 溶液。In step (e1), the DRIE method is preferably a Bosch method. Preferably, step (e1) is performed using an STS multi-function ASE DRIE etching system under the following conditions (inductively coupled plasma (ICP) source power and bias power are set to 900 W and 15 W, respectively. ICP source for passivation step) The power and partial power are fixed at 800W and 0W, respectively. Step (f2) is carried out using an etching solution, for example, a H 3 PO 4 , H 2 SO 4 , and CuCl 2 solution.

任何已知電鍍技術均可用以進行步驟(b2)與(f3)。例如,步驟(b2)與(f3)可藉由電解電鍍、無電解電鍍、濺射,或蒸發而進行。Any known plating technique can be used to perform steps (b2) and (f3). For example, steps (b2) and (f3) can be carried out by electrolytic plating, electroless plating, sputtering, or evaporation.

在步驟(f1)、(g2)與(g3)中,該光阻移除劑係例如由E.I.Du Pont De Nemours and Company所製造與銷售的EKC162TM 與EKC265TMIn the step (f1), (g2) and (g3), the photoresist remover based for example EIDu Pont De Nemours and Company and manufactured and sold by EKC162 TM EKC265 TM.

本發明之方法使其的可更容易地控制在TSV技術之蝕刻步驟期間之通道深度,及排除總是發生於涉及「濕式」方法之TSV技術之「超載」情况。本發明之乾膜光阻方法可應用於通道形成、通道保護與通道電鍍。與其中使用液態光阻(正型或負型)之先前技術方法相反,本發明之乾膜光阻方法需要相當短的全加工時間。The method of the present invention makes it easier to control the depth of the channel during the etching step of the TSV technology and to eliminate the "overload" condition that always occurs with the TSV technology involving the "wet" method. The dry film photoresist method of the present invention can be applied to channel formation, channel protection, and channel plating. In contrast to prior art methods in which a liquid photoresist (positive or negative) is used, the dry film photoresist method of the present invention requires a relatively short total processing time.

本發明將因參考下列實例而變得顯而易見,其僅用以說明且應不用以限制申請專利範圍中所述之本發明範圍。The invention will be apparent from the following examples, which are intended to be illustrative only and not to limit the scope of the invention described in the claims.

實例Instance 實例1-通道形成Example 1 - Channel Formation

材料與程序:Materials and procedures:

製備6個具有100×100mm2 面積的晶圓供隨後使用。使用層合機作為層合工具,於下列條件下將由E.I.Du Pont De Nemours and Company所製造與銷售的MPFTM MX5000系列(15微米厚)之乾膜光阻層壓於各晶圓上:Six wafers having an area of 100 x 100 mm 2 were prepared for subsequent use. use Laminator as lamination instrument, under the following conditions will be manufactured and sold EIDu Pont De Nemours and Company MPF TM MX5000 series (15 microns thick) of a dry film resist is laminated on each wafer:

速度:1m/minSpeed: 1m/min

壓力:3kg/cm2 Pressure: 3kg/cm 2

溫度:110℃Temperature: 110 ° C

在該等晶圓上之乾膜光阻依據該等下列程序圖案化:The dry film photoresist on the wafers is patterned according to the following procedures:

在該晶圓上之該等乾膜光阻藉由通過微影蝕刻遮罩使用一帶有25.44mJ/cm2 i-線的MA8 Suss定位器而進行曝光,以形成未曝光的光阻區域與曝光的光阻區域。該晶圓在26℃下使用0.65%的碳酸鈉溶液進行顯影60秒。所有六個晶圓移至使用一STS多功ASE DRIE蝕刻系統的蝕刻室中。就該蝕刻步驟而言,感應耦合電漿(ICP)源功率及偏功率分別設定為900W與15W。對鈍化步驟而言,ICP源功率及偏功率分別設定為800W與0W。使用Zygo干涉儀作為20微米通道深度的測量工具。於6個晶圓中各形成具有10、20、30、40、50微米直徑的通道。晶圓中之3個移至烘箱中在85℃下進行顯影後烘乾20分鐘。所有6個晶圓以O2 去鑽污歷時3分鐘以移除潛在顯影殘渣。The dry film photoresist on the wafer is exposed by a lithography etch mask using a MA8 Suss locator with a 25.44 mJ/cm 2 i-line to form an unexposed photoresist area and exposure. The photoresist area. The wafer was developed using a 0.65% sodium carbonate solution at 26 ° C for 60 seconds. All six wafers were moved into an etch chamber using an STS multi-function ASE DRIE etch system. For this etching step, the inductively coupled plasma (ICP) source power and the bias power were set to 900 W and 15 W, respectively. For the passivation step, the ICP source power and the bias power are set to 800 W and 0 W, respectively. A Zygo interferometer was used as a measurement tool for 20 micron channel depth. Channels having diameters of 10, 20, 30, 40, and 50 microns are formed in each of the six wafers. Three of the wafers were transferred to an oven and developed at 85 ° C for 20 minutes. All 6 wafers were etched with O 2 for 3 minutes to remove potential development debris.

結果:result:

未進行顯影後烘烤之該等晶圓的橫截面SEM圖顯示不同的通道浸蝕深度。就16、33及58分鐘的蝕刻時間而言,具有20微米直徑的等通道之蝕刻深度分別為52、92與150微米。該結果亦顯示乾膜厚度未明顯流失,其揭露該乾膜光阻MPFTM MX5000系列(15微米厚),在Bosch方法中具有高的蝕刻選擇性(即,100:1)。高倍放大的SEM圖顯示在該晶圓與該光阻之間不存在「底部蝕刻(under etching)」效應。Cross-sectional SEM images of the wafers that were not post-development baked showed different channel etch depths. For etch times of 16, 33 and 58 minutes, the etch depths of the equal channels having a diameter of 20 microns were 52, 92 and 150 microns, respectively. The results also showed that the dry film thickness loss is not significant, which disclose that MPF TM MX5000 series of dry film photoresist (15 microns thick), having a high etch selectivity (i.e., 100: 1) In the Bosch process. The high magnification SEM image shows no "under etching" effect between the wafer and the photoresist.

在進行顯影後烘乾之晶圓中,甚至發現蝕刻選擇性(見圖1)。進行顯影後烘乾的該等晶圓與未進行顯影後烘乾的晶圓兩者之抗蝕劑在DRIE方法中均良好地存在。In the wafer which was dried after development, even etching selectivity was found (see Fig. 1). The resists of both the wafers subjected to development and drying and the wafers which were not subjected to development and drying were well present in the DRIE method.

圖1中所示的SEM圖片證明在該乾膜光阻MPFTM MX5000系列(15微米厚)之微影蝕刻後所得結果,該乾膜光阻係在其上具有50微米直徑之通道之未塗敷之矽晶圓。SEM image shown in FIG. 1 demonstrates that the dry film photoresist MPF TM MX5000 series (15 m thick) The results obtained after the lithography, the photoresist dry film system having an uncoated 50 micron diameter of the passage in which Apply the wafer.

圖2中所示的SEM圖片證明在58分鐘蝕循環後獲得的結果,其導致一高的垂直側壁。The SEM image shown in Figure 2 demonstrates the results obtained after the 58 minute eclipse cycle, which results in a high vertical sidewall.

圖3、4及5中所示的SEM圖片證明在3個蝕刻循環即,分別蝕刻16、33及58分鐘後各獲得的結果。The SEM images shown in Figures 3, 4 and 5 demonstrate the results obtained after three, etch cycles, i.e., 16 , 33 and 58 minutes, respectively.

實例2-填充與未填充通道的通道保護Example 2 - Channel Protection for Filled and Unfilled Channels

製備具有直徑範圍從10微米至250微米的通道之晶圓。在各晶圓上沉積2μm的薄金屬層,及接著在晶圓上側之整個表面上電鍍一10微米的金屬層。依下列方式進行乾膜光阻對晶圓上的未填充金屬化通道與金屬填充之通道之通道保護的評估。Wafers having channels having diameters ranging from 10 microns to 250 microns are prepared. A 2 μm thin metal layer was deposited on each wafer, and then a 10 μm metal layer was plated on the entire surface of the upper side of the wafer. The dry film photoresist is evaluated for channel protection of unfilled metallization channels and metal filled channels on the wafer in the following manner.

1.未填充通道的保護1. Protection of unfilled channels

依據實例1之程序,將E.I.Du Pont De Nemours and Company所製造與銷售的MPFTM MX5000系列(15微米厚)乾膜光阻層壓在晶圓上,但使用下表1所示的條件:The procedure according to Example 1, the EIDu Pont De Nemours and Company manufactured and sold by MPF TM MX5000 series (15 m thick) laminated dry film photoresist on the wafer, but using the conditions shown in Table 1 below:

在層壓後,該等在通道上具有乾膜光阻的晶圓使用具有狗骨構造之遮罩進行微影蝕刻製程。該等晶圓通過該遮罩使用帶有25.44mJ/cm2 i-線的MA8 Suss定位器進行曝光,以在該等晶圓的該等通道上形成曝光的光阻區域及在該晶圓的其他區域上形成未曝光的光阻區域。使該等晶圓在26°C下使用0.65%的碳酸鈉溶液進行顯影60秒。隨後,該等晶圓移至在80℃之烘箱中供顯影後烘10分鐘。After lamination, the wafers having dry film photoresist on the vias are subjected to a photolithographic etching process using a mask having a dog bone structure. The wafers are exposed through the mask using a MA8 Suss positioner with a 25.44 mJ/cm 2 i-line to form an exposed photoresist region on the channels of the wafers and on the wafer. Unexposed photoresist regions are formed on other regions. The wafers were developed using a 0.65% sodium carbonate solution at 26 ° C for 60 seconds. Subsequently, the wafers were transferred to an oven at 80 ° C for development and baked for 10 minutes.

該測試係藉由使用具有狗骨構造之遮罩進行,使用實例1的曝光、顯影及蝕刻步驟。獲得具有通道的晶圓之橫截面SEM圖片。在TSV應用中使用乾膜光阻證明層壓期間在晶圓上之預先退出之通道上的獨特「遮蓋」能力而無失敗。此外,即使在該等通道具有大如200微米直徑的情況下,在該等晶圓之該等未填充通道上的乾膜光阻保護該等通道在隨後的蝕刻步驟中不被蝕刻。The test was performed using a mask having a dog bone configuration using the exposure, development and etching steps of Example 1. Obtain a cross-sectional SEM picture of the wafer with the channel. The use of dry film photoresist in TSV applications demonstrates the unique "masking" capability on the pre-exit channel on the wafer during lamination without failure. Moreover, even if the channels have a diameter as large as 200 microns, the dry film photoresist on the unfilled channels of the wafers protects the channels from being etched during subsequent etching steps.

結果:result:

圖6與7中所示之SEM圖片,顯示藉由使用熱輥層壓而獲得之該乾膜光阻MPFTM MX5000系列(15微米厚)之「遮蓋」能力。未觀察到遮蓋失敗。6 and FIG. 7 of the SEM photograph shown in the display by using a hot roll lamination of the dry film resist obtained MPF TM MX5000 series (15 microns thick) of the "cover" capability. No cover failure was observed.

圖8中所示之SEM圖片,顯示使用具有狗骨構造之遮罩在微影蝕刻製程後的晶圓。The SEM image shown in Figure 8 shows the wafer after the lithography process using a mask having a dog bone structure.

圖9與10中所示之SEM圖片,顯示源自「遮蓋」殘存實驗之晶圓。該乾膜光阻MPFTM MX5000系列(15微米厚)不僅與金屬蝕刻化學品完全相容,且具有較强的「遮蓋」抗性,即使當使用高於正常的側蝕時亦然。此外,在該乾膜光阻移除後,該等通道內或該等晶圓表面上未觀察到殘渣。The SEM images shown in Figures 9 and 10 show wafers derived from the "covering" residual experiment. The dry film photoresist EVEN MPF TM MX5000 series (15 microns thick) not fully compatible with the metal etch chemistry, and has a strong "cover" resistance, even when a higher than normal undercut. In addition, no residue was observed in the channels or on the surface of the wafers after the dry film photoresist was removed.

2.填充通道的保護2. Fill channel protection

使用如用於未填充通道的保護中之相同程序,以乾膜光阻MPFTM MX5000系列(15微米厚)保護此測試中之該等晶圓的完全填充通道。在此測試中,乾膜光阻MPFTM MX5000系列(15微米厚)亦對該等晶圓之完全填充通道提供良好保護,且在該蝕刻與乾膜光阻移除步驟期間未觀察到失敗。Using the same procedure as for the protection of the unfilled channel, to a dry film photoresist MPF TM MX5000 series (15 microns thick) is protected completely fill the channel in this test of the wafers. In this test, a dry film photoresist MPF TM MX5000 series (15 microns thick) also provide a good protection for the other channel is completely filled wafer, and the failure was not observed during the etch dry film photoresist removal step.

結論:in conclusion:

乾膜光阻MPFTM MX5000系列(15微米厚),由於其在該Bosch過程中獨特的乾膜性能,包含加工容易、厚度均勻、高產量及優異的選擇性,故在3D TSV應用中係一優異的光阻替代品。使用乾膜光阻MPFTM MX5000系列(15微米厚)形成通道之結果,顯示高的選擇性(即,100:1),尚且,在該Bosch方法之後無明顯厚度損失。此外,該乾膜光阻MPFTM MX5000系列(15微米厚)可容易於移除而在該等通道內或晶圓表面上無任何殘渣。在該通道保護測試中,其結果顯示使用乾膜光阻MPFTM MX5000系列(15微米厚)可獲得清潔的顯影特徵與强的遮蓋能力。該製程後未發現顯影殘渣與破裂遮蓋通道。The dry film photoresist MPF TM MX5000 series (15 micron thick) is one of the 3D TSV applications due to its unique dry film properties during the Bosch process, including easy processing, uniform thickness, high throughput and excellent selectivity. Excellent photoresist replacement. Using a dry film photoresist MPF TM MX5000 series (15 microns thick) formed of the result of channel, display high selectivity (i.e., 100: 1), yet, no significant thickness loss after the Bosch process. In addition, the dry film photoresist MPF TM MX5000 series (15 microns thick) to be readily removed without any residue on the wafer surface, or such passage. In this channel protection test results are shown using a dry film photoresist MPF TM MX5000 series (15 microns thick) obtained cleaning the developing characteristics and strong hiding power. No development residue and cracked cover channels were found after the process.

實例3-通道電鍍Example 3 - Channel Plating

製備具有50微米直徑之通道的矽晶圓。該晶圓進行通道絕緣因而在晶圓上沉積具有600nm厚度的氧化層(經由CVD),及隨後於該氧化層上形成200nm氮化層(LPCVD)。該晶圓接著進行晶種沉澱因而在晶圓上形成具有0.1μm厚度的Ti層後接著沉積3pm厚之Cu層。此後,依據實例1之程序,將該由E.I.Du Pont De Nemours and Company所製造與銷售的MPFTM MX5000系列(15微米厚)乾膜光阻層壓在該等晶圓上,但使用下列條件:A tantalum wafer having a 50 micron diameter channel was prepared. The wafer is channel insulated to deposit an oxide layer (via CVD) having a thickness of 600 nm on the wafer, and then a 200 nm nitride layer (LPCVD) is formed on the oxide layer. The wafer was then subjected to seed precipitation to form a Ti layer having a thickness of 0.1 μm on the wafer followed by deposition of a 3 pm thick Cu layer. Thereafter, the procedure according to Example 1, the fabricated from EIDu Pont De Nemours and Company and marketed MPF TM MX5000 series (15 m thick) laminated on the dry film resist the wafers, but using the following conditions:

機器:Leonardo-層壓工具,Machine: Leonardo-Laminating Tools,

卡盤溫度:80℃,Chuck temperature: 80 ° C,

輥溫度:20℃,及Roller temperature: 20 ° C, and

刀溫度:120℃。Knife temperature: 120 ° C.

在層壓後,MA6手動工具在36mJ/cm2 的曝光能下使晶圓進行曝光。該晶圓接著在下列條件下進行顯影:After lamination, the MA6 hand tool exposed the wafer at an exposure level of 36 mJ/cm 2 . The wafer is then developed under the following conditions:

機器:SssACS200TMMachine: S ssACS200 TM ,

試劑:緩衝的0.65%K2 CO3 (商品名:D4000),Reagent: buffered 0.65% K 2 CO 3 (trade name: D4000),

溫度:對圖案電鍍應用為28℃Temperature: 28°C for pattern plating applications

顯影時間:50秒,及Development time: 50 seconds, and

清洗時間:10秒(以MgSO4 人工硬化之水)。Washing time: 10 seconds (water artificially hardened with MgSO 4 ).

顯影後,使用400W/O2 閃光電漿使晶圓進行電鍍2分鐘,接著酸洗1分鐘。該電鍍速度係2μm/min。After development, the wafer was plated for 2 minutes using 400 W/O 2 flash plasma, followed by pickling for 1 minute. The plating speed was 2 μm/min.

實例4-產量比較Example 4 - Yield Comparison

產量係比較本發明之方法與兩種先前技術的方法,本發明方法使用乾膜光阻MPFTM MX5000系列(15微米厚),先前技術使用液態正型光阻(由AZ化學公司製造與銷售的AZ4620TM )及液態負型光阻(由JSR公司製造與銷售的THB系列TM )。該比較結果示於下表2:Comparison of Yield based method of the present invention to two prior art methods, the present invention is a method using a dry film photoresist MPF TM MX5000 series (15 microns thick), the prior art using a liquid positive photoresist (manufactured by AZ Chemical Company and marketed AZ4620 TM ) and liquid negative photoresist (THB series TM manufactured and sold by JSR). The results of this comparison are shown in Table 2 below:

如上表所示,相較於使用液態正型光阻(由AZ化學公司製造與銷售的AZ4620TM )及液態負型光阻(由JSR公司製造與銷售的THB系列TM )之兩種先前技術方法,使用MPFTM MX5000系列(15微米厚)乾膜光阻之本發明方法需要相當短的總處理時間。As shown in the above table, there are two prior art methods compared to the use of liquid positive photoresist (AZ4620 TM manufactured and sold by AZ Chemical Co., Ltd.) and liquid negative photoresist (THB series TM manufactured and sold by JSR Corporation). using the MPF TM MX5000 series (15 microns thick) of a dry film resist method of the present invention requires a relatively short total treatment time.

圖1所示之SEM圖片,顯示在乾膜光阻MPFTM MX5000系列(15微米厚)之微影蝕刻製程後獲得之結果,該乾膜光阻係加在具有50微米直徑的通道之未裝填的矽晶圓上。The SEM image shown in FIG. 1, shows the results obtained after the dry film photoresist MPF TM MX5000 series (15 microns thick) of the lithography process, the dry film photoresist-based channel added unloaded having a diameter of 50 microns On the wafer.

圖2所示之SEM圖片,顯示在58分鐘蝕刻循環後獲得的結果。The SEM image shown in Figure 2 shows the results obtained after a 58 minute etch cycle.

圖3、4與5所示之SEM圖片,顯示分別在16分鐘、33分鐘、及58分鐘的蝕刻循環後獲得的結果。The SEM images shown in Figures 3, 4 and 5 show the results obtained after an etch cycle of 16 minutes, 33 minutes, and 58 minutes, respectively.

圖6與7所示之SEM圖片,顯示該乾膜光阻MPFTM MX5000系列(15微米厚)之「遮蓋(tenting)」能力,其係藉由使用熱輥層壓而獲得。SEM images shown in FIG. 6 of 7, the dry film photoresist MPF TM MX5000 series (15 microns thick) of "covering (tenting)" capability, which system is obtained by using a hot roll laminator.

圖8所示之SEM圖片,顯示在使用具有一狗骨構造的遮罩進行微影蝕刻製程後之晶圓。The SEM image shown in Fig. 8 shows the wafer after the lithography process using a mask having a dog bone structure.

圖9與10所示之SEM圖片,顯示從一「遮蓋」殘存實驗中獲得的晶圓。The SEM images shown in Figures 9 and 10 show wafers obtained from a "cover" residual experiment.

(無元件符號說明)(no component symbol description)

Claims (16)

一種用於在晶圓中保護矽穿孔的方法,其包括下列步驟:(a2)提供一具有矽穿孔的晶圓,(b2)在該晶圓上電鍍一金屬層,(c2)在該晶圓上層壓一乾膜光阻,(d2)通過一遮罩使該乾膜光阻曝光至光源以在該晶圓的複數通道上形成曝光的光阻區域,及在該晶圓的其他區域上形成未曝光的光阻區域,(e2)使該乾膜光阻顯影以露出該等未曝光光阻區域底下部分,(f2)以一蝕刻溶液蝕刻該晶圓之該等露出之底下部分以保護該等矽穿孔,及在該晶圓上形成所需圖案,及(g2)以一光阻移除劑從該晶圓處移除該等曝光的光阻區域。 A method for protecting a ruthenium perforation in a wafer, comprising the steps of: (a2) providing a wafer having a ruthenium perforation, (b2) plating a metal layer on the wafer, and (c2) plating the wafer Laminating a dry film photoresist, (d2) exposing the dry film photoresist to a light source through a mask to form an exposed photoresist region on the plurality of channels of the wafer, and forming an unmasked region on other regions of the wafer Exposing the photoresist region, (e2) developing the dry film photoresist to expose the underlying portions of the unexposed photoresist regions, and (f2) etching the exposed bottom portions of the wafer with an etching solution to protect the portions矽perforating, and forming a desired pattern on the wafer, and (g2) removing the exposed photoresist regions from the wafer with a photoresist removal agent. 如請求項1之方法,其中該晶圓係由銦氧化錫(ITO)玻璃、矽、二氧化矽、氮化矽、GaN、藍寶石、InGaN、AlInGaP、或陶器構成。 The method of claim 1, wherein the wafer is composed of indium tin oxide (ITO) glass, germanium, hafnium oxide, tantalum nitride, GaN, sapphire, InGaN, AlInGaP, or ceramics. 如請求項1之方法,其中在步驟(b2)中之該金屬係銅。 The method of claim 1, wherein the metal is copper in the step (b2). 如請求項1之方法,其中步驟(b2)係藉由在該晶圓上沉澱一薄金屬層,及隨後在該晶圓的該薄金屬層上電鍍一金屬層而進行。 The method of claim 1, wherein the step (b2) is performed by depositing a thin metal layer on the wafer and subsequently plating a metal layer on the thin metal layer of the wafer. 如請求項1之方法,其中在步驟(c2)中之該乾膜光阻係一包括感光性丙烯酸酯的負型乾膜光阻。 The method of claim 1, wherein the dry film photoresist in step (c2) comprises a negative dry film photoresist of a photosensitive acrylate. 如請求項1之方法,其中在步驟(d2)中之該光源係紅外線、寬帶紫外線、深紫外線、超紫外線、e-光束或x射線。 The method of claim 1, wherein the light source in the step (d2) is infrared light, broadband ultraviolet light, deep ultraviolet light, ultra ultraviolet light, e-light beam or x-ray. 如請求項1之方法,其中於步驟(e2)中使用具有0.1至1.5v/v%濃度的鹼性碳酸鈉水溶液。 The method of claim 1, wherein an aqueous alkaline sodium carbonate solution having a concentration of 0.1 to 1.5 v/v% is used in the step (e2). 如請求項1之方法,其中步驟(f2)係以一蝕刻溶液進行。 The method of claim 1, wherein the step (f2) is performed with an etching solution. 如請求項1之方法,其中該晶圓背面亦經保護。 The method of claim 1, wherein the back side of the wafer is also protected. 如請求項9之方法,其中該晶圓之背面係藉由在該晶圓背面層壓一乾膜光阻,及將該乾膜光阻曝光至光源以在該晶圓之該背面上形成曝光的光阻區域而保護。 The method of claim 9, wherein the back side of the wafer is formed by laminating a dry film photoresist on the back side of the wafer, and exposing the dry film photoresist to a light source to form an exposure on the back surface of the wafer. Protected by the photoresist area. 一種用於電鍍晶圓中矽穿孔的方法,其包括下列步驟:(a3)提供一具有矽穿孔的晶圓,(b3)在該晶圓上沉澱一薄金屬層,(c3)在該晶圓之該薄金屬層上層壓一乾膜光阻,(d3)通過一遮罩使該乾膜光阻曝光至光源以在該晶圓的複數通道上形成未曝光的光阻區域及在該晶圓的其他區域上形成曝光的光阻區域,(e3)使該乾膜光阻顯影以露出底下部分的該晶圓之該等通道,(f3)以一金屬電鍍該晶圓之該等通道直至其被填滿,及(g3)以一光阻移除劑從該晶圓移除該等曝光的光阻區域。 A method for etching a ruthenium in a wafer, comprising the steps of: (a3) providing a wafer having a ruthenium perforation, (b3) depositing a thin metal layer on the wafer, and (c3) depositing the wafer Laminating a thin film of photoresist on the thin metal layer, (d3) exposing the dry film photoresist to a light source through a mask to form an unexposed photoresist region on the plurality of channels of the wafer and on the wafer Forming an exposed photoresist region on other regions, (e3) developing the dry film photoresist to expose the underlying portions of the wafer, and (f3) plating the channels of the wafer with a metal until it is Filling, and (g3) removing the exposed photoresist regions from the wafer with a photoresist remover. 如請求項11之方法,其中該晶圓係由銦氧化錫(ITO)玻璃、矽、二氧化矽、氮化矽、GaN、藍寶石、InGaN、 AlInGaP、或陶器構成。 The method of claim 11, wherein the wafer is made of indium tin oxide (ITO) glass, germanium, germanium dioxide, tantalum nitride, GaN, sapphire, InGaN, Made up of AlInGaP, or pottery. 如請求項11之方法,其中在步驟(b3)與(f3)中之該金屬係銅。 The method of claim 11, wherein the metal is copper in steps (b3) and (f3). 如請求項11之方法,其中在步驟(c3)中之該乾膜光阻係一包括感光性丙烯酸酯的負型乾膜光阻。 The method of claim 11, wherein the dry film photoresist in step (c3) comprises a negative dry film photoresist of a photosensitive acrylate. 如請求項11之方法,其中在步驟(d3)中之該光源係紅外線、寬帶紫外線、深紫外線、超紫外線、e-光束或x射線。 The method of claim 11, wherein the light source in the step (d3) is infrared light, broadband ultraviolet light, deep ultraviolet light, ultra ultraviolet light, e-light beam or x-ray. 如請求項11之方法,其中於步驟(e3)中使用具有0.1至1.5v/v%濃度的鹼性碳酸鈉水溶液。 The method of claim 11, wherein an aqueous alkaline sodium carbonate solution having a concentration of 0.1 to 1.5 v/v% is used in the step (e3).
TW97135816A 2008-09-18 2008-09-18 Use of dry film photoresists in through-silicon via applications TWI390629B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97135816A TWI390629B (en) 2008-09-18 2008-09-18 Use of dry film photoresists in through-silicon via applications

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97135816A TWI390629B (en) 2008-09-18 2008-09-18 Use of dry film photoresists in through-silicon via applications

Publications (2)

Publication Number Publication Date
TW201013774A TW201013774A (en) 2010-04-01
TWI390629B true TWI390629B (en) 2013-03-21

Family

ID=44829470

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97135816A TWI390629B (en) 2008-09-18 2008-09-18 Use of dry film photoresists in through-silicon via applications

Country Status (1)

Country Link
TW (1) TWI390629B (en)

Also Published As

Publication number Publication date
TW201013774A (en) 2010-04-01

Similar Documents

Publication Publication Date Title
US20160276212A1 (en) Method For Producing Semiconductor Device
TWI685938B (en) Skip via structures
TWI655513B (en) Photolithographic pattern for forming fine pitch features
KR100386621B1 (en) Method for forming dual-damascene interconnect structures
US10497610B2 (en) Dual photoresist approach to lithographic patterning for pitch reduction
TWI390629B (en) Use of dry film photoresists in through-silicon via applications
US6511916B1 (en) Method for removing the photoresist layer in the damascene process
JP2004342873A (en) Semiconductor device and its manufacturing method
KR100640966B1 (en) A method for cleaning a semiconductor device
JP2011181640A (en) Method of forming wiring conductor
JP2008016553A (en) Method of manufacturing semiconductor device
JP2019087768A (en) Semiconductor device
TW548789B (en) Method of forming metal line
KR100596609B1 (en) Method for burying resist and method for manufacturing semiconductor device
KR20030074870A (en) Method for fabricating metal power line of semiconductor device
KR100755126B1 (en) Method for forming cu line of semiconductor device
KR100649312B1 (en) Manufacturing method of semiconductor device
JP2004040019A (en) Method for forming metal wiring
KR101868457B1 (en) Method for forming via hole and for manufacturing via contact with the same
KR20010047961A (en) method to shape line first dual damascene pattern use the oxide mask
KR100702801B1 (en) Method of fabricating metal lines by dual damascene process
KR100996160B1 (en) Method of manufacturing a capacitor in a semiconductor devices
US20190371652A1 (en) Integrated circuit chip package having reduced contact pad size
TW201942686A (en) Method of manufacturing semiconductor structure
TWI436451B (en) Semiconductor device structure and manufacturing method thereof

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees