TWI389457B - Double trigger logic circuit - Google Patents

Description

Double trigger logic

This creation relates to a combined logic circuit, and more particularly to a dual trigger logic circuit.

Digital systems are becoming more and more diverse. How to reduce the power consumption of the chip is the current major research direction. In all digital synchronization systems, one or more sets of clock systems are usually used, and the clock signal is used to control the movement of data. The clock system is composed of a system clock distribution network and a flip-flop. It is the most power-consuming part of the entire chip. The power consumption can be divided into static power consumption and dynamic power consumption. Power consumption is divided into switching power and short-circuit current power consumption, while static power consumption is mostly leakage current power consumption.

The technology to reduce power can be used to reduce static power and reduce dynamic power. Since dynamic power consumption is always much larger than static power consumption, the circuit we designed is mainly implemented to reduce the dynamic power consumption. The most effective way to reduce power consumption is to reduce the operating voltage, but the problem with lowering the voltage is the speed drop. Therefore, another feasible way is to use a dual-edge trigger design, so that the output yield can be reduced without In the case of throughput, the power is effectively reduced. Therefore, in the composition of the actual circuit, we use a pulse-triggered flip-flop to further reduce the loading capacitance and power consumption of the system clock.

Please refer to the structure of the conventional flip-flop as shown in "Figures 1, 2". It consists of two latches, which control the data sampling and data retention by the positive/negative edge of the clock signal. As shown in Figure 1, the master latch 1 performs data sampling. , the slave lock (slave latch) 2 to do the data retention action, in use, about the movement of the data, from a data input (Din) 3 to a data output (Qout) 4 is synchronized with a clock signal input The edge signal of the block 5, and the positive edge trigger mode is to sample only the positive edge signal of the data input terminal (Din) 3 at the clock signal input terminal (Clock) 5, and the negative edge trigger mode samples the data. The input terminal (Din) 3 is at the negative edge signal of the clock signal input terminal (Clock) 5, so that the data transfer operation can be completed, so each time the data transmission state needs to use two clock signals to complete The whole job.

As shown in Figure 2, the timing diagram of the flip-flop in Figure 1 represents a sample data (Sample Data) 7 and a hold data 8 (Hold Data) on the positive and negative edges of a clock signal 6. ), but this will produce a problem such as a race trough, so the time conditions should be considered and whether it is in line with the ability to keep the flip-flops working properly.

The double edge triggered flip flop (DETFF) means that it can use the clock signal 6 to complete the entire data transmission work every time the data is transmitted. Typically, The double-edge triggering flip-flop can store data in the positive or negative edge of the clock signal, but there is a long transmission delay time, and the capacitive load pushed by the clock signal input terminal (Clock) 5 is large, although It is still possible to store the data at the clock signal input terminal (Clock) 5 of the positive or negative edge, so the clock signal input terminal (Clock) 5 must be doubled as the original clock signal. The frequency becomes another new clock signal, so the clock frequency used by the double-edge triggering flip-flop is one-half of the clock frequency of the general single-edge triggering flip-flop, but the same data transmission rate can be achieved because The power consumption is proportional to the clock frequency of the operation, so its power consumption will also decrease, so double-edge triggered flip-flops are often proposed for use in power-reduced designs.

Compared with the single-edge flip-flop and the double-edge flip-flop, the structure of the double-edge flip-flop is more complicated than the single-edge flip-flop. It is not only used. The larger the wafer area, the more internal junctions and the switching capacitors, while reducing the benefits of reduced frequency.

In the application of the conventional technology, an additional explicit-pulsed-triggered flip-flop and an IMPlicit-pulsed-triggered flip-flop are developed. It can be divided into two types: single-edge pulse-trigger type and double-edge pulse-wave-type flip-flop. The external pulse-trigger type flip-flop circuit can be used in multi-string and parallel connection. Sharing, and the pulse wave generator of the embedded pulse-trigger type flip-flop is not shared, so the external pulse-trigger type flip-flop can reduce the overall power consumption, but it is in the string. When connected in parallel, the pulse wave may be too large, so the pulse wave cannot be generated. Therefore, the advantage of the external pulse-trigger type flip-flop has no embedded pulse-trigger type flip-flop, and the circuit has The obvious pulse generator will cause more energy consumption, and the operating frequency of the embedded pulse-triggered flip-flop is higher than that of the external pulse-trigger generator.

Therefore, the pulse-triggered flip-flop is designed due to the low complexity of the circuit design. It is becoming more and more popular in the application of the register; another important feature of the pulse generator is to control its operation mode. The traditional pulse generator can only be fixed in one mode, or please refer to Figure 3. As shown in the figure, it is a conventional dual mode logic circuit that uses a MUX circuit 9A to control two logic circuits: an AND logic circuit 9B and an XNOR logic circuit 9C, and a mode selection signal input E to the MUX circuit 9A. Transmission mode selection signal, but its logic circuit composition requires a lot of transistors, although its circuit composition is simple, but the load capacitance on a clock signal input (CLK) 9D is quite large, resulting in great power consumption.

While the development of low-power design technology, it is often required that the mode of single-pulse or double-pulse triggering must have multiple modes of operation, for example, in the data communication circuit during the data synchronization phase. Double-edge triggering doubles the frequency of effective work. Once synchronization is achieved, the circuit can be converted to single-edge triggering to reduce the effective clock to reduce power consumption. In the past, if such a circuit was designed, two designs would be designed. Different mode pulse generator circuits, single-edge pulse-triggered circuits are mostly composed of inverters plus AND or OR logic gates to generate positive or negative pulse signals; and double-edge pulse trigger circuits use inverters. Add XNOR logic gate and XOR logic gate to form another selection of MUX circuit.

The conventional CMOS circuit composition of logic circuits, in which the logic circuits of XOR, XNOR, AND, OR, and MUX are used, although the circuit composition is simple, but there is another threshold voltage loss problem, this is When the circuit can't operate at low voltage, it will This causes more power consumption. Due to the threshold voltage loss problem, this problem causes the circuit to have insufficient driving capability and short-circuit current. Therefore, in the case of conventional technology research, it is quite time-consuming to establish a custom circuit. It takes a lot of work, and it takes time to design, implement, characterize, and integrate. Therefore, it is desirable to provide a better timing specification and lowest power consumption to increase processing speed.

Therefore, the purpose of this creation is to utilize two logic circuits to form a low-complexity dual-trigger logic circuit.

Based on the above object, the present invention is a dual-trigger logic circuit, which is provided with a clock signal input terminal and a clock delay signal input terminal, and includes: a first PMOS transistor, a second PMOS transistor, and a first An NMOS transistor, a second NMOS transistor and a third PMOS transistor.

The first PMOS transistor is coupled to a mode select signal input E, the first PMOS transistor is coupled to the clock delay signal input terminal, and the second PMOS transistor is coupled to the first PMOS transistor, the second PMOS transistor The transistor is coupled to the clock signal input end, the first NMOS transistor is coupled to the first PMOS transistor, the second NMOS transistor is coupled to the clock signal input terminal A, and the second NMOS transistor is coupled to A third PMOS transistor is coupled to the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, and the third PMOS transistor are coupled to each other to generate an output signal.

With the above technical solution, the present invention is a dual trigger logic circuit having the following advantages:

First, such a combinational logic circuit is designed through a small number of transistors Logic gates, on the one hand, reduce the use of electronic components, with low complexity to reduce the load capacitance design of the clock system, can greatly reduce power consumption, and on the other hand, the dual operation mode is not limited to a certain use requirement.

Second, in order to reduce the complexity of the circuit, there is no power supply to the ground path, so when the transistor does not generate obvious short-circuit current during the transition of the conversion, resulting in power consumption, using XNOR and AND logic The difference in operation is used as a selection line for the control mode, so that the MUX circuit of the prior art is removed, which can reduce the delay time and make the power-delay-product (PDP) decrease a lot.

The detailed description of the present invention and the technical description thereof are now described in the following examples, but it should be understood that these examples are for illustrative purposes only and are not to be construed as limiting.

Please refer to FIG. 4 , which is a dual-trigger logic circuit for connecting a clock signal input terminal A and a clock delay signal input terminal B, which includes: a first PMOS transistor P1, a The second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2 and a third PMOS transistor P3.

The source of the first PMOS transistor P1 is coupled to a mode selection signal input E. The first PMOS transistor P1 is coupled to the clock delay signal input terminal B by a gate thereof, and the source of the second PMOS transistor P2. The pole is connected to the drain of the first PMOS transistor P1, and the gate of the second PMOS transistor is coupled to the clock signal input terminal A. The first NMOS transistor N1 has its gate and the first The gate of the PMOS transistor P1 is coupled to the second NMOS transistor N2. The second NMOS transistor N2 is coupled to the clock signal input terminal A, and the second NMOS transistor N2 is coupled to a third PMOS transistor P3. The drain of the second PMOS transistor P2, the drain of the first NMOS transistor N1, the drain of the second NMOS transistor N2 and the source of the third PMOS transistor P3 are connected and generate an output signal.

In addition, at least one first inverter 10 is disposed in front of the clock delay signal input terminal B, and the number of the at least one inverter 10 is set to three in the original creation, and the inverters 10 and the first The three PMOS transistors P3 are connected.

Please refer to Figure 5 again for the truth table of AND and XNOR. In order to reduce the circuit complexity, by observing the AND and XNOR truth tables, the difference between the two is only when the clock is used. When the signal input terminal A and the signal input terminal B of the clock delay signal input terminal are both "0", the AND output is "0" and the XNOR output is "1", and the difference can be used as the mode selection signal input. E's control selection method.

Please refer to Figure 6 for the AND/XNOR logic circuit diagram designed with reference to Figure 5. There is no power supply to the ground path in this circuit design, so there will be no obvious short circuit during the transition. The current causes power consumption, and the circuit diagram of Fig. 6 also removes the MUX circuit 9A in the conventional "Fig. 3", so that the delay time can be further reduced and the power delay product (power-delay-product, PDP) also drops a lot, but still has its shortcomings; please also refer to "Figure 5, 6", when the clock signal input terminal A, the clock delay signal input terminal B and the mode selection signal input E When the input signal is "000, 011, 111", the output will still have a threshold voltage decay. The problem of threshold voltage loss exists. When the circuit is applied to the pulse generator, when the two states "011 and 111" are generated at the positive edge of the clock, "0→1", please refer to "Figure 7". It can be seen that this problem can be solved by adding a second inverter 20 and a transistor 30 in "FIG. 7", which is a circuit diagram for solving the threshold voltage decay, if the circuit is applied to a pulse generator (Fig. When not shown, when the EAB of the input signal of the clock signal input terminal A, the clock delay signal input terminal B and the mode selection signal input E is "000", the circuit does not generate a pulse wave signal, so the input The problem of the signal does not affect the circuit of the pulse generator, so when connected to the pulse generator, since the pulse wave becomes narrower, the power consumption caused by the short-circuit current is also reduced, and there is no threshold voltage decay. (threshold voltage loss) problem.

Therefore, please refer to "Fig. 4, 7" at the same time, and the second inverter 20 added in "Fig. 7" can be replaced by the first inverter 10 in "Fig. 4". Therefore, in fact, only five transistors in "Figure 4" are required to form a dual-mode logic circuit. In this creation, three first inverters 10 are used as the clock delay function and the circuit diagram of "FIG. 7" is used. The composition is the "Figure 4" dual-mode logic circuit, and the circuit's Boolean algebra is as follows:

Example:

Please refer to "Figures 5 and 8" as an example. One clock input signal CLK, one clock delay input signal CLKD and the mode selection in Figure 8 The selection signal input E1 is compared with the input signal of the clock signal input terminal A, the clock delay signal input terminal B and the mode selection signal input E in "Fig. 5", which is set to a double pulse mode by using the original creation. The circuit diagram of the flip-flop is triggered, and the circuit implementation action is:

(1) When a mode selection signal input E1 is "1" (double edge pulse trigger generation mode): a. When a clock input signal CLK and a clock delay input signal CLKD are both "0" (the clock input signal) CLK falling edge): a first transistor MP1 and a second transistor MP2 are in an ON state, which generates a pulse signal Pulse of "1" to turn on a latch 40, and the data is input from a data input terminal. 50 is transmitted to a data output terminal 60; b. when the clock input signal CLK and the clock delay input signal CLKD are both "1" (the rising edge of the clock input signal CLK): a third transistor MN1 When a fourth transistor MN2 and a fifth transistor MP3 are in an ON state, the pulse signal Pulse is generated to be "1" to turn on the latch 40, and the data is transmitted from a data input terminal 50 to a data. The output terminal 60; c. the clock input signal CLK and the clock delay input signal CLKD are "01" or "10" (when the clock input signal CLK is fixed): the third transistor MN1 or the first When the fourth transistor MN2 is in the ON state, the pulse signal Pulse is "0" (no pulse generation), and the latch 40 is matched by a third inverter 70 thereof. Transistor to maintain the voltage of the output terminal 60 of the information.

(2) When the mode selection signal input E1 is "0" (single edge pulse wave generation mode): a. when the clock input signal CLK and the clock delay input signal CLKD are both "0" (the clock) The falling edge of the input signal CLK: the first transistor MP1 and the second transistor MP2 are in an ON state, and the pulse signal Pulse is "0" (no pulse generation), and the latch 40 is the third The inverter 70 performs a circuit feedback operation to maintain the voltage of the data output terminal 60. b. When the clock input signal CLK and the clock delay input signal CLKD are both "1" (the rise of the clock input signal CLK) The third transistor MN1, the fourth transistor MN2 and the fifth transistor MP3 are in an ON state, the pulse signal Pulse is "1" (pulse generation), and the latch 40 is turned on, and Data is transmitted from the data input terminal 50 to the data output terminal 60; c. when the clock input signal CLK and the clock delay input signal CLKD are "01" or "10" (the clock input signal CLK is fixed) Time): the third transistor MN1 or the fourth transistor MN2 is in an ON state, the pulse signal Pulse is "0" (no pulse generation), and the latch 40 is caused by the third counter The phaser 70 acts as a circuit to maintain the voltage at the data output 60.

In summary, we propose dual triggering using AND-XNOR logic modules. Type logic circuit capable of supporting two pulse trigger modes: single-edge triggered and double-edge triggered, and saves a lot in using the number of transistors and layout area, so this Creation can achieve high-speed and low-power operation expectation, so whether it is promoted or applied in the industry, the subsequent huge benefits will hope to do its part for the electronics industry.

However, the foregoing is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. That is, the equal changes and modifications made by the patent application scope of this creation are covered by the scope of the creation patent.

Conventional part:

1‧‧‧Master lock (master latch)

2‧‧‧servant latch (slave latch)

3‧‧‧Data input (Din)

4‧‧‧ Data output (Qout)

5‧‧‧clock signal input (Clock)

6‧‧‧ clock signal

7‧‧‧Sampling data (Sample Data)

8‧‧‧Hold Data

9A‧‧‧MUX circuit

9B‧‧‧AND logic circuit

9C‧‧‧XNOR logic circuit

9D‧‧‧clock signal input (CLK)

E‧‧‧ mode selection signal input

This creative part:

10‧‧‧First Inverter

20‧‧‧Second inverter

30‧‧‧Optoelectronics

40‧‧‧Locker

50‧‧‧ data input

60‧‧‧ data output

70‧‧‧ third inverter

A‧‧‧ clock signal input

B‧‧‧clock delay signal input

C‧‧‧ signal line

CLK‧‧‧ clock input signal

CLKD‧‧‧ clock delay input signal

Pulse‧‧‧ Pulse Signal

E‧‧‧ mode selection signal input

E1‧‧‧ mode selection signal input

P1‧‧‧First PMOS transistor

P2‧‧‧Second PMOS transistor

P3‧‧‧ Third PMOS transistor

N1‧‧‧First NMOS transistor

N2‧‧‧Second NMOS transistor

MP1‧‧‧first transistor

MP2‧‧‧second transistor

MN1‧‧‧ third transistor

MN2‧‧‧4th transistor

MP3‧‧‧ fifth transistor

Figure 1 is a schematic diagram of a conventional flip-flop.

Figure 2 is a timing diagram of a conventional master-servant flip-flop.

Figure 3 is a schematic diagram of a conventional dual mode logic circuit.

Figure 4 is a circuit diagram of a dual trigger logic circuit of the present invention.

Figure 5 is an AND and XNOR truth table.

Figure 6 is a schematic diagram of an AND/XNOR logic circuit designed according to the AND and XNOR truth tables.

Figure 7 is a circuit diagram for solving the threshold voltage decay.

Figure 8 is a circuit diagram of the creation of a dual pulse mode trigger flip-flop.

10‧‧‧First Inverter

A‧‧‧ clock signal input

B‧‧‧clock delay signal input

P1‧‧‧First PMOS transistor

P2‧‧‧Second PMOS transistor

N1‧‧‧First NMOS transistor

N2‧‧‧Second NMOS transistor

P3‧‧‧ Third PMOS transistor

C‧‧‧ signal line

E‧‧‧ mode selection signal input

Claims (5)

A dual-trigger logic circuit for connecting a clock signal input end and a clock delay signal input end, comprising: a first PMOS transistor, a source of the first PMOS transistor and a mode selection signal input E Connecting, the first PMOS transistor is coupled to the clock-delay signal input terminal by a gate thereof; and a second PMOS transistor, a source of the second PMOS transistor is coupled to a drain of the first PMOS transistor, a gate of the second PMOS transistor is coupled to the clock signal input terminal; a first NMOS transistor having a gate coupled to a gate of the first PMOS transistor; and a first a second NMOS transistor, the second NMOS transistor is coupled to the clock signal input terminal, and the second NMOS transistor is coupled to a third PMOS transistor, and the second PMOS transistor has a drain The first NMOS transistor drain, the drain of the second NMOS transistor and the source of the third PMOS transistor are connected and generate an output signal. The dual-trigger logic circuit of claim 1, wherein the clock signal input terminal A is connected to any one of a flip-flop, an adder and a multiplexer, a latch, a register, and a counter. The dual-trigger logic circuit of claim 1, wherein at least one inverter is disposed between the clock signal input end and the clock delay signal input end. The dual-trigger logic circuit of claim 3, wherein the optimal number of the at least one inverter is three. The dual-trigger logic circuit of claim 4, wherein the third PMOS transistor is coupled between the inverters by a signal line C.