TWI389123B - System for operating a memory array and method of the same - Google Patents

Description

System and method for operating a memory array

The present invention generally relates to a memory device and more particularly to a system and method for operating a memory device.

Flash memory is a type of non-volatile memory that can be written and erased multiple times and can retain its contents without power consumption. Nitride read only memory (NROM), a type of flash memory, can include an array of N columns by M rows of NROM cells for data storage. Each of the NROM cells may include a metal oxide semiconductor (MOS) transistor having a source, a drain, and a stacked gate structure formed on the P-type substrate. The gate structure can include a polysilicon layer overlying an oxide/nitride/oxide (ONO) stack layer, wherein the nitride layer acts as an eletron trapping layer.

Each NROM unit can store one or more bits of data. For example, a two-bit memory component allows two bits of data to be stored in a single cell, one bit being stored in a trapped layer adjacent to the source region and the other being stored in a trapped layer adjacent to the drain region in. The presence or absence of a negative charge in one of the regions of the trapped layer may indicate the state of the corresponding bit.

In a multi-bit memory device that utilizes an ONO stacked layer to store charge, the charge added or removed during the stylization and erase operations should be limited to the respective source and drain regions of the cell. However, in fact, at The accumulation and removal of charge in one of the source and drain regions may affect the charge in another region, thus changing the read, program, and erase features of the cell over time. Finally, the accumulation of charge changes the threshold voltage used to determine the state of the individual bits in the cell. This is due to the threshold voltage shift due to the interaction between the two regions of the cell, commonly referred to as bit disturb. In addition, the charge loss after repeated cycles of the memory cells also causes the threshold voltage (especially the program threshold voltage) to shift. The threshold voltage change due to bit interference and/or charge loss prevents the memory component from correctly sensing the state of each bit of the cell.

Determining the state of each bit of a multi-bit cell (including stylized state or at least by comparing the value from the memory cell (eg, the voltage level of the data bit) with a reference value Erase status). In general, the reference cells are pre-programmed and set to an erased state during initial fabrication so that a stable reference value can be provided. When the value from the memory unit is greater than the reference value, it is determined that the memory unit is in the erased state. On the other hand, when the value of the memory unit is less than the reference value, it is determined that the memory unit is in a stylized state. Figure 1 illustrates a diagram illustrating the sensing margin of a memory component. Line 102 represents the ideal program threshold voltage for the memory cell over time. Line 104 represents an example of a change in the program threshold voltage of a memory cell over time, taking into account effects such as bit interference and charge loss. Line 106 represents the ideal erase voltage for the memory cell over time. Line 108 represents the erasure of the memory cell in consideration of effects such as bit interference and charge loss. An example of a change in pressure over time. Line 110 represents the reference value provided by the reference unit of the memory element in the prior art, which maintains a constant value over time as shown in FIG. Referring to FIG. 1, the sensing margin 112 between the reference value 110 and the program threshold voltage 104 of the memory cell may decrease over time due to effects such as bit interference and/or charge loss effects, which will Increase the likelihood of sensing errors and reduce the reliability of memory components.

One example consistent with the present invention provides a system for operating a memory component. Such a memory component can include: a memory array having a plurality of memory cells; a plurality of word lines each coupled to at least one of the memory cells in the respective columns; a plurality of bit lines connected to at least one of the memory cells in the corresponding row; and a plurality of dynamic reference cells, each coupled to one of the word lines, to provide A dynamic reference value used to determine the state of at least one of the associated memory cells. The dynamic reference value can reflect a change in the threshold value of at least one of the associated memory cells.

In another example, a system for operating a memory component can include: a memory array having a plurality of memory cells; a plurality of word lines each coupled to at least one of the memory cells in the respective column; a plurality of bit lines each coupled to at least one of the memory cells in the respective row; a plurality of dynamic reference cells each coupled to one of the word lines for providing an associated memory for determining a dynamic reference value of a state of at least one of the body units; and a control circuit for programming the dynamic reference unit, So that the dynamic reference value can reflect a change in the threshold value of at least one of the associated memory cells.

Yet another example consistent with the present invention provides a method of operating a memory component. The method can include: stylizing a dynamic reference unit; generating a dynamic reference value that reflects a change in a threshold value of the memory unit; reading a unit value from the memory unit; and determining a state of the memory unit based on the dynamic reference value.

The above general description and the following detailed description are to be considered as illustrative and not restrictive

The following summary, as well as the following detailed description of the embodiments of the invention However, it should be understood that the invention is not limited to the precise arrangements and instrumentalities shown.

2 illustrates an illustrative diagram of a system 10 for operating a memory component, such as an NROM array, in an example consistent with the present invention. System 10 can include a memory array 12, a set of dynamic reference cells 14, a small cell reference array 16, a number of main sense amplifiers 18, a dynamie referenee sensing amplifier 20, a number of comparators 22, and a number of inputs/ Output (Input/Output, I/O) circuit 30.

In one example, system 10 can be provided on a single substrate. This substrate can have one or more high density regions and low density peripheral regions. One or more M x N memory arrays 12 can be placed in a high density region. In an instance The dynamic reference unit 14 is adjacent to the memory array 12 in one of the high density regions of the substrate. The aforementioned peripheral area includes sensing amplifiers 18 and 20, comparators 22, and I/O circuit 30. In an example, a mini-cell referenee array 16 having a plurality of small reference cells can also be placed in the peripheral area.

The memory array 12 can include a number of memory cells arranged in M rows and N columns. Each of the memory cells can include a MOS transistor having a stacked gate structure. The stacked gate structure may include a polysilicon layer on the ONO layer, the ONO layer having a tantalum nitride layer sandwiched between two ruthenium dioxide layers. Memory cells located in the same column may be connected via word line 24, while memory cells located in the same row may be connected via bit line 26. In other words, system 10 can have a number of word lines 24 each coupled to one or more memory cells in a respective column and a plurality of bit lines 26 each coupled to one or more memory cells in a respective row.

The set of dynamic reference units 14 can include a number of dynamic reference units that are interconnected via a bit line 28. The dynamic reference cells can be placed adjacent to or coupled to the memory array 12. In an example, each of the dynamic reference cells is coupled to the memory cell via a column of word lines. Each of the dynamic reference cells provides a dynamic reference value (such as a read threshold voltage in an example) for the associated memory cell to determine the state of the memory cell. By sharing the same word line with the memory cells, each of the dynamic reference cells can operate through the same cyclos as the associated memory cells, and thereby experience the same effects as on the memory cells. Or similar Effects such as charge loss.

The small cell reference array 16 includes at least one small reference cell coupled to each of the main sense amplifiers 18 for providing a static reference value. The small reference unit can be programmed once at a fixed value by the memory manufacturer to be substantially stable over time. In an example, where the dynamic reference unit can provide a dynamic reference value in the read mode of system 10, small unit reference array 16 can be provided for the memory unit in a verify mode, such as a program verify mode. Stable reference value. In an example, the dynamic reference unit can provide a reference value for the memory unit in both the read mode and the verify mode of system 10.

The main sense amplifier 18 and the dynamic reference sense amplifier 20 can be placed in a peripheral area. Each of the main sense amplifiers 18 can be coupled to one of the bit lines 26 for reading a cell value of one of the memory cells of a row. Dynamic reference sense amplifier 20 can be coupled to bit line 28 for reading a reference value of one of the dynamic reference cells.

Each comparator 22 can be coupled to one of the main sense amplifier 18, the dynamic reference sense amplifier 20, and a small unit reference unit. In an example, comparator 22 can be used to determine the state of the memory cell by comparing the cell value provided by associated main sense amplifier 18 to the dynamic reference value provided by dynamic reference sense amplifier 20. . Based on the above comparison, the state of the memory cell can be determined. A comparison result can then be provided to one of the I/O circuits 30 for output.

In some examples, the dynamic reference unit can be pre-programmed such that the reference value is visible to the programized threshold voltage (Program Vt) of the memory unit. Variety. As an example, pre-programming can be performed during the manufacturing process of the memory system. 3 is a flow diagram 300 showing an exemplary process of a stylized dynamic reference unit. Referring to Figure 3, the foregoing process can begin with step 302 (pre-erase stylization) during which a word line can be selected and a negative charge such as a charge of about 0 to 10 volts can be applied to the nitride storage layer of the associated memory cell. . A number of charge pulses can be applied to the associated memory cell until the cell voltage exceeds the verify level. The number of pulses required to exceed the verification level (ie, the pulse count) reflects the low boundary of the programmed threshold voltage. The pulse count information can be recorded in a register or fuse, which is also the type of memory unit responsible for storing operational related information associated with the word line.

Subsequent to step 302, at step 304, a charge such as a charge of about -5 volts to 5 volts may be applied to erase data in all of the memory cells. Then step 306 (erasing verification and over erasing unit detection) is performed to verify and detect whether the data in all the memory cells is properly erased. For the over erase unit, step 308 (post-erase stylization) is performed to apply a negative charge to the over-erased eells. Steps 306 and 308 are repeated until all memory cells are verified to be in the erased state. Thereafter, initialization of the dynamic reference unit is performed at step 310 by programmatically (i.e., writing) the dynamic reference unit with information of the pulse count of each word line obtained in step 302.

4 is an illustrative diagram illustrating a sensing margin for an example consistent with the present invention. Line 402 represents the ideal program threshold voltage for the memory cell to remain constant over time. Line 404 represents the program threshold voltage of the memory unit at any time. The change, the change can be caused by effects such as bit interference and charge loss. Line 406 represents the ideal erase threshold voltage for the memory cell that remains constant over time. 408 represents the change in the threshold voltage of the memory cell over time, and the change can be caused by effects such as bit interference and charge loss. Line 410 illustrates an example of a dynamic reference value provided by a dynamic reference unit. In an example, the dynamic reference value can vary over time. For example, the dynamic reference value 410 can be programmed according to the process described above to provide a reference value to the associated memory that reflects the characteristics of the memory, which can vary over time. In one example, the difference between the reference value and the corresponding program threshold voltage 404 of the memory unit can be maintained substantially stable over time. In other words, the sense margin 412 (ie, the difference between the program threshold voltage 404 and the dynamic reference 410) can be substantially stable.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧System

12‧‧‧ memory array

14‧‧‧Dynamic reference unit

16‧‧‧Small unit reference array

18‧‧‧Main sense amplifier

20‧‧‧Dynamic Reference Sense Amplifier

22‧‧‧ Comparator

24‧‧‧ character line

26, 28‧‧‧ bit line

30‧‧‧Input/output circuits

Lines 102, 104, 106, 108, 110‧‧

112, 412‧‧‧Sense margin

300‧‧‧ Flowchart

302~310‧‧‧Steps

Lines 402, 404, 406, 408, 410‧‧

1 is a diagram of the sensing margin of a memory element in the prior art.

2 is a block diagram of an exemplary embodiment of an NROM memory in accordance with the present invention.

3 is a flow chart showing an exemplary process of a stylized dynamic reference unit.

4 is a diagram of a sensing margin of an exemplary embodiment of the present invention.

10‧‧‧System

12‧‧‧ memory array

14‧‧‧Dynamic reference unit

16‧‧‧Small unit reference array

18‧‧‧Main sense amplifier

20‧‧‧Dynamic Reference Sense Amplifier

22‧‧‧ Comparator

24‧‧‧ character line

26, 28‧‧‧ bit line

30‧‧‧Input/output circuits

Claims (12)

A system for operating a memory array, comprising: a memory array having a plurality of memory cells; a plurality of word lines each coupled to at least one of the memory cells in a corresponding column; The plurality of memory cells are each coupled to at least one of the memory cells in the corresponding row; a dynamic reference unit of each group, each dynamic reference cell being coupled to one of the word lines to provide a dynamic a reference value for determining a state coupled to at least one of the plurality of memory cells on a word line corresponding to the dynamic reference cell; a plurality of main sense amplifiers capable of reading coupling to a cell value of at least one of the plurality of memory cells of the corresponding word line; a dynamic reference sense amplifier capable of reading a dynamic value from one of the dynamic reference cells; a small cell reference array capable of Providing a reference value that remains substantially stable over time; and a plurality of comparators, each comparator being coupled to a respective one of the main sense amplifiers, the dynamic reference sense amplifier, and the small unit reference array Comparing the cell value, the dynamic value, and the stable reference value directly from the small cell reference array to determine a state of the memory cell of the corresponding row, wherein the same word line is shared by the memory cell Each of the dynamic reference units is operable to pass the same cycles as the associated memory unit, wherein each cycle includes stylization and wiping In addition, the dynamic reference value can reflect a change in a threshold value of at least one of the plurality of memory cells coupled to the corresponding word line. A system for operating a memory array as described in claim 1, wherein the dynamic reference unit of the group is adjacent to the memory array. The system for operating an array of memory according to claim 1, wherein the dynamic reference unit is capable of causing the dynamic reference value and the at least one of the plurality of memory units coupled to the corresponding word line. The difference between the limits remains substantially stable. The system for operating an array of memory as described in claim 1 further includes a control circuit capable of programming the dynamic reference units. A system for operating a memory array as described in claim 4, wherein the control circuit is a low boundary of the threshold of at least one of the memory cells connected to the corresponding word line (low) Boundary) to program the dynamic reference units. A system for operating a memory array, comprising: a memory array having a plurality of memory cells; a plurality of word lines each coupled to at least one of the memory cells in a corresponding column; The plurality of memory cells are each coupled to at least one of the memory cells in the corresponding row; a dynamic reference unit of each group, each dynamic reference cell being coupled to one of the word lines to provide a dynamic a reference value, the dynamic reference value being used to determine a state of coupling to at least one of the plurality of memory cells corresponding to a character line of the dynamic reference unit; a plurality of main sense amplifiers capable of reading cell values of at least one of the memory cells coupled to the corresponding word line; dynamic reference sense amplifiers capable of reading from the dynamic reference cells a dynamic value of one; a small cell reference array capable of providing a substantially stable reference value over time; a plurality of comparators, each comparator being coupled to a corresponding one of the main sense amplifiers, the dynamic reference sense amplifier, and the a small cell reference array for comparing the cell value, the dynamic value, and the stable reference value directly from the small cell reference array to determine a state of the memory cell of the corresponding row; and a control circuit capable of stylizing the dynamics a reference unit, wherein by sharing the same word line with the memory unit, each of the dynamic reference units is operable to pass the same cycles as the associated memory unit, wherein each cycle Including stylization and erasing, the dynamic reference value can reflect a presence of at least one of the memory cells coupled to the corresponding word line Value change. A system for operating a memory array as described in claim 6 wherein the dynamic reference unit of the group is adjacent to the memory array. The system for operating an array of memory according to claim 6, wherein the dynamic reference unit is capable of causing the dynamic reference value and the at least one of the plurality of memory units coupled to the corresponding word line. The difference between the limits remains substantially stable. The operating memory array system as described in claim 6 The control circuit is configured to program the dynamic reference cells with a low boundary of the threshold value of at least one of the memory cells connected to the corresponding word line. A method of operating a memory component, the method comprising the steps of: accessing a memory array having a plurality of memory cells; and programming a dynamic reference cell coupled to each of the respective columns a plurality of word lines of at least one of the memory cells, and the dynamic reference unit can provide a dynamic reference value, the dynamic reference value being capable of reflecting a memory cell coupled to a word line a change in the threshold value; reading a unit value of the memory unit from one of the main sense amplifiers coupled to a corresponding one of the memory cells; reading from a dynamic reference sensing coupled to the dynamic reference unit The dynamic reference value of the amplifier; and determining the state of the memory cell by comparing the cell value, the dynamic reference value, and a stable reference value from a small cell reference array through a comparator. The method of operating a memory component according to claim 10, wherein the programming the dynamic reference unit comprises: programming the dynamic reference unit such that the dynamic reference value and the threshold of the memory unit are The difference between the two remains substantially stable. The method of operating a memory component according to claim 10, wherein the programming the dynamic reference unit comprises: Pre-wiping the memory unit; obtaining a low boundary of the threshold of the memory unit; programming the dynamic reference unit with the low boundary of the threshold of the memory unit.