TWI386050B - Readout circuit for an image sensor - Google Patents

Description

Image sensor readout circuit

The present invention relates to image sensors, and more particularly to a readout architecture for an image sensor having a horizontal binning function.

Semiconductor image sensors, such as charge coupled devices (CCDs) or complementary metal oxide semiconductor (CMOS) sensors, are commonly used in cameras or cameras to convert visible light images into electrical signals for subsequent storage and transmission. Or display.

For today's image sensors, a column amplifier (CA) is used to read the image signal of each line. One reason for giving gain to the signal at the front stage of the analog chain is to obtain a better signal-to-noise ratio (SNR). The first figure shows the readout architecture of a conventional image sensor in which each row (co11, co12...) is connected to a corresponding row amplifier (CA1, CA2, ...), respectively. Next, the signals are sequentially transmitted to a programmable gain amplifier (PGA) by the switching device. The reset signal of the sample-and-hold-reset (SHR) capacitor C _SHRn (n=1, 2...) in each row is sequentially transmitted to the programmable gain amplifier (PGA). The image signals of the sample-and-hold-signal (SHS) capacitor C _SHSn (n=1, 2...) in each row are also sequentially transmitted to the programmable gain amplifier ( PGA).

As more and more pixels (or light quads) are produced in the image sensor, the area of each pixel and its image intensity will be relatively small. In order to enhance image intensity for better signal-to-noise ratio (SNR), it is often necessary to add signals (or called binning) of multiple pixels. The second figure shows the readout architecture of a conventional image sensor with combined functions, where each row (co11, co12...) is connected to a corresponding row amplifier (CA1, CA2, ...), respectively. The signals of the multiple lines are added (or combined) by a multiplexer (MUX) before the signal is transmitted to the programmable gain amplifier (PGA). Then, the output of the multiplexer (MUX) is sequentially transferred to the programmable gain amplifier (PGA) via the switching device. Since the signals of the rows and rows are combined, the combination shown in the second figure is called a horizontal combination technique.

In the conventional image sensor readout architecture shown in the first figure, multiple row amplifiers CA are required. As the number of rows increases, the area of the wafer occupied by the row amplifier CA becomes considerable. In the readout architecture of the conventional combined image sensor shown in the second figure, signal combination after the line amplifier CA is disadvantageous to its signal-to-noise ratio (SNR).

In view of the above-mentioned shortcomings of the conventional image sensor readout architecture, it is desirable to propose a novel readout architecture for image sensors to increase signal to noise ratio and reduce wafer area.

In view of the above, one of the objects of the present invention is to provide a readout architecture for an image sensor, particularly for an image sensor having a horizontal binning function for improving signal to noise ratio (SNR) and reducing Wafer area.

According to an embodiment of the invention, the readout circuit of the image sensor comprises a row of amplifiers (CA); and a plurality of capacitors/switches, each group comprising a capacitor and a switch connected to the plurality of row nodes of the image sensor One. The readout circuit further includes a multiplexer coupled between the complex capacitor/switch group and the input of the row amplifier; and an associated double sampling (CDS) circuit for receiving the output of the line amplifier. The readout circuit further includes a switching device for sequentially transmitting the output of the CDS circuit, and an amplifier for receiving the output of the switching device.

The third figure shows the readout architecture of an image sensor with a horizontal binning function in accordance with an embodiment of the present invention. The image sensor can be, but is not limited to, a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS) sensor for converting an image of visible light into an electrical signal. The readout architecture of this embodiment can be applied to digital image processing devices such as, but not limited to, cameras or cameras.

In this embodiment, each row (co11, co12...) or bit line of the image sensor is electrically coupled to each other via the capacitor Cn and the switch phin (n=1, 2...), respectively. The input of the MUX of the tool. For the sake of simplicity, the transistors (or switches) and their control signals in the drawings use the same symbols. One of the plates of the capacitor Cn is coupled to each row (co11, co12...), and the switch phin (n=1, 2...) is coupled between the other plate of the capacitor Cn and the input of the multiplexer MUX. The multiplexer MUX can be used to add (or binning) signals of multiple lines (co11, co12...). In another embodiment, the multiplexer MUX is operating in a "non-binning" state.

The output of the multiplexer MUX is fed to a row of amplifiers CA1. In the preferred embodiment, only a single row amplifier CA1 is used instead of using multiple row amplifiers (CAn, n = 1, 2...) as in the conventional architecture (as shown in the first and second figures). . Thereby, a considerable wafer area can be saved. In another embodiment, other line amplifiers CAn (n = 2, 3...) as shown by the dashed lines in the third figure may be used.

Referring again to the third figure, the feedback capacitor Cf is coupled between the output of the line amplifier (eg, CA1) and the input. The CA reset switch CA_rst is also coupled between the output of the line amplifier (eg, CA1) and the input.

A correlated double sampling (CDS) circuit includes a sample-and-hold-reset_signal (SHR) switch (SHRn, n=1, 2...) and a sample-and-hold- A sample-and-hold-image-signal (SHS) switch (SHSn, n = 1, 2...) that receives the output of the line amplifier CAn (n = 1, 2, ...), respectively. The SHR switch and the SHS switch are respectively coupled to the SHR capacitor C _SHRn (n=1, 2...) and the SHS capacitor C _SHSn (n=1, 2...). In the preferred embodiment, only a single CDS circuit 10 is used, rather than multiple CDS circuits as used in conventional readout architectures (as shown in the first and second figures). Thereby, a considerable wafer area can be saved. In another embodiment, other CDS circuits as indicated by the dashed lines in the third figure may be used.

Next, the signals are sequentially transmitted to an amplifier, such as a programmable gain amplifier (PGA). The programmable gain amplifier PGA can be a differential amplifier. The reset signal at the SHR capacitor C _SHR1 is sequentially transmitted to the programmable gain amplifier PGA via a switching device 12 via the first path 12A, and the image signal at the SHS capacitor C _SHS1 is also controlled by the switching device 12 And sequentially transmitted to the programmable gain amplifier (PGA) via the second path 12B. Furthermore, the CDS circuit 10 further includes a switch SW; when the binning operation is completed, the signal in the SHR capacitor C _SHR and the SHS capacitor C _SHS is fed to the next amplifier (for example, PGA). The switch SW is closed.

The fourth A diagram shows the pixel circuit of the first row of the image sensor of the embodiment of the present invention, and the fourth B diagram shows the pixel circuit of the second row. Each pixel circuit includes a reset transistor rstn (n=1, 2), a source follower sfn (n=1, 2), a selection transistor seln (n=1, 2), and a transmission power Crystal (or transfer gate) txn (n = 1, 2). In the figure, when the reset transistor rstn is turned on, it can be used to reset the photodiode Dn (n = 1, 2) to a reset reference voltage. When the source follower sfn is turned on, it can be used to buffer the image signal of the photodiode Dn. When the selection transistor seln is turned on by the word line, the reading of the pixel image signal is allowed. When the transmission transistor txn is turned on, it can be used to transmit the pixel image signal of the photodiode Dn. The pixel circuit of the image sensor provides an output to a row node (coln, n = 1, 2) that is coupled to the input of the third mode readout circuitry.

The fifth diagram shows the correlation signal timing diagrams of the third and fourth A/B diagrams in the combined binning mode. In operation, first, the CA reset switch CA_rst (100) is closed to reset the line amplifier CA1. The SHR switch is closed (101) such that the CA reset signal is stored in the SHR capacitor C _SHR . At this stage, the SHS switch is also closed (102). In practice, there will be an overlap between the active SHR signal and the active SHS signal, in order to prevent the coupling effect. In another embodiment, the SHS switch at this stage is open. At the same time, the reset transistor rstn is turned on (103). Next, by closing the switch phin (n = 1, 2) (104), the output reset signal of the pixel circuit (fourth A/B map) is received and stored in the capacitor Cn (n = 1, 2).

Next, the transfer transistor txn of the pixel circuit (fourth A/B map) is turned on (105). Thereby, the input voltage of the line amplifier CA is equivalent to the image signal minus the stored reset signal; the input voltage is then amplified by the line amplifier CA, and the SHS switch is continuously closed, but the SHR switch is turned off (106) . Thereby, the image signal is thus stored in the SHS capacitor C _SHS . In a binning operation, the multiplexer MUX can be used to add (or combine) signals of multiple lines (co11, co12...).

According to a preferred embodiment of the present invention, since only a single row amplifier CA and a single CDS circuit 10 are used, a considerable wafer area can be saved. In other words, with the multiplexer MUX, each row of amplifiers can be repeatedly used and shared between multiple lines. Furthermore, the combination of pixels before the line amplifier can improve the signal to noise ratio (SNR).

The sixth graph shows the correlation signal timing diagrams of the third and fourth A/B diagrams in the normal mode. In operation, first, when the first switch phi1 is closed (200), the output of the first row of pixel circuits (fourth A picture) is connected to the readout architecture (third figure). In this cycle 200, the operations of the first row of pixel circuits and the readout architecture are similar to those of the fifth diagram, and therefore will not be described again. Next, when the second switch phi2 is closed (201), the output of the second row of pixel circuits (fourth B) is connected to the readout architecture (third diagram). In this period 201, the operation of the second row of pixel circuits and the readout architecture is similar to that of the fifth diagram, and therefore will not be described again.

The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

10. . . Associated Double Sampling (CDS) Circuit

12. . . Switching device

12A, 12B. . . path

100-106. . . (combination mode) time point of the relevant signal

200-201. . . (normal mode) time period of the relevant signal

Co11, co12. . . Row

CA1, CA2. . . Line amplifier (CA)

CA_rst. . . CA reset switch

C _f . . . Feedback capacitor

C1, C2. . . capacitance

C _SHR1 , C _SHR2 . . . SHR capacitor

C _SHS1 , C _SHS2 . . . SHS capacitor

D1, D2. . . Light secondary body

MUX. . . Multiplexer

PGA. . . Programmable gain amplifier

Phi1, phi2. . . switch

Rst1, rst2. . . Reset transistor

SHR. . . Sample-and-hold-reset (SHR) switch

SHS. . . Sample-and-hold-image (SHS) switch

SW. . . switch

Sf1, sf2. . . Source follower

Se11, se12. . . Select transistor

tX1, tX2. . . Transmission transistor (transmission gate)

The first figure shows the readout architecture of a conventional image sensor.

The second figure shows the readout architecture of a conventional image sensor with combined functions.

The third figure shows the readout architecture of an image sensor with a horizontal binning function in accordance with an embodiment of the present invention.

The fourth A diagram shows the pixel circuit of the first row of the image sensor of the embodiment of the present invention, and the fourth B diagram shows the pixel circuit of the second row.

The fifth diagram shows the correlation signal timing diagrams of the third and fourth A/B diagrams in the combined binning mode.

The sixth graph shows the correlation signal timing diagrams of the third and fourth A/B diagrams in the normal mode.

12. . . Switching device

12A, 12B. . . path

Co11, co12. . . Row

CA1, CA2. . . Line amplifier (CA)

CA_rst. . . CA reset switch

Cf. . . Feedback capacitor

C1, C2. . . capacitance

C _SHR1 , C _SHR2 . . . SHR capacitor

C _SHS1 , C _SHS2 . . . SHS capacitor

MUX. . . Multiplexer

PGA. . . Programmable gain amplifier

Phi1, phi2. . . switch

SHR. . . Sample-and-hold-reset (SHR) switch

SHS. . . Sample-and-hold-image (SHS) switch

SW. . . switch

Claims (15)

An image sensor readout circuit comprising: at least one row of amplifiers (CA), when reset, generates a CA reset signal; a capacitor and a switch are connected to a row of nodes of the image sensor; a multiplexer coupled between the capacitor/switch and an input of the line amplifier; a correlated double sampling (CDS) circuit for receiving an output of the line amplifier; and a switching device coupled to the CDS circuit And the amplifier, wherein the switching device is configured to sequentially transmit the output of the CDS circuit to the amplifier; wherein the CDS circuit comprises: a sample-and-hold-reset signal (SHR) switch for sampling the CA a reset signal; an SHR capacitor coupled to the SHR switch for holding the CA reset signal; and a sample-and-hold image signal (SHS) switch for sampling the image signal of the image sensor; An SHS capacitor coupled to the SHS switch for maintaining the image signal; The signal stored in the SHR capacitor is sequentially transmitted to one of the two differential inputs of the amplifier by the switching device, and the signal stored in the SHS capacitor is sequentially transmitted to another difference of the amplifier by the switching device. Input. The readout circuit of the image sensor of claim 1, wherein one of the capacitor plates is coupled to the row node, and the switch is coupled to the other electrode of the capacitor and the multiplexer input between. The readout circuit of the image sensor according to claim 1, wherein the multiplexer is used to add signals of the plurality of rows. The readout circuit of the image sensor according to claim 1, wherein the multiplexer allows only a single line of image signals to pass at each time. The readout circuit of the image sensor according to claim 1 further includes a feedback capacitor coupled between the output of the line amplifier and the input. The readout circuit of the image sensor according to claim 5 further includes a CA reset switch coupled between the output and the input of the line amplifier. The readout circuit of the image sensor according to claim 1, further comprising an amplifier for receiving an output of the CDS circuit. The readout circuit of the image sensor of claim 7, wherein the amplifier comprises a programmable gain amplifier (PGA). A readout circuit for an image sensor, comprising: a row of amplifiers (CA), when reset, generates a CA reset signal; a plurality of capacitors/switch groups, each group comprising a capacitor and a switch, the connection thereof One of a plurality of row nodes of the image sensor; a multiplexer coupled between the complex capacitor/switch group and the input of the row amplifier; and an associated double sampling (CDS) circuit for receiving the row An output of the amplifier; a switching device for sequentially transmitting the output of the CDS circuit; and an amplifier for receiving an output of the switching device; wherein the CDS circuit comprises: a sample-and-hold-reset signal ( a SHR) switch for sampling the CA reset signal; An SHR capacitor coupled to the SHR switch for maintaining the CA reset signal; a sample-and-hold image signal (SHS) switch for sampling the image signal of the image sensor; and an SHS capacitor, coupled Connected to the SHS switch for maintaining the image signal; wherein the signal stored in the SHR capacitor is sequentially transmitted to one of the two differential inputs of the amplifier by the switching device, and the signal stored in the SHS capacitor is used by The switching device is sequentially transmitted to another differential input of the amplifier. The readout circuit of the image sensor of claim 9, wherein one of the capacitor plates is coupled to the row node, and the switch is coupled to the other electrode of the capacitor and the multiplexer input between. The readout circuit of the image sensor according to claim 9, wherein the multiplexer is used to add signals of the plurality of rows. The readout circuit of the image sensor according to claim 9, wherein the multiplexer allows only a single line of image signals to pass at each time. The readout circuit of the image sensor according to claim 9 further includes a feedback capacitor coupled between the output of the line amplifier and the input. The readout circuit of the image sensor according to claim 13 further includes a CA reset switch coupled between the output of the line amplifier and the input. The readout circuit of the image sensor according to claim 9, wherein the amplifier comprises a programmable gain amplifier (PGA).