TWI383349B - Reference voltage generating circuit, display panel and display apparatus - Google Patents

Description

Reference voltage generating circuit, display panel and display device

The present invention relates to a reference voltage generating circuit, a display panel, and a display device.

With the development of display technology, display devices and their products have been widely used.

Referring to FIG. 1 , a display device 1 includes a system voltage source 11 , a DC-DC converter 12 , a reference voltage generating circuit 13 , a driving circuit 14 , and a picture . Prime array 15.

The DC-DC power converter 12 converts the system voltage V1 _C (generally about 3.3V~5V) outputted by the system voltage source 11 into a boost voltage V1 _A (generally about 9V~13V), and provides them separately. The reference voltage generating circuit 13, the driving circuit 14, and other components of the display device 1 are used as power sources required for operation.

Referring to FIG. 1 and FIG. 2 simultaneously, the reference voltage generating circuit 13 has a plurality of resistors R1a to R1 _k which are sequentially connected in series to form a resistor string 131. The resistor string 131 generates a plurality of reference voltages V1 _{R a} VV1 _{R j} according to the boost voltage V1 _A to be output to the driving circuit 14. The driving circuit 14 receives an image data and drives the pixel array 15 to display a picture according to a reference voltage corresponding to the image data to generate a driving voltage V1 _D.

However, as the display screen is different, the driving voltage V1 _D generated by the driving circuit 14 is also different, causing the load corresponding to the DC-DC power converter 12 to be different, so that the boosting voltage V1 _{A is} easily carried. Noise. In addition, the process of converting the system voltage V1 _C to the boosted voltage V1 _A by the DC-DC power converter 12 also causes the boosted voltage V1 _{A to be} interspersed with noise, and the reference voltage V1 _R generated by the reference voltage generating circuit 13 is made. _a ~V1 _{R j is} unstable, causing problems such as crosstalk on the display screen, and lowering the display quality of the display device 1.

In order to solve the above problems, the industry has developed a reference voltage generating circuit having a voltage stabilizing function.

Referring to FIG. 3, the conventional reference voltage generating circuit 13' is different from the reference voltage generating circuit 13 (shown in FIG. 2), and the reference voltage generating circuit 13' further includes a shunt regulator 132' ( Shunt regulator) is electrically connected to one end E1 _{1 of the} resistor string 131, wherein the shunt regulator 132' is composed of at least one Zener diode Z ₁ and two resistors R _{Z 1} , R _{Z 2} composition to stabilize the voltage value of the one end of the resistor string 131 E1 _1, Bishi reference voltage generating circuit 13 'generated by the reference voltage V1 _{R a} ~ V1 _{R j} stable. The voltage value of one end E1 ₁ of the resistor string 131 can be changed by adjusting the resistance values of the resistors R _{Z 1} and R _{Z 2} .

However, since the size of the shunt regulator is proportional to 132 'about the electrical energy consumed by the boosted voltage V1 _A, and the magnitude of the boosted voltage V1 _A system based on the actual design decisions, and can not be arbitrarily changed, resulting in a display device 1 can not effectively reduce the loss of electrical energy.

Therefore, how to provide a reference voltage generating circuit, a display panel and a display device capable of effectively reducing power consumption is one of the important topics in the current display industry.

In view of the above problems, an object of the present invention is to provide a reference voltage generating circuit, a display panel, and a display device which can effectively reduce power consumption.

In order to achieve the above object, a reference voltage generating circuit according to the present invention is coupled to a first voltage generating circuit, wherein the first voltage generating circuit generates a first voltage, and the reference voltage generating circuit includes a current Mirror and a partial pressure unit. The first voltage generating circuit generates a first voltage; the current mirror is electrically connected to the first voltage generating circuit, and generates an input current and an output current according to the first voltage, wherein the output current and the input current have a fixed relationship Ratio; the voltage dividing unit is electrically connected to the current mirror, and generates a plurality of reference voltages according to the output current.

In addition, in order to achieve the above object, a display panel according to the present invention comprises a first voltage generating circuit, a second voltage generating circuit, a reference voltage generating circuit, a pixel array and a driving circuit. The first voltage generating circuit generates a first voltage; the second voltage generating circuit generates a second voltage; the reference voltage generating circuit has a current mirror and a voltage dividing unit. The current mirror system is electrically connected to the first voltage generating circuit, and generates an input current and an output current according to the first voltage, wherein the output current and the input current have a fixed ratio, the voltage dividing unit and the current mirror and the second The voltage generating circuit is electrically connected, and generates a plurality of reference voltages according to the output current and the second voltage; the driving circuit drives the pixel array according to an image data and the reference voltages.

Furthermore, in order to achieve the above object, a display device according to the present invention has a display panel, and the display panel includes a first voltage generating circuit, a second voltage generating circuit, a reference voltage generating circuit, and a pixel array. And a drive circuit. The first voltage generating circuit generates a first voltage; the second voltage generating circuit generates a second voltage; the reference voltage generating circuit has a current mirror and a voltage dividing unit. The current mirror system is electrically connected to the first voltage generating circuit, and generates an input current and an output current according to the first voltage, wherein the output current and the input current have a fixed ratio, the voltage dividing unit and the current mirror and the second The voltage generating circuit is electrically connected, and generates a plurality of reference voltages according to the output current and the second voltage; the driving circuit drives the pixel array according to an image data and the reference voltages.

According to the above, the reference voltage generating circuit, the display panel and the display device according to the present invention use a current mirror to provide an output current having a fixed ratio to the input current to the voltage dividing unit according to the input current to stabilize the voltage dividing unit. Voltage, and a reference voltage generating circuit having a shunt regulator in the prior art, the shunt regulator can not reduce the power consumption due to the magnitude of the boosted voltage, and the reference voltage generating circuit, the display panel and the present invention In the display device, the first voltage and the fixed ratio of an appropriate size can be designed to effectively reduce the power loss of the current mirror, thereby making the reference voltage generating circuit, the display panel and the display device of the present invention more power-saving.

In addition, since the current mirror is cheaper than the shunt regulator, the cost of the reference voltage generating circuit of the present invention can be lower than that of the reference voltage generating circuit having the shunt regulator, thereby reducing the reference voltage generating circuit and the display of the present invention. The cost of panels and display devices.

Hereinafter, a reference voltage generating circuit, a display panel, and a display device according to a preferred embodiment of the present invention will be described with reference to the related drawings.

[Reference voltage generating circuit of the first preferred embodiment]

Referring to FIG. 4, the reference voltage generating circuit 21 of the first preferred embodiment of the present invention is exemplified by a gamma reference voltage generating circuit. The reference voltage generating circuit 21 is coupled to a first voltage generating circuit 22 and a second voltage generating circuit 23. The first voltage generating circuit 22 generates a first voltage V2 _C , and the second voltage generating circuit 23 generates a second voltage V2 _A . The reference voltage generating circuit 21 includes a current mirror 211 and a voltage dividing unit 212.

The current mirror 211 is electrically connected to the first voltage generating circuit 22, and generates an input current I2 _I and an output current I2 _O according to the first voltage V2 _C . There is a fixed ratio between the output current I2 _O and the input current I2 _I.

The voltage dividing unit 212 has a plurality of resistors R2 _a to R2 _k which are connected in series with each other. Among them, the number of resistors R2 _a to R2 _k may vary according to actual conditions. One end E2 ₁ of the voltage dividing unit 212 is electrically connected to the second voltage generating circuit 23, and the other end E2 ₂ of the voltage dividing unit 212 is electrically connected to the current mirror 211 according to the output current I2 _O and the second voltage V2 _A. A plurality of reference voltages V2 _{R a} ~V2 _{R j are} generated. The voltage difference between the reference voltages V2 _{R a} ~V2 _{R j} is related to the magnitude of the output current I2 _O , and the voltage levels of the reference voltages V2 _{R a} ~V2 _{R j} and the second voltage V2 _A related.

In this embodiment, the current mirror 211 has a first transistor Q _{2 1} and a second transistor Q _{2 2} . Wherein the first gate transistor Q ₂₁ of the pole ₂₁ G, a first transistor Q D Drain electrode ₂₁ of the transistor ₂₁ and the second shutter ₂₂ is extremely Q G ₂₂ is electrically connected to the first system voltage generating circuit 22, a first source transistor Q _{2 1 2 1} and S-pole of the second source transistor Q _{2 2 2 2} S-pole of the system is grounded, and the drain of the second transistor Q _{2 2} D _{2 2} based extreme The other end E2 _{2 of the} voltage dividing unit 212 is electrically connected to cause the output current I2 _{O to} flow through the voltage dividing unit 212 and the second transistor Q _{2 2} . Further, the fixed ratio is associated with the channel area width to length ratio of the first transistor Q _{2 1 and} the channel area width to length ratio of the second transistor Q _{2 2} . In this embodiment, the first transistor Q _{2 1} and the second transistor Q _{2 2} are an N-type metal oxide semi-transistor (NMOS).

As the current mirror 211 has the first transistor Q _{2 1} and the second transistor Q _{2 2} , it is cheaper than the shunt regulator 132 ′ (shown in FIG. 3 ), so the cost of the reference voltage generating circuit 21 can be compared. It is known that the reference voltage generating circuit 13' (shown in FIG. 3) having the shunt regulator 132' is inexpensive.

Further, since the reference voltage generating circuit 21 line by the current mirror 211 is generated according to the input current I2 _I the input current I2 _I having an output fixed ratio of currents I2 _O to dividing unit 212 to the respective reference voltage V2 _{R a} ~ V2 _{R j} The voltage difference between them is fixed, thereby stabilizing the reference voltage V2 _{R a} ~V2 _{R j} outputted by the voltage dividing unit 212. In addition, the operator can design a first voltage V2 _{C of} appropriate size and a fixed ratio to effectively reduce the power lost by the current mirror 211. In this embodiment, the voltage value of the first voltage V2 _C is less than the voltage value of the second voltage V2 _A. For example, the voltage value of the first voltage V2 _C is less than but not limited to 2.5 volts, and the voltage value of the second voltage V2 _A is approximately, but not limited to, between 9 volts and 13 volts. At this time, compared with the reference voltage generating circuit 13' (shown in FIG. 3) having the shunt regulator 132', the energy consumption ratio of the current mirror 211 to the shunt regulator 132' is about the first. The voltage value of the voltage V2 _C (below 2.5 volts) relative to the voltage of the boost voltage V1 _A (9 volts to 13 volts). In other words, the reference voltage generating circuit 21 saves power compared to the reference voltage generating circuit 13'.

Furthermore, the operator can appropriately select the channel area width to length ratio of the specific first transistor Q _{2 1 and} the channel area width to length ratio of the specific second transistor Q _{2 2} , so that the input current I2 _{I is} as small as possible as the output current. I2 _O to reduce the power lost by the current mirror 211. Of course, the operator can also connect other transistors in the second transistor Q _{2 2} to reduce the input current I2 _I to reduce the power loss of the current mirror 211.

For example, referring to FIG. 5, the current mirror 211' further has a third transistor Q _{2 3} . In the embodiment, the third transistor Q _{2 3} is an N-type MOS transistor. A third gate transistor Q ₂₃ of the pole line and the gate G ₂₃ of the first transistor Q ₂₁ of the electrode G _{2 1,} the first transistor Q D Drain electrode ₂₁ of the transistor ₂₁ and the second Q _{2 2} the gate G _{2 2} electrically connected to the drain of the third transistor Q ₂₃ D ₂₃ of the pole system and the second transistor Q _{2 2} Drain electrically connected to the D _{2 2.} The fixed ratio is related to the channel area width to length ratio of the first transistor Q _{2 1 ,} the channel area width to length ratio of the second transistor Q _{2 2, and} the channel area width to length ratio of the third transistor Q _{2 3} . At this time, the operator can design the appropriate channel area width to length ratio of the third transistor Q _{2 3} to change the fixed ratio between the output current I2' _O and the input current I2' _I , thereby reducing the input current I2' _I to reduce the current. The electrical energy lost by the mirror 211'.

In addition, it is worth mentioning that the first voltage generating circuit 22 can include a voltage source (for example, a system voltage source) and a voltage stabilizing circuit. The voltage source generates an original first voltage and outputs the original first voltage to the voltage stabilizing circuit, and then the voltage stabilizing circuit outputs a first voltage V2 _C according to the original first voltage, wherein the original first voltage and the voltage of the first voltage V2 _C Values can be the same or different. Of course, the first voltage generating circuit 22 may also include only one voltage source (for example, a system voltage source).

Similarly, the second voltage generating circuit 23 can include a voltage source (such as a system voltage source) and a DC-DC power converter. The voltage source generates an original second voltage and outputs the original second voltage to the DC-DC power converter, and then the DC-DC power converter boosts the original second voltage to the second voltage V2 _A , of course, the second voltage generating circuit 23 may also contain only one voltage source.

According to the above description, the reference voltage generating circuit according to the present invention uses a current mirror to provide an output current having a fixed ratio to the input current to the voltage dividing unit according to the input current to stabilize the voltage of the voltage dividing unit, which is connected in parallel with the conventional one. In the reference voltage generating circuit of the voltage regulator, the shunt regulator can not reduce the power consumption due to the influence of the magnitude of the boosting voltage. In the reference voltage generating circuit of the present invention, the first voltage and the fixed size can be designed. The ratio is used to effectively reduce the power loss of the current mirror, thereby making the reference voltage generating circuit of the present invention more power efficient.

In addition, since the current mirror is cheaper than the shunt regulator, the cost of the reference voltage generating circuit of the present invention can be lower than that of the reference voltage generating circuit having the shunt regulator.

[Reference voltage generating circuit of the second preferred embodiment]

Referring to FIG. 6, the reference voltage generating circuit 31 of the second preferred embodiment of the present invention cooperates with a first voltage generating circuit 32 and a second voltage generating circuit 33. The first voltage generating circuit 32 generates a first voltage V3 _C , and the second voltage generating circuit 33 generates a second voltage V3 _A . The reference voltage generating circuit 31 includes a current mirror 311 and a voltage dividing unit 312.

The current mirror 311 is electrically connected to the first voltage generating circuit 32, and generates an input current I3 _I and an output current I3 _O according to the first voltage V3 _C , wherein the output current I3 _O and the input current I3 _I have a fixed relationship. ratio.

The voltage dividing unit 312 has a plurality of resistors R3 _a to R3 _k which are connected in series with each other. The voltage dividing unit 312 is electrically connected to the second voltage generating circuit 33, and the voltage dividing unit 312 is electrically connected to the current mirror 311 to generate a plurality of reference voltages V3 _{R a} according to the output current I3 _O and the second voltage V3 _A. V3 _{R j} . Wherein, the voltage difference between each reference voltage V3 _{R a} ~V3 _{R j} is related to the magnitude of the output current I3 _O , and the voltage level of each reference voltage V3 _{R a} ~V3 _{R j} is related to the second voltage V3 _A .

In this embodiment, the current mirror 311 has a first transistor Q _{3 1} , a second transistor Q _{3 2} , a third transistor Q _{3 3} and a fourth transistor Q _{3 4} . Wherein the first transistor Q ₃₁ of the gate electrode ₃₁ G, a first transistor Q D Drain electrode ₃₁ of the transistor ₃₁ and the second shutter ₃₂ is extremely Q G ₃₂ is electrically connected to the first system voltage generation circuit 32; a first source transistor Q _{31 31} S-pole of the second source transistor Q _{32 32} S-pole of the ground lines; second transistor Q drain electrode D of ₃₂ lines and ₃₂ the third transistor Q ₃₃ of the gate electrode G _{3 3,} the drain of the third transistor Q _{3 3 3 3} D extremely transistor Q and the fourth gate G ₃₄ of the pole ₃₄ is electrically connected; third transistor Q the source electrode ₃₃ S ₃₃ Q source and a fourth transistor ₃₄ of the S-pole line ₃₄ is electrically connected to the second voltage generation circuit 33; a fourth transistor Q drain electrode D of ₃₄ lines and ₃₄ minutes One end E3 _{1 of the} pressing unit 312 is electrically connected, so that the output current I3 _O flows through the voltage dividing unit 312 and the fourth transistor Q _{3 4} . Wherein, the fixed ratio is the aspect ratio of the channel region of the first transistor Q _{3 1 ,} the aspect ratio of the channel region of the second transistor Q _{3 2 ,} the aspect ratio of the channel region of the third transistor Q _{3 3} , and the fourth The channel area width to length ratio of the transistor Q _{3 4} is related. In this embodiment, the first transistor Q _{3 1} and the second transistor Q _{3 2} are N-type MOS transistors, and the third transistor Q _{3 3} and the fourth transistor Q _{3 4} are P. Type MOS semi-transistor (PMOS).

The reference voltage generating circuit 31 uses the current mirror 311 to provide an output current I3 _O having a fixed ratio with the input current I3 _I to the voltage dividing unit 312 according to the input current I3 _I so that the reference voltages V3 _{R a} to V3 _R The voltage difference between _j is fixed and the voltage level of each reference voltage V3 _{R a} ~V3 _{R j} , thereby stabilizing the reference voltage V3 _{R a} ~V3 _{R j} outputted by the voltage dividing unit 312.

[Display panel of preferred embodiment]

Referring to FIG. 7 , the display panel 4 includes a reference voltage generating circuit 41 , a first voltage generating circuit 42 , a second voltage generating circuit 43 , a driving circuit 44 , and a pixel array 45 .

The first voltage generating circuit 42 generates a first voltage V4 _C , and the second voltage generating circuit 43 generates a second voltage V4 _A . The reference voltage generating circuit 41 has a current mirror 411 and a voltage dividing unit 412.

The current mirror 411 is electrically connected to the first voltage generating circuit 42 and generates an input current I4 _I and an output current I4 _O according to the first voltage V4 _C , wherein the output current I4 _O and the input current I4 _I have a fixed relationship. The voltage dividing unit 412 is electrically connected to the current mirror 411 and the second voltage generating circuit 43 and generates a plurality of reference voltages V4 _{R a} to V4 _{R j} according to the output current I4 _O to be supplied to the driving circuit 44. The driving circuit 44 The pixel array 45 is driven according to an image data and a reference voltage.

The reference voltage generating circuit 41, the first voltage generating circuit 42 and the second voltage generating circuit 43 of the present embodiment are the reference voltage generating circuit 21, the first voltage generating circuit 22 and the second voltage generating circuit in the first preferred embodiment. 23 and the reference voltage generating circuit 31, the first voltage generating circuit 32, and the second voltage generating circuit 33 (shown in FIGS. 4 to 6) of the second preferred embodiment are not described in detail herein.

According to the above description, the display panel according to the present invention uses a current mirror to provide an output current having a fixed ratio to the input current to the voltage dividing unit according to the input current to stabilize the voltage of the voltage dividing unit, and has a shunt regulator. In the reference voltage generating circuit, the shunt regulator cannot be reduced in power consumption due to the magnitude of the boosted voltage. In the display panel of the present invention, the first voltage and the fixed ratio of an appropriate size can be designed to effectively reduce The power loss of the current mirror further makes the reference voltage generating circuit, the display panel and the display device of the present invention more power-saving.

In addition, since the current mirror is cheaper than the shunt regulator, the cost of the reference voltage generating circuit of the present invention can be lower than that of the reference voltage generating circuit having the shunt regulator, and the cost of the display panel of the present invention can be reduced.

[Display device of preferred embodiment]

Referring to FIG. 8, the display device DA can be a plasma display device, a field emission display device, a liquid crystal display device, or an organic light emitting diode display device. In the embodiment, the display device DA is exemplified by a liquid crystal display device, and includes a display panel 4 and a backlight module 5. The display panel 4 is detailed in the display panel (shown in FIG. 7) of the preferred embodiment, and details are not described herein.

In addition, the backlight module 5 provides a backlight to the display panel 4.

In summary, the reference voltage generating circuit, the display panel and the display device according to the present invention use a current mirror to provide an output current having a fixed ratio to the input current to the voltage dividing unit according to the input current to stabilize the voltage dividing unit. Voltage, and a reference voltage generating circuit having a shunt regulator in the prior art, the shunt regulator can not reduce the power consumption due to the magnitude of the boosted voltage, and the reference voltage generating circuit, the display panel and the present invention In the display device, the first voltage and the fixed ratio of an appropriate size can be designed to effectively reduce the power loss of the current mirror, thereby making the reference voltage generating circuit, the display panel and the display device of the present invention more power-saving.

In addition, since the current mirror is cheaper than the shunt regulator, the cost of the reference voltage generating circuit of the present invention can be lower than that of the reference voltage generating circuit having the shunt regulator, thereby reducing the reference voltage generating circuit and the display of the present invention. The cost of panels and display devices.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1. . . Display device

11. . . System voltage source

12. . . DC-DC power converter

13. . . Reference voltage generating circuit

13’. . . Reference voltage generating circuit

131. . . Resistor string

132’. . . Shunt regulator

14. . . Drive circuit

15. . . Pixel array

twenty one. . . Reference voltage generating circuit

211, 211’. . . Current mirror

212. . . Partition unit

twenty two. . . First voltage generating circuit

twenty three. . . Second voltage generating circuit

31. . . Reference voltage generating circuit

311. . . Current mirror

312. . . Partition unit

32. . . First voltage generating circuit

33. . . Second voltage generating circuit

4. . . Display panel

41. . . Reference voltage generating circuit

411. . . Current mirror

412. . . Partition unit

42. . . First voltage generating circuit

43. . . Second voltage generating circuit

44. . . Drive circuit

45. . . Pixel array

5. . . Backlight module

D _{2 1} , D _{2 2} , D _{2 3} . . . Bungee

D _{3 1} , D _{3 2} , D _{3 3} , D _{3 4} . . . Bungee

DA. . . Display device

E1 ₁ , E2 ₁ , E3 ₁ . . . One end

E2 ₂ . . . another side

G _{2 1} , G _{2 2} , G _{2 3} . . . Gate

G _{3 1} , G _{3 2} , G _{3 3} , G _{3 4} . . . Gate

I2 _I , I2' _I , I3 _I , I4 _I . . . Input Current

I2 _O , I2' _O , I3 _O , I4 _O . . . Output current

R1 _a ~R1 _k . . . Resistor

R2 _a ~ R2 _k . . . Resistor

R3 _a ~R3 _k . . . Resistor

R _{Z 1} , R _{Z 2} . . . Resistor

V1 _C . . . System voltage

V1 _D. . . Driving voltage

V1 _A . . . Boost voltage

V2 _C , V3 _C , V4 _C . . . First voltage

V2 _A , V3 _A , V4 _A . . . Second voltage

V1 _{R a} ~V1 _{R j} . . . Reference voltage

V2 _{R a} ~V2 _{R j} . . . Reference voltage

V3 _{R a} ~V3 _{R j} . . . Reference voltage

V4 _{R a} ~V4 _{R j} . . . Reference voltage

S _{2 1} , S _{2 2} , S _{2 3} . . . Source

S _{3 1} , S _{3 2} , S _{3 3} , S _{3 4} . . . Source

Q _{2 1} , Q _{3 1} . . . First transistor

Q _{2 2} , Q _{3 2} . . . Second transistor

Q _{2 3} , Q _{3 3} . . . Third transistor

Q _{3 4} . . . Fourth transistor

Z ₁ . . . Jenus diode

1 is a block diagram showing a conventional display device; FIG. 2 is a circuit diagram showing the reference voltage generating circuit of FIG. 1; and FIG. 3 is another circuit diagram showing a reference voltage having a shunt regulator. FIG. 4 is a circuit diagram showing a reference voltage generating circuit according to a first preferred embodiment of the present invention; and FIG. 5 is another circuit diagram showing a reference voltage generating circuit according to a first preferred embodiment of the present invention; Figure 6 is another circuit diagram showing a reference voltage generating circuit of a second preferred embodiment of the present invention; Figure 7 is a block diagram showing a display panel in accordance with a preferred embodiment of the present invention; and Figure 8 is a block Figure shows a display device in accordance with a preferred embodiment of the present invention.

twenty one. . . Reference voltage generating circuit

211. . . Current mirror

212. . . Partition unit

twenty two. . . First voltage generating circuit

twenty three. . . Second voltage generating circuit

D _{2 1} , D _{2 2} . . . Bungee

E2 ₁ . . . One end

E2 ₂ . . . another side

G _{2 1} , G _{2 2} . . . Gate

I2 _I . . . Input Current

I2 _O . . . Output current

R2 _a ~ R2 _k . . . Resistor

V2 _C . . . First voltage

V2 _A . . . Second voltage

V2 _{R a} ~V2 _{R j} . . . Reference voltage

S _{2 1} , S _{2 2} . . . Source

Q _{2 1} . . . First transistor

Q _{2 2} . . . Second transistor

Claims (37)

A reference voltage generating circuit is coupled to a first voltage generating circuit, wherein the first voltage generating circuit generates a first voltage, and the reference voltage generating circuit comprises: a current mirror coupled to the first voltage Generating a circuit electrical connection, and generating an input current and an output current according to the first voltage, wherein the output current has a fixed ratio with the input current; and a voltage dividing unit is electrically connected to the current mirror And generating a plurality of reference voltages according to the output current. The reference voltage generating circuit of claim 1, wherein the voltage dividing unit has a plurality of resistors connected in series with each other. The reference voltage generating circuit of claim 1, wherein the current mirror has at least a first transistor and a second transistor, and the gate of the first transistor and the first transistor The pole is electrically connected to the gate of the second transistor. The reference voltage generating circuit of claim 3, wherein the gate of the first transistor, the drain of the first transistor, and the gate of the second transistor are electrically connected to the first a voltage generating circuit, the drain of the second transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the second transistor. The reference voltage generating circuit of claim 3, wherein the fixed ratio is related to a channel area width to length ratio of the first transistor and a channel area width to length ratio of the second transistor. The reference voltage generating circuit of claim 3, wherein the current mirror further has a third transistor, a gate of the third transistor and a gate of the first transistor, the first The drain of the crystal and the gate of the second transistor are electrically connected, and the drain of the third transistor is electrically connected to the drain of the second transistor. The reference voltage generating circuit of claim 6, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and the third transistor The width and length of the channel area are related. The reference voltage generating circuit of claim 3, wherein the current mirror further has a third transistor and a fourth transistor, wherein the gates are electrically connected to each other, and the third transistor has a drain The gate of the second transistor and the gate of the third transistor are electrically connected to each other, and the source of the third transistor and the source of the fourth transistor are electrically connected to the second voltage And generating a circuit, the drain of the fourth transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the fourth transistor. The reference voltage generating circuit of claim 8, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and the third transistor The channel area width to length ratio is associated with the channel area width to length ratio of the fourth transistor. The reference voltage generating circuit of claim 1 is further configured to cooperate with a second voltage generating circuit, wherein the second voltage generating circuit generates a second voltage and is electrically connected to the voltage dividing unit. The voltage dividing unit generates the reference voltages according to the second voltage and the output current. The reference voltage generating circuit of claim 10, wherein the voltage value of the first voltage is less than the voltage value of the second voltage. The reference voltage generating circuit of claim 1, wherein the voltage value of the first voltage is substantially less than 2.5 volts. A reference voltage generating circuit as described in claim 1 is a Gamma reference voltage generating circuit. A display panel includes: a first voltage generating circuit that generates a first voltage; a second voltage generating circuit that generates a second voltage; and a reference voltage generating circuit that has: a current mirror, The system is electrically connected to the first voltage generating circuit, and generates an input current and an output current according to the first voltage, wherein the output current has a fixed ratio with the input current, and a voltage dividing unit is Electrically connecting with the current mirror and the second voltage generating circuit, and generating a plurality of reference voltages according to the output current and the second voltage; a pixel array; and a driving circuit based on an image data and the The reference voltage is used to drive the pixel array. The display panel of claim 14, wherein the voltage dividing unit has a plurality of resistors connected in series with each other. The display panel of claim 14, wherein the current mirror has at least a first transistor and a second transistor, and the gate of the first transistor and the first transistor of the first transistor The gate of the second transistor is electrically connected. The display panel of claim 16, wherein the gate of the first transistor, the drain of the first transistor, and the gate of the second transistor are electrically connected to the first voltage generating The circuit, the drain of the second transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the second transistor. The display panel of claim 16, wherein the fixed ratio is related to a channel area width to length ratio of the first transistor and a channel area width to length ratio of the second transistor. The display panel of claim 16, wherein the current mirror further has a third transistor, a gate of the third transistor and a gate of the first transistor, and the first transistor The gate of the second transistor is electrically connected to the gate of the second transistor, and the drain of the third transistor is electrically connected to the drain of the second transistor. The display panel of claim 19, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and a channel of the third transistor. The area width to length ratio is related. The display panel of claim 16, wherein the current mirror further has a third transistor and a fourth transistor, wherein the gates are electrically connected to each other, and the third transistor has a drain The gate of the second transistor and the gate of the third transistor are electrically connected to each other, and the source of the third transistor and the source of the fourth transistor are electrically connected to the second voltage generating circuit The drain of the fourth transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the fourth transistor. The display panel of claim 21, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and a channel of the third transistor. The area width to length ratio is related to the width to length ratio of the channel region of the fourth transistor. The display panel of claim 14, wherein the voltage value of the first voltage is less than the voltage value of the second voltage. The display panel of claim 14, wherein the voltage value of the first voltage is substantially less than 2.5 volts. The display panel of claim 14, wherein the reference voltage generating circuit is a gamma reference voltage generating circuit. A display device includes a display panel, the display panel includes: a first voltage generating circuit that generates a first voltage; a second voltage generating circuit that generates a second voltage; a reference voltage generated The circuit has a current mirror electrically connected to the first voltage generating circuit, and generates an input current and an output current according to the first voltage, wherein the output current and the input current have a a fixed ratio, and a voltage dividing unit electrically connected to the current mirror and the second voltage generating circuit, and generating a plurality of reference voltages according to the output current and the second voltage; a pixel array; and a driving circuit And driving the pixel array according to an image data and the reference voltages. The display device of claim 26, wherein the voltage dividing unit has a plurality of resistors connected in series with each other. The display device of claim 26, wherein the current mirror has at least a first transistor and a second transistor, the gate of the first transistor and the first transistor of the first transistor The gate of the second transistor is electrically connected. The display device of claim 28, wherein the gate of the first transistor, the drain of the first transistor, and the gate of the second transistor are electrically connected to the first voltage generating The circuit, the drain of the second transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the second transistor. The display device of claim 28, wherein the fixed ratio is related to a channel length to length ratio of the first transistor and a channel area width to length ratio of the second transistor. The display device of claim 28, wherein the current mirror further has a third transistor, a gate of the third transistor and a gate of the first transistor, the first transistor The gate of the second transistor is electrically connected to the gate of the second transistor, and the drain of the third transistor is electrically connected to the drain of the second transistor. The display device of claim 31, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and a channel of the third transistor. The area width to length ratio is related. The display device of claim 28, wherein the current mirror further has a third transistor and a fourth transistor, wherein the gates are electrically connected to each other, and the third transistor has a drain The gate of the second transistor and the gate of the third transistor are electrically connected to each other, and the source of the third transistor and the source of the fourth transistor are electrically connected to the second voltage generating circuit The drain of the fourth transistor is electrically connected to the voltage dividing unit, and the output current flows through the voltage dividing unit and the fourth transistor. The display device of claim 33, wherein the fixed ratio is a width to length ratio of a channel region of the first transistor, a channel length to length ratio of the second transistor, and a channel of the third transistor. The area width to length ratio is related to the width to length ratio of the channel region of the fourth transistor. The display device of claim 26, wherein the voltage value of the first voltage is less than the voltage value of the second voltage. The display device of claim 26, wherein the voltage value of the first voltage is substantially less than 2.5 volts. The display device of claim 26, wherein the reference voltage generating circuit is a gamma reference voltage generating circuit.