TWI381437B - Method for surface modification of semiconductor layer and method of manufacturing semiconductor device - Google Patents

Description

Surface treatment method of semiconductor layer and method of manufacturing semiconductor device

The present invention relates to a surface treatment method for a semiconductor layer and a method of fabricating the same, and more particularly to a surface treatment method for removing a plurality of fine particles on a surface of a semiconductor layer and a method of manufacturing the semiconductor device.

With the rapid development of the semiconductor industry and the advancement of technology, various electronic devices using semiconductor technology are immersed in the daily life of modern people, such as personal computers, digital cameras, and mobile phones, among which many applications are applied. Applications of semiconductor technology, such as liquid crystal display panels, memory or sense wafers, and the like. The advancement of semiconductor technology has become one of the important driving forces for the development of science and technology.

In general, a basic application commonly used in semiconductor devices is a MOS transistor, which is made up of three layers of a metal layer, an oxide layer, and a semiconductor layer. The thickness is stacked in sequence. A common semiconductor layer material is tantalum, and a common oxide layer material is cerium oxide (SiO ₂ ), in which the effect of insulating is achieved by utilizing the high dielectric constant property of the oxide layer. In addition, the metal layer is generally made of a poly-silicon material to serve as an electrode layer of the transistor, and a doping technique is used to incorporate a dopant into the polysilicon material to increase its conductivity. In the process of a semiconductor device, when an impurity is to be doped into a polycrystalline germanium material, for example, an in-situ doped poly silicon layer can be used. The impurities are driven into the polycrystalline germanium material of the electrode layer by the high-temperature diffusion doping method to achieve the purpose of doping.

However, when the above-mentioned synchronously doped polysilicon layer is deposited, the surface thereof may cause precipitation of particles due to light, heat or other factors. Please also refer to FIG. 1A to FIG. 1D. FIG. 1A is a schematic view showing the distribution of particles after depositing the synchronous doped polysilicon layer for 4 hours; FIG. 1B is a schematic view showing the distribution of particles after 8 hours of depositing the synchronous doped polysilicon layer; A schematic diagram showing the distribution of particles after deposition of the synchronous doped polysilicon layer for 24 hours is shown; FIG. 1D is a schematic diagram showing the distribution of particles after 48 hours of deposition of the synchronous doped polysilicon layer. As can be seen from Figures 1A to 1D, the number of particles 111 increases with time. Since the particles 111 cause the surface quality of the synchronous doped polysilicon layer 110 to decrease, the electrical properties of the polycrystalline germanium material are deteriorated, the chance of random single-bit error is increased, and the operation of the MOS transistor is further reduced. Quality and reliability. Furthermore, the yield of MOS transistors will also be affected, which will increase production costs relatively.

The present invention relates to a surface treatment method for a semiconductor layer and a method of manufacturing a semiconductor device which removes particles deposited on the surface of a semiconductor layer by a cleaning method and maintains the surface of the semiconductor layer in a clean state for a certain period of time. The surface treatment method of the semiconductor layer and the method of manufacturing the semiconductor device of the present invention have the advantages of improving product yield, reducing cost, improving product reliability, and simple method.

According to an aspect of the invention, a surface treatment method of a semiconductor layer is proposed. First, a semiconductor layer is provided, the surface of which has a plurality of particles. Second, the particles are removed using a cleaning method. This cleaning method first contacts the semiconductor layer with an organic remover. The semiconductor layer is then contacted with a first peroxide mixture. Then, the semiconductor layer is brought into contact with a second peroxide mixture.

According to another aspect of the present invention, a method of fabricating a semiconductor device is provided. First, a substrate is provided. Then, an insulating layer is sequentially formed on the substrate to form a semiconductor layer on the insulating layer, and the surface of the semiconductor layer has a plurality of particles. Second, the particles are removed using a cleaning method. In this cleaning method, the semiconductor layer is sequentially contacted with an organic remover, a first peroxide mixture, and a second peroxide mixture.

In order to make the above-mentioned contents of the present invention more comprehensible, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

A preferred embodiment is presented below as a detailed description of the invention. This example is intended to be illustrative, and is not intended to limit the scope of the invention. In addition, the illustration in the embodiments also omits unnecessary elements to clearly show the technical features of the present invention.

2 and 3A-3F, FIG. 2 is a flow chart of a method for fabricating a semiconductor device according to a preferred embodiment of the present invention; FIG. 3A is a diagram showing a substrate and an insulating layer according to a preferred embodiment of the present invention. And a schematic view of the semiconductor substrate layer; FIG. 3B is a schematic view showing the surface of the semiconductor substrate layer formed on the third substrate; FIG. 3C is a schematic view showing the diffusion of impurities into the semiconductor substrate layer of FIG. FIG. 3D is a schematic view showing the semiconductor layer of FIG. 3C after being cleaned; FIG. 3E is a schematic view showing the substrate of FIG. 3D after being doped; FIG. 3F is a schematic view showing the pattern of the insulating layer of FIG. schematic diagram.

In accordance with a method of fabricating a semiconductor device in accordance with a preferred embodiment of the present invention, first, as shown in step 101, a substrate 10 is provided. Next, in step 102, an insulating layer 30 is formed to cover the substrate 10.

Then, as shown in step 103, a semiconductor layer is formed on the insulating layer 30. The semiconductor layer is formed by, for example, depositing a semiconductor substrate layer 41 on the insulating layer 30, and the semiconductor substrate layer 41 covers only a portion of the insulating layer 30, as shown in FIG. 3A. Next, a doped layer 42 is formed to cover the surface of the semiconductor substrate layer 41 as shown in FIG. 3B. In the present embodiment, the doping layer 42 is, for example, an in-situ doped polysilicon layer, and includes a high concentration of one of the dopants 52. After the doping layer 42 is formed, the method of forming the semiconductor layer is followed by the step of further doping 52, as shown in FIG. 3C. In the present embodiment, the impurity 52 is, for example, entered into the semiconductor substrate layer 41 by the high temperature diffusion doping of the doped layer 42. After the doping step is completed, the semiconductor substrate layer 41 and the doped layer 42 are entirely formed into the semiconductor layer 40.

After the semiconductor layer 40 is formed, its surface gradually precipitates a plurality of particles 51 over time. The manufacturing method of this embodiment is followed by the step of removing the particles 51. As shown in step 104 of Fig. 2, the surface treatment of the semiconductor layer 40 is performed by a cleaning method for removing the particles 51 as shown in Fig. 3D. First, the organic contaminant on the surface of the semiconductor layer 40 can be removed by using an organic material removing agent composed of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ) to reduce the hydrophobicity of the surface of the semiconductor layer 40 and increase the connection. The efficiency of the cleaning step down. Next, the semiconductor layer 40 can be selectively contacted with an oxide remover to improve surface quality by removing oxides on the surface of the semiconductor layer 40. The oxide remover includes, for example, a deionized aqueous solution of hydrogen fluoride. Next, the semiconductor layer 40 is sequentially contacted with a first peroxide mixture and a second peroxide mixture. In this embodiment, the first peroxide mixture comprises ammonia water (NH ₄ OH), hydrogen peroxide and de-ionized water, and the second peroxide mixture comprises hydrochloric acid (HCl), hydrogen peroxide and deionized water. . A portion of the semiconductor layer 40 is oxidized by hydrogen peroxide, and the partially oxidized semiconductor layer 40 is removed by aqueous ammonia, whereby the particles 51 are removed from the surface of the semiconductor layer 40. Hydrochloric acid removes the alkali metal ions on the surface of the semiconductor layer 40 to further improve the surface quality of the semiconductor layer 40. Next, the surface of the semiconductor layer 40 can be washed with water. After the cleaning step, the particles 51 on the surface of the semiconductor layer 40 are removed, at which time the semiconductor layer 40 is in a clean state, and the cleaning state is maintained for at least about 12 hours. This ensures that the surface of the semiconductor layer 40 is free of such particles 51 in the subsequent process step.

After cleaning the surface of the semiconductor layer 40, the manufacturing method according to the preferred embodiment of the present invention then infiltrates another impurity on both sides of the corresponding semiconductor layer 40 of the substrate 10 to form a source, as shown in steps 105 and 3E. Zone 11 and bungee zone 12. The substrate 10 and the semiconductor layer 40 are preferably doped with the same type. In the present embodiment, the material of the insulating layer 30 is, for example, cerium oxide (SiO ₂ ), and the method of doping the substrate 10 can be performed by, for example, ion implantation and using the insulating layer 30 as a buffer layer. In the manner, impurities are incorporated into the substrate 10.

Then, step 106 is performed to pattern the insulating layer 30. The patterned insulating layer 30' is substantially the same width as the semiconductor 40, as shown in Fig. 3F. After the above-described patterning step is completed, the semiconductor device 100 in accordance with a preferred embodiment of the present invention is completed. In the present embodiment, the semiconductor device 100 is exemplified by a MOS transistor, and the semiconductor layer 40 is used as a gate electrode of the semiconductor device 100. In the present embodiment, the semiconductor layer 40 is, for example, a doped polysilicon layer, and the semiconductor layer may be only a polysilicon layer. The rest of the materials used in the technical field to which the present invention pertains, such as ruthenium, iridium or a combination thereof, can be applied thereto. The material of the insulating layer 30' is preferably cerium oxide for use as a gate oxide layer of the semiconductor device 100.

Please refer to FIG. 4A and FIG. 4B simultaneously. FIG. 4A is a schematic view showing the distribution of surface particles after one week of formation of the semiconductor layer; FIG. 4B is a schematic view showing the distribution of particles on the surface of the semiconductor layer after the surface treatment method of the embodiment is applied. In this embodiment, the surface of the semiconductor layer 40 is cleaned using an organic remover, a first peroxide mixture, and a second peroxide mixture. After a period of one week after the formation of the semiconductor layer 40, the number of particles 51 on the surface of the semiconductor layer 40 is detected by the detecting machine, and the particles 51 are already covered on the surface of the semiconductor layer 40 in a capacity detectable by the detecting machine. As shown in the circular area in Figure 4A. Next, referring to FIG. 4B, after applying the surface treatment method according to the preferred embodiment of the present invention, the number of particles 51 on the surface of the semiconductor layer 40 is greatly reduced.

On the other hand, the effect of the surface treatment method according to the preferred embodiment of the present invention can be understood by the number of particles 51 at different times. Please refer to Figure 5, which shows the relationship between the number of particles and time. The detection point A indicates the number of the fine particles 51 after the formation of the semiconductor layer 40; the detection point B indicates the number of the particles 51 which have passed 12 hours after the formation of the semiconductor layer 40; and the detection point C indicates that after the semiconductor layer 40 is cleaned according to the surface treatment method of the present embodiment, The number of particles 51 on the surface; the detection point D, the detection point E, and the detection point F indicate the number of particles 51 which have passed 12 hours, 24 hours, and 36 hours after cleaning, respectively. As shown in Fig. 5, after the semiconductor layer 40 is cleaned according to the surface treatment method of this embodiment, the number of the particles 51 is greatly reduced, and after another 12 hours (detection point D), the number of the particles 51 is again turned upward. rising. That is, the surface treatment method of the semiconductor layer according to the preferred embodiment of the present invention can greatly reduce the number of particles 51 on the surface of the semiconductor layer 40, and can maintain a clean state for at least about 12 hours. Therefore, when the semiconductor device performs the subsequent process steps, the surface of the semiconductor layer 40 is cleaned, and the problem of deterioration in yield and quality of the semiconductor device due to the formation of the surface particles 51 is avoided.

The surface treatment method of the semiconductor layer and the method for fabricating the semiconductor device according to the preferred embodiment of the present invention are the process of using the organic substance removing agent, the first peroxide mixed solution and the second peroxide mixed solution in the semiconductor device The surface of the semiconductor layer is cleaned, which has the advantages of simple method and obvious effect. Regardless of the manner in which the semiconductor layer is formed, the surface treatment method according to the present embodiment can effectively remove particles deposited on the surface of the semiconductor layer. Therefore, when the semiconductor device performs a subsequent process step, for example, when a deuterated metal layer or a metallization process is formed, good electrical performance can be maintained. That is to say, the surface treatment method of the preferred embodiment of the present invention can effectively avoid the problem that the quality of the semiconductor device is degraded due to the dispersion of the particles, such as the metal oxide semi-transistor or the quality problem caused by the gate leakage current in the memory. The semiconductor device is provided with a stable threshold voltage value. Overall, it not only improves product yield, but also reduces production costs and further enhances product reliability.

In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10. . . Substrate

11. . . Source area

12. . . Bungee area

30, 30’. . . Insulation

40. . . Semiconductor layer

41. . . Semiconductor substrate layer

42. . . Doped layer

51, 111. . . particle

52. . . Impurity

100. . . Semiconductor device

110. . . Synchronous doped polysilicon layer

FIG. 1A is a schematic view showing the particle distribution after depositing the synchronous doped polysilicon layer for 4 hours; FIG. 1B is a schematic view showing the particle distribution after depositing the synchronous doped polysilicon layer for 8 hours; FIG. 1C is a diagram showing the deposition of the synchronous doped polysilicon layer 24 Schematic diagram of particle distribution after hours; FIG. 1D is a schematic view showing the distribution of particles after 48 hours of depositing the synchronous doped polysilicon layer; FIG. 2 is a flow chart showing a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention; A schematic view of a substrate, an insulating layer, and a semiconductor substrate layer according to a preferred embodiment of the present invention; and FIG. 3B is a schematic view showing a surface of the semiconductor substrate layer of the third layer shown in FIG. 3A; FIG. 3C A schematic diagram of the impurity diffused into the semiconductor substrate layer of FIG. 3B; FIG. 3D is a schematic view showing the semiconductor layer of FIG. 3C after being cleaned; FIG. 3E is a diagram showing the impurity doped with the substrate of the 3D pattern after doping FIG. 3F is a schematic view showing the patterning of the insulating layer of FIG. 3E; FIG. 4A is a schematic view showing the distribution of surface particles after one week of forming the semiconductor layer; FIG. 4B is a view showing the surface of the embodiment to which the embodiment is applied; The semiconductor layer is a schematic view of the rear surface of the particle distribution method; and FIG. 5 shows the relationship between time and the number of particles of FIG.

Claims (16)

A surface treatment method for a semiconductor layer, comprising: providing a semiconductor layer, wherein the semiconductor layer is a synchronous doped polysilicon layer, the surface of the semiconductor layer has a plurality of particles; and removing the particles by a cleaning method, The method comprises: contacting the semiconductor layer with an organic material removing agent, then contacting the semiconductor layer with a first peroxide mixture; and contacting the semiconductor layer with a second peroxide mixture, wherein the semiconductor layer is contacted The step of removing the organic material and the step of contacting the semiconductor layer with the first peroxide mixture does not include contacting the semiconductor layer with a hydrofluoric acid. The surface treatment method according to claim 1, wherein the material of the semiconductor layer is ruthenium, osmium or a combination thereof. The surface treatment method according to claim 1, wherein the first peroxide mixture comprises ammonia water (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and de-ionized water. The surface treatment method of claim 2, wherein the second peroxide mixture comprises hydrochloric acid (HCl), hydrogen peroxide, and deionized water. The surface treatment method of claim 1, wherein after the step of contacting the semiconductor layer with the second peroxide mixture, the method further comprises: washing the semiconductor layer with water. The surface treatment method of claim 5, wherein the organic matter removing agent comprises sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide. A method of fabricating a semiconductor device, comprising: providing a substrate; forming an insulating layer over the substrate; forming a semiconductor layer on the insulating layer, wherein the semiconductor layer is a synchronous doped polysilicon layer, the surface of the semiconductor layer Having a plurality of particles; and removing the particles by a cleaning method comprising: contacting the semiconductor layer with an organic removal agent, and then contacting the semiconductor layer with a first peroxide mixture; The semiconductor layer is in contact with a second peroxide mixture, wherein the step of contacting the semiconductor layer with the organic removal agent and the step of contacting the semiconductor layer with the first peroxide mixture does not include: Contact with hydrofluoric acid. The manufacturing method of claim 7, wherein after the step of contacting the semiconductor layer with the second peroxide mixture, the method further comprises: washing the semiconductor layer with water. The manufacturing method of claim 7, wherein the organic matter removing agent comprises sulfuric acid and hydrogen peroxide. The manufacturing method according to claim 7, wherein the first peroxide mixture comprises aqueous ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and de-ionized water. The manufacturing method according to claim 10, wherein the second peroxide mixture comprises hydrochloric acid (HCl), hydrogen peroxide, and deionization. water. The manufacturing method of claim 7, wherein the method further comprises: doping a dopant to the substrate corresponding to both sides of the semiconductor layer. The manufacturing method of claim 12, wherein after the step of infiltrating the impurity, the method further comprises: patterning the insulating layer such that the insulating layer is substantially equal to the semiconductor layer. The manufacturing method according to claim 7, wherein the insulating layer is made of cerium oxide (SiO ₂ ). The manufacturing method according to claim 7, wherein the material of the semiconductor layer is tantalum, niobium or a combination thereof. The manufacturing method of claim 7, wherein the forming the semiconductor layer further comprises: forming the insulating layer of a semiconductor substrate layer covering portion; and diffusing doping by a doped layer (diffusion doping) An impurity enters the semiconductor substrate layer.