1380560 » ί 六、發明說明： 【發明所屬之技術領域】 本發明係有關於切換式電源轉換，特別是關於可調整主變麼 、 器二次側電流路徑關閉時間之切換式電源轉換。 【先前技術】 在電子設備之供電中，切換式電源轉換器因其具有高轉換效 率及小型零件尺寸之優勢而廣被採用。 以返馳式交流轉直流電源轉換器為例，圖la展示一返驰式交 "il轉直流電源轉換器之主變壓器充電週期，圖lb展示一返馳式交 • 流轉直流電源轉換器之主變壓器放電週期。如圖la及圖比所示 之架構包含有一 N型金氧半(NM〇s)電晶體101、一主變壓器1〇2、 一二極體103及一電容1〇4。 在該架構中，該NM0S電晶體101係用以反應於一脈衝寬度調 變（PWM)信號VG1以控制該主變壓器1〇2之電能轉換。 該主變壓器1 〇2係用以將輸入直流電源VlN轉換成一直流輸出 電壓Vcc。 該二極體1〇3係耦接至該主變壓器1〇2之二次側，用以在該 NMOS電晶體ιοί開啟時截斷該二次側之電流路徑，及在該刪 ® 電晶體1〇1關閉時釋放磁通能量至該電容104。當該NM〇s電晶體 101開啟時，該二極體103之陰極電壓為Vin/n+Vcc，其大於該二極 體103之陽極電壓GND’致使該二極體103逆偏而截斷該二次側之 電流路徑；當該NMOS電晶體101關閉時，該主變壓器1〇2二次側 之電壓極性會正、負互換，致使該二極體103之陽極電壓大於其 陰極電壓而使該二次側之電流路徑開啟。 該電容104係用以承載該直流輸出電壓Vcc。 曰藉由一 PWM控制器（未示於圖中）之PWM信號Vgi使該nm〇s電 晶體101週期性地開啟、關閉，輸入電源即可經由該主變壓器1〇2 轉換至輸出端。 3 然而，當磁通能量經由該二極體103釋放時，該二極體1〇3 之開啟電壓〇· 7V會消耗相當多之能量而使轉換效率劣化，特別是 當該直流輸出電壓Vcc額定在一低電壓時。 習知電源轉換器所採用之一解決方案係以具低開啟電壓之一 開關電路取代該二極體103以增進轉換效率。 請參照圖2,其繪示一習知電路’用以開關一返驰式舵轉叱 電源轉換器之變壓器二次側。如圖2所示，該習知電路包含有一 二極體201、一比較器202及一 NMOS電晶體203。 該二極體201係用以在該比較器202及該NMOS電晶體203之 切換速度慢於輸入信號之切換速度時開、關一電源轉換器之變壓 器二次側。 該比較器202及該NMOS電晶體203係用以模擬一二極體之功 能。該比較器202反應該二極體201之陽極電壓及陰極電壓以控 制該NMOS電晶體203之開啟。當該陽極電塵比該陰極電壓高且其 壓差大於一臨界電壓時，該比較器202會將該NMOS電晶體203開 啟’且該NMOS電晶體203之開啟電壓遠小於該二極體2〇1之開啟 電壓；若否，該比較器202會將該NMOS電晶體203關閉。圖2電 路中之開啟電流I與開啟電壓VF之關係示於圖3。如圖3所示， 當Vf超過0. 25mv時，該開啟電流I會以i/Rds〇n之斜率增加；當Vf 低於0· 25mv時，該開啟電流I會縮減至〇。 雖然該習知電路可降低開啟電壓，其仍然有二主要缺點。首 先’該0. 25mv之臨界電壓需要一具較佳解析度之比較器方能匹配 而使該習知電路不易實施。再者，在連續電流模式(c〇ntinu〇us Current Mode ; CCM)中該臨界電壓之數值很難決定。請參照圖4， 當電源轉換器工作於CCM時’若負載狀況由低負載變成高負載， 致使該咼負載所需之二次側截斷電流高於一臨界電流，其中該臨 界電流對應於-預定之臨界電壓（該臨界電壓=該臨界電流χ R_) ’則該顧電路將永遠得不_發减斷該二次側電流路 1380560 徑，而可能導致系統災難。 為解決CCM下之二次側電流路徑截斷相關問題，美國專利 6771059B1提出在二次侧量測該二極體陰極電壓之週期，其係藉由 偵測對應於主側開啟時之一高電壓V1N/N+Vcc而完成（示於圖ia)， 然後依該週期定出截斷該二次側之時間。然而，此方案無法適用 於不連續電流模式（Discontinuous Current Mode ; DCM)，因為在 DCM下，主變壓器中之能量在主側開啟之前早已放光了，其結果 是’該二次側電流路徑之輸出電容會提供一逆向電流，而該逆向 電流會在該主側開啟時干擾該主變壓器之充電。因此，亟需提供 φ 一解決方案’其可妥適截斷CCM下之二次側電流路徑及DCM下之 二次側電流路徑。 有鑒於此瓶頸’本發明提出一新穎的架構，用以產生一關閉 預測信號，以妥適截斷CCM下之二次側電流路徑及DCM下之二次 側電流路徑、避免在二次側電流路徑產生逆向電流。 【發明内容】 本發明之一目的在於提供一二次側關閉時間調整方法，使一 切換式電源轉換器能妥適地截斷CCM下之二次側電流路徑及DCM 下之二次側電流路徑，以避免在二次側電流路徑產生逆向電流。 • 本發明另一目的在於提供一二次側關閉時間調整裝置，使一 切換式電源轉換器能妥適地截斷CCM下之二次側電流路徑及DCM 下之二次侧電流路徑，以避免在二次侧電流路徑產生逆向電流。 本發明又一目的在於提供利用一二次侧關閉時間調整裝置之 一系統，使一切換式電源轉換器能妥適地截斷CCM下之二次側電 流路徑及DCM下之二次侧電流路徑，以避免在二次側電流路徑產 生逆向電流。 為達到本發明前述之目的，一適用於切換式電源轉換之二次 側關閉時間調整方法乃被提出，該方法包含以下步驟：依一第一 參考電壓偵測一二次側電晶體跨電壓之下降緣以產生一第一重置 5 if，第二參考電壓躺該二次侧電晶體跨電壓之上升緣以 設η;依該第—重置信號及該第-設置信號驅動 if 二次側放電結束信號；以及依該二次側 孜電、〜束仏號之週期產生一關閉預測信號。 調敕ίΓ!ί之目的，本發明進一步提出一種二次侧關閉時間 =襄置’其適用於-切換式電源轉換，該裝置具有：一第一比 =產ΓΓ第—參考電壓及—二次側電晶體跨電壓之電壓比 生—第一重置信號；—第二比較器，用以依-第二參考電 二— 人侧電晶體跨電壓之電壓比較而產生—第—設置信號； 第一閃鎖器，用以依該第-重置信號及該第一設置作號產生一 U則放電結束信號；以及—關賴信號產生單/用以依該 一-人側放電結束信號之週期產生一關閉預測信號。 到前述之目的，本發明進—步提出—種糊—二次側關 ^ 曰调整裝置之系統，其制於—她式電源轉換該系統具 ㈣一第-比較器，用以依H考電壓及—二次侧電晶體跨 j之電壓比較而產生-第—重置信號；—第二比較器，用以依 一第一參考電壓及該二次侧電晶體跨電壓之電壓比較而產生一第 「設置信號；-閃鎖器，用以依該第—重置信號及該第一設置信 號產生一一次侧放電結束信號；一關閉預測信號產生單元，用以 依該二次側放電結束信號之週期產生一關預測信號以關閉該二 次側電晶體；以及一脈衝寬度調變控制器，用以產生一脈衝寬度 調變信號以控制該切換式電源轉換。 為使貴審查委員能進一步瞭解本發明之結構、特徵及其目 的’茲附以圖式及較佳具體實施例之詳細說明如后。 【實施方式】 請參照圖5，其繪示一二次側電晶體壓降VdskCCM及此诞之 工作波形，以說明本發明關閉二次側電晶體之主要原理。如圖5 所示，DCM及CCM下之壓降Vds其波形差異在於DCM下之〜波形在 1380560 放電期間具有2V。之峰值。因觀_此差異，本發明乃在放電 期間設置-介於G至2V。間之臨界賴，以_放電結束時間。本 發明由放電結束時間制放電結束聊，再依放電結束時間及放 電，束週期產生-_綱信號以襲二次側電晶體。本發明之 設計在CCM及DCM下都能發揮功效，因為在放電期間所設介於〇 至2V。間之臨界電壓’不管該電源轉換處於CCM或DCM，都能捕捉 到放電結束之_。又’ 2V。之值夠大，使侧侧電路易於實施 且偵測結果較不受雜訊影響。1380560 » ί VI. Description of the Invention: [Technical Field] The present invention relates to switched power conversion, and more particularly to switched power conversion of an adjustable main transformer and a secondary current path turn-off time. [Prior Art] In the power supply of electronic equipment, the switching power converter is widely used because of its high conversion efficiency and small part size. Taking a flyback AC-to-DC power converter as an example, Figure la shows the main transformer charging cycle of a flyback-type il-to-DC power converter. Figure lb shows a fly-back AC/DC converter. Main transformer discharge cycle. The structure shown in Figures la and Figures includes an N-type gold oxide half (NM〇s) transistor 101, a main transformer 1〇2, a diode 103, and a capacitor 1〇4. In this architecture, the NMOS transistor 101 is responsive to a pulse width modulation (PWM) signal VG1 to control the power conversion of the main transformer 〇2. The main transformer 1 〇 2 is for converting the input DC power source VlN into a DC output voltage Vcc. The diode 1〇3 is coupled to the secondary side of the main transformer 1〇2 for cutting off the current path of the secondary side when the NMOS transistor ιοί is turned on, and in the ®® transistor 1〇 When the switch is off, the magnetic flux energy is released to the capacitor 104. When the NM〇s transistor 101 is turned on, the cathode voltage of the diode 103 is Vin/n+Vcc, which is greater than the anode voltage GND' of the diode 103, causing the diode 103 to reverse bias and intercept the two. The current path of the secondary side; when the NMOS transistor 101 is turned off, the voltage polarity of the secondary side of the main transformer 1〇2 is positively and negatively interchanged, so that the anode voltage of the diode 103 is greater than its cathode voltage, so that the second The current path on the secondary side is turned on. The capacitor 104 is used to carry the DC output voltage Vcc. The nm〇s transistor 101 is periodically turned on and off by a PWM signal Vgi of a PWM controller (not shown), and the input power can be converted to the output via the main transformer 1〇2. 3 However, when the magnetic flux energy is released through the diode 103, the opening voltage 〇·7V of the diode 1〇3 consumes a considerable amount of energy and deteriorates the conversion efficiency, especially when the DC output voltage Vcc is rated. At a low voltage. One solution adopted by conventional power converters is to replace the diode 103 with a switching circuit having a low turn-on voltage to improve conversion efficiency. Referring to FIG. 2, a conventional circuit is shown for switching the secondary side of the transformer of a flyback rudder turntable power converter. As shown in FIG. 2, the conventional circuit includes a diode 201, a comparator 202, and an NMOS transistor 203. The diode 201 is configured to turn on and off the secondary side of the transformer of the power converter when the switching speed of the comparator 202 and the NMOS transistor 203 is slower than the switching speed of the input signal. The comparator 202 and the NMOS transistor 203 are used to simulate the function of a diode. The comparator 202 reflects the anode voltage and the cathode voltage of the diode 201 to control the opening of the NMOS transistor 203. When the anode dust is higher than the cathode voltage and the voltage difference is greater than a threshold voltage, the comparator 202 turns on the NMOS transistor 203 and the turn-on voltage of the NMOS transistor 203 is much smaller than the diode 2〇 The turn-on voltage of 1; if not, the comparator 202 turns off the NMOS transistor 203. The relationship between the turn-on current I and the turn-on voltage VF in the circuit of Fig. 2 is shown in Fig. 3. As shown in FIG. 3, when Vf exceeds 0.25 mv, the turn-on current I increases by the slope of i/Rds〇n; when Vf is less than 0·25 mv, the turn-on current I is reduced to 〇. Although this conventional circuit can reduce the turn-on voltage, it still has two major drawbacks. First, the threshold voltage of 0.25 mv requires a comparator of better resolution to match, making the conventional circuit difficult to implement. Furthermore, the value of the threshold voltage is difficult to determine in the continuous current mode (c〇ntinu〇us Current Mode; CCM). Referring to FIG. 4, when the power converter operates in the CCM, 'if the load condition changes from a low load to a high load, the secondary side cutoff current required for the load is higher than a critical current, wherein the critical current corresponds to a predetermined The threshold voltage (the threshold voltage = the critical current χ R_) 'The circuit will never be able to reduce the secondary side current path 1380560 diameter, which may cause system disaster. In order to solve the problem of secondary current path truncation under CCM, U.S. Patent 6,771,059 B1 proposes to measure the period of the diode voltage of the diode on the secondary side by detecting a high voltage V1N corresponding to the main side opening. /N+Vcc is completed (shown in Figure ia), and then the time to cut off the secondary side is determined according to the period. However, this scheme cannot be applied to the Discontinuous Current Mode (DCM) because the energy in the main transformer has already been discharged before the main side is turned on under DCM. The result is that the secondary current path is The output capacitor provides a reverse current that interferes with the charging of the main transformer when the primary side is turned on. Therefore, it is not necessary to provide a φ-solution which can properly intercept the secondary side current path under the CCM and the secondary side current path under the DCM. In view of this bottleneck, the present invention proposes a novel architecture for generating a turn-off prediction signal to properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM to avoid the secondary side current path. A reverse current is generated. SUMMARY OF THE INVENTION One object of the present invention is to provide a secondary side turn-off time adjustment method, such that a switching power converter can properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM. Avoid reverse currents in the secondary side current path. Another object of the present invention is to provide a secondary side closing time adjusting device for enabling a switching power converter to properly cut off the secondary side current path under the CCM and the secondary side current path under the DCM to avoid The secondary current path produces a reverse current. Another object of the present invention is to provide a system for using a secondary side off-time adjusting device to enable a switching power converter to properly cut off the secondary current path under the CCM and the secondary current path under the DCM. Avoid reverse currents in the secondary side current path. In order to achieve the foregoing object of the present invention, a secondary side turn-off time adjustment method suitable for switching power conversion is proposed, the method comprising the steps of: detecting a secondary side transistor cross voltage according to a first reference voltage Decreasing edge to generate a first reset 5 if, the second reference voltage is lying on the rising edge of the secondary side transistor across the voltage to set η; driving the if secondary side according to the first reset signal and the first set signal a discharge end signal; and generating a turn-off prediction signal according to the period of the secondary side chirp and the bundle apostrophe. For the purpose of ί Γ ί ί ί , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The voltage of the side transistor across the voltage is greater than the first reset signal; the second comparator is used to generate a voltage-to-voltage comparison of the voltage of the second side of the second side of the human side transistor - the first setting signal; a flash locker for generating a U-discharge end signal according to the first-reset signal and the first setting signal; and - a signal generating unit/period for the one-person side discharge end signal period A close prediction signal is generated. In view of the foregoing, the present invention further proposes a system for a paste-secondary side-adjusting device, which is manufactured by the her-type power conversion system (4)-first comparator for determining the voltage according to the H test. And - the secondary side transistor crosses the voltage comparison of j to generate - the first - reset signal; - the second comparator is configured to generate a voltage according to a first reference voltage and the voltage of the secondary side transistor across the voltage a first setting signal; a flash locker for generating a primary side discharge end signal according to the first reset signal and the first set signal; and a turn off prediction signal generating unit for ending according to the secondary side discharge The period of the signal generates a turn-off prediction signal to turn off the secondary side transistor; and a pulse width modulation controller for generating a pulse width modulation signal to control the switching power supply conversion. The structure, features, and objects of the present invention will be described in detail with reference to the drawings and preferred embodiments. FIG. 5 illustrates a secondary side transistor voltage drop VdskCCM and The work of this birthday The waveform is used to illustrate the main principle of the invention for closing the secondary side transistor. As shown in Fig. 5, the waveform difference of the voltage drop Vds under DCM and CCM is that the waveform under DCM has a peak value of 2V during the discharge of 1380560. In view of this difference, the present invention is set during the discharge - between G and 2V. The critical value is between _ discharge end time. The present invention ends the discharge by the discharge end time, and then according to the discharge end time and discharge, the bundle The cycle generates a signal to the secondary side of the transistor. The design of the present invention can function in both CCM and DCM because the threshold voltage between 〇 and 2V is set during discharge, regardless of the power conversion. CCM or DCM can capture the end of the discharge. Also '2V. The value is large enough to make the side circuit easy to implement and the detection result is less affected by noise.
請參照圖6,其繪示本發_閉二次側電晶體—較佳實施例之 流程圖。如圖6所示’該方法包含以下步驟：依—第—參考電壓 偵測-二次側電晶體跨電壓之下降緣以產生—第—重置信號(步 驟a);依-第二參考電壓偵測該二次側電晶體跨電壓之上升緣以 產生-第-設置信號(步驟b);依該第一重置信號及該第一設置信 號驅動H鎖操作以產生—二次侧放電結束钱(步驟c);以 及依該二次側放電結束信號之週期產生__酬預測信號(步驟幻。 在步驟a中’該第一參考電壓可設於〇v至_〇. 7v之間，而二 次側電晶體跨電Μ之下降緣代表—放電期間之開始。 在步驟b t，該第二參考電壓可設於〇ν至2V〇之間，而二次 侧電晶體跨電壓之上升緣代表一放電期間之結束。 在步驟c t ’該二次側放電結束信制—脈衝魏，其上升 緣或下降緣之辦變換係由該第―重置錢及該第—設置信號促 成，而該位準變換可用以代表放電期間之結束。 在步驟d中，該關閉預測信號係一脈衝信號，其由該二次側 放電結束信號及該二次側放電結束信號軸之—比值決定，以關 該二次㈣晶體。該_制信號之脈衝產生時間乃可妥適地 定在距主側開啟前一短時間處以避免系統災難發生。 請參麵7，其繪示本發關關—二次侧電晶體—較佳實施例 之方塊圖。如圖7所示’本發明該較佳實施例至少包含一眶電 1380560 I < 晶體7(U、一主變壓器702、一 NMOS電晶體703、一電容704及一 二次側開關控制器705。 在該架構_，該NM0S電晶體701係用以反應於一 PWM信號Vci • 以控制該主變壓器702之電源轉換。 該主變壓器702係用以將輸入直流電源vIN轉至一直流輸出雷 壓 Vcc。 該NM0S電晶體703係耦接至該主變壓器702之二次側，用以 在該二次側開關控制器705 —閘控信號VG2之控制下，於該nm〇s 電晶體701開啟時戴斷該二次側之電流路徑，及於該顺〇s電晶體 φ 7〇1關閉時釋放磁通能量至該電容7〇4。 該電容704係用以承載該直流輸出電壓vC(^藉由一 pWM控制 器（未示於圖中）之PWM信號VG1使該NM0S電晶體701週期性地開 啟、關閉，輸入電源即可經由該主變壓器702轉換至輸出端。 該二次側開關控制器705係用以依該NM0S電晶體703之沒極 電壓Vd產生該閘控信號Vk。相關的操作包括：依一第一參考電壓 偵測該NM0S電晶體703之汲極電壓VD之下降緣以產生一第一重 置信號(步驟a);依一第二參考電壓偵測該NM〇s電晶體7〇3之汲 極電壓Vd之上升緣以產生^第一設置信號(步驟b);依該第一重 馨置仏號及該第一設置信號產生一二次側放電結束信號，其中該二 次側放電結束信號為一脈衝信號，其上升緣或下降緣之位準轉換 乃由該第一重置信號及該第一設置信號促成，且該位準轉換係用 以代表該放電期間之結束（步驟c)，以及依該二次側放電結束信號 之週期產生一關閉預測信號，其中該關閉預測信號係一脈衝信 號，其由該二次侧放電結束信號及該二次側放電結束信號週期之 一比值決定，以關閉該二次側電晶體。該關閉預測信號之脈衝產 生時間乃可妥適地定在距主側開啟前一短時間處以避免系統災難 發生（步驟d)。 圖8繪示了圖7中該二次侧開關控制器7〇5之一細部方塊圖。 8 1380560 如圖8所示’該二次側開關控制器705包含一比較器8〇1、一比較 器802、一閂鎖器803、一反相器804、一遮蔽時間模組8〇5、一 或閘806、一 SR閂鎖器807、一緩衝器808及一關閉預測信號產 生單元809。 該比較器801係用以依該没極電壓Vd及一第一參考電壓 Vth’OT/<)ff產生一第一重置信號，而該比較器8〇2係用以依該汲 極電壓Vd及一第二參考電壓Vth,rising產生一第一設置信號ysET1，其 中該第二參考電壓Vth,rising大於該第一參考電壓Vth,cn/()i。 該閃鎖器803及反相器804係用以依該第一重置信號Vreseti及 •該第一設置信號VsET1產生一二次侧放電結束信號V2nddischend，其中該 一久側放電結束彳g號Vhddisehend為一脈衝信號，其上升緣或下降緣之 位準轉換乃由該第一重置信號VresET1及該第一設置信號Vsm促成， 且該位準轉換係用以代表該放電期間之結束。 該遮蔽時間模組805係用以依該第一重置信號Vreset ,產生一第 二設置信號Vset2及一關閉信號V〇FF，其中該第二設置信號係用 以開啟該二次侧電晶體703，而該關閉信號VGFF則用以強迫該二次 侧電晶體703關閉。 該或閘806係用以依該關閉信號V〇FF及一關閉預測信號^™!) 產生一第二重置信號VRESET2。 , 該SR閂鎖器807及緩衝器808係用以依VsET2及V_產生該 • 閘控信號Vg2’其中VSET2用以使該閘控信號Vgz輸出開啟狀態以開啟 ， 該二次側電晶體703，而Vreset2用以使該閘控信號yG2輸出關閉狀態 以關閉該二次侧電晶體703。 該關閉預測信號產生單元809係用以依該二次侧放電結束信 號V2nddisdienti產生該關閉預測信號V〇 FFPRED ’其中該關閉預測信號V〇FFPRED 係一脈衝信號，其由該二次側放電結束信號v2nddisehend及該二次側放 電結束信號Vaiddischend其週期之一比值決定，以關閉該二次側電晶體 703。 9 1380560 圖9繪示圖8中該關閉預測信號產生單元809之一細部方塊 圖。如圖9所示，該關閉預測信號產生單元809包括一 D型正反 器901、一單發脈波產生器902、一開關903、一電流源904、一 電谷905、一運算放大器906、一電阻907、一電阻908、一比較 器909、一單發脈波產生器910、一開關911、一電流源912、一 電谷913、一運算放大器914、一電阻915、一電阻916、一比較 器917及一開關單元918。 該D型正反器901係用以依Vhddischend產生一第一選擇信號Vsela 及一第二選擇號Vselb。該D型正反器901乃充當一除頻器以使VseU 鲁之脈衝與vselb之脈衝可交替呈現。 該單發脈波產生器902係用以依Vsela產生一第一放電脈衝 RESETA ° 該開關903係用以反應於RESETA而對該電容905實施放電。 該電流源904及該電容905係用以產生一斜波信號Vrampa。 該運算放大器906、電阻907及電阻908係用以產生該第一斜 波4s Vrampa 之一分壓 Vrefa。 該比較器909係用以依該Vrampa及一分壓Vrefb產生一第一關閉 預測號 VoFTPREDICTA。 • 該單發脈波產生器910係用以依Vselb產生一第二放電脈衝 RESETB 〇 … 該開關911係用以反應於RESETB而對該電容913實施放電。 • 該電流源912及該電容913係用以產生一斜波信號Vrampb。 該運算放大器914、電阻915及電阻916係用以產生該第二斜 波信號Vrampb之一分壓Vrefb。 該比較器917係用以依該Vrampb及Vrefa產生一第二關閉預測信 號 VoFFPREDICTB 〇 鼇 該開關早元918係用以在Vsela之控制下’使VoFFPREDICTA與VoFFPREDICTB 父替呈現以產生VoFTPRED。 1380560 圖7、圖8及圖9之CCM工作波形示於圖1〇，而圖7、圖8 及圖9之DCM工作波形示於圖U。如圖1〇及圖u所示，v〇_ 之每-個脈衝均在V2nddlsehend上升緣之—小段時間前出現，而v__ 與Vqffpredictb係交替呈現以產生V〇FFPRED。 利用如圖8及圖9所示本發明-較佳實施例之二次側關閉時 間調整裝置實現圖7中該二次側開關控制器7G5，—可調整二 關閉時間之AC轉DC魏轉換邱得呈現。糾 用於AC轉AC, DC轉AC，orDC轉DC之切換式電源轉換。兀了應 於太，乃較佳實施例，舉凡局部之變更或修飾而源 ΐ 熟習該項技藝之人所易於推知者，例如引 ^載波讀财式、取樣點數之變更、 ^數之變更、平滑化處理方式之變更等，俱不脫 綜上所陳，本案無論就目的、手段與 ，之技術特徵，且其首先發明合於實 =:= 社會，實感德便。委員明察並祈早日賜予專利，俾嘉惠 【圖式簡單說明] 麼器示意圖’其繪示一返驰式AC㈣電源轉換器之變 圖1 b為一'示音屠| ^ 壓器放電賴。 錢卜返喊AG#Det轉換器之變 圖2為一示意圖，甘 轉DC電源轉換器之變懕^會不一習知電路’用以開關一返馳式AC 圖3為一示音圖^二次側。 圖4為一^意圖示圖2習知電路之B特性曲線。 之二次侧電流相對於時門、不連續電流模式及連續電流模式下Referring to Figure 6, there is shown a flow chart of a preferred embodiment of the present invention. As shown in FIG. 6 , the method includes the following steps: the first-reference voltage detection-secondary transistor cross-voltage falling edge to generate a -first reset signal (step a); the second-reference voltage Detecting a rising edge of the secondary side transistor across the voltage to generate a -first setting signal (step b); driving the H-lock operation according to the first reset signal and the first setting signal to generate - the secondary side discharge ends Money (step c); and generating a __reward prediction signal according to the period of the secondary side discharge end signal (step magic. In step a, the first reference voltage may be set between 〇v and _〇. 7v, The falling edge of the secondary side transistor across the power 代表 represents the beginning of the discharge period. In step bt, the second reference voltage can be set between 〇ν and 2V〇, and the rising edge of the secondary side transistor across the voltage Representing the end of a discharge period. In step ct 'the secondary side discharge end signal system - the pulse Wei, the rising edge or the falling edge of the transformation is caused by the first "replacement money" and the first setting signal, and the A level shift can be used to represent the end of the discharge period. In step d, the close prediction letter a pulse signal, which is determined by the ratio of the secondary side discharge end signal and the secondary side discharge end signal axis to close the secondary (four) crystal. The pulse generation time of the _ signal can be properly determined A short time before opening from the main side to avoid system disasters. Please refer to Figure 7, which shows a block diagram of the present invention - a secondary side transistor - a preferred embodiment. The preferred embodiment includes at least one germanium 1380560 I < crystal 7 (U, a main transformer 702, an NMOS transistor 703, a capacitor 704, and a secondary side switch controller 705. In the architecture, the NM0S The transistor 701 is configured to react to a PWM signal Vci to control the power conversion of the main transformer 702. The main transformer 702 is configured to turn the input DC power source vIN to the DC output voltage Vcc. The NM0S transistor 703 is The second side of the main transformer 702 is coupled to the secondary side switch controller 705, the gate control signal VG2, and the secondary side current is turned on when the nm〇s transistor 701 is turned on. Path, and when the transistor φ 7〇1 is turned off The magnetic flux is applied to the capacitor 7〇4. The capacitor 704 is used to carry the DC output voltage vC (the periodicity of the NMOS transistor 701 is made by a PWM signal VG1 of a pWM controller (not shown). When the ground is turned on and off, the input power can be converted to the output through the main transformer 702. The secondary side switch controller 705 is configured to generate the gate control signal Vk according to the gate voltage Vd of the NMOS transistor 703. The operation includes: detecting a falling edge of the drain voltage VD of the NM0S transistor 703 according to a first reference voltage to generate a first reset signal (step a); detecting the NM〇s according to a second reference voltage a rising edge of the drain voltage Vd of the crystal 7〇3 to generate a first set signal (step b); generating a secondary side discharge end signal according to the first reset nickname and the first set signal, wherein the The secondary side discharge end signal is a pulse signal, and the level transition of the rising edge or the falling edge is facilitated by the first reset signal and the first set signal, and the level conversion is used to represent the discharge period. End (step c), and according to the secondary side discharge end signal The cycle generates a shutdown prediction signal, wherein the shutdown prediction signal is a pulse signal determined by a ratio of the secondary side discharge end signal and the secondary side discharge end signal period to turn off the secondary side transistor. The pulse generation time of the off prediction signal can be properly set a short time before the main side is turned on to avoid a system disaster (step d). FIG. 8 is a detailed block diagram of the secondary side switch controller 7〇5 of FIG. 7. 8 1380560 As shown in FIG. 8 , the secondary side switch controller 705 includes a comparator 8〇1, a comparator 802, a latch 803, an inverter 804, and a masking time module 8〇5. A gate 806, an SR latch 807, a buffer 808, and a turn-off prediction signal generating unit 809. The comparator 801 is configured to generate a first reset signal according to the step voltage Vd and a first reference voltage Vth'OT/< ff, and the comparator 8 〇 2 is configured to be according to the drain voltage Vd and a second reference voltage Vth,rising generate a first set signal ysET1, wherein the second reference voltage Vth,rising is greater than the first reference voltage Vth,cn/()i. The flash locker 803 and the inverter 804 are configured to generate a secondary side discharge end signal V2nddischend according to the first reset signal Vreseti and the first set signal VsET1, wherein the one-side discharge end 彳g number Vhddisehend is The level transition of the rising edge or the falling edge of a pulse signal is facilitated by the first reset signal VresET1 and the first set signal Vsm, and the level transition is used to represent the end of the discharge period. The masking time module 805 is configured to generate a second setting signal Vset2 and a closing signal V〇FF according to the first reset signal Vreset, wherein the second setting signal is used to turn on the secondary side transistor 703. And the off signal VGFF is used to force the secondary side transistor 703 to be turned off. The OR gate 806 is configured to generate a second reset signal VRESET2 according to the turn-off signal V〇FF and a turn-off prediction signal ^TM!). The SR latch 807 and the buffer 808 are configured to generate the gating signal Vg2' according to VsET2 and V_, wherein VSET2 is used to enable the gating signal Vgz to be turned on to turn on, the secondary side transistor 703 And Vreset2 is used to output the gating signal yG2 to the off state to turn off the secondary side transistor 703. The off prediction signal generating unit 809 is configured to generate the off prediction signal V〇FFPRED ' according to the secondary side discharge end signal V2nddisdienti, wherein the off prediction signal V〇FFPRED is a pulse signal, and the secondary side discharge end signal is The ratio of the period of v2nddisehend and the secondary side discharge end signal Vaiddischend is determined to close the secondary side transistor 703. 9 1380560 FIG. 9 is a detailed block diagram of the off prediction signal generating unit 809 of FIG. As shown in FIG. 9, the shutdown prediction signal generating unit 809 includes a D-type flip-flop 901, a single-shot pulse generator 902, a switch 903, a current source 904, a valley 905, an operational amplifier 906, a resistor 907, a resistor 908, a comparator 909, a single pulse generator 910, a switch 911, a current source 912, a valley 913, an operational amplifier 914, a resistor 915, a resistor 916, a The comparator 917 and a switch unit 918. The D-type flip-flop 901 is configured to generate a first selection signal Vsela and a second selection number Vselb according to Vhddischend. The D-type flip-flop 901 acts as a frequency divider to alternate the VseU pulse and the Vselb pulse. The single pulse generator 902 is configured to generate a first discharge pulse RESETA according to Vsela. The switch 903 is configured to discharge the capacitor 905 in response to RESETA. The current source 904 and the capacitor 905 are used to generate a ramp signal Vrampa. The operational amplifier 906, the resistor 907 and the resistor 908 are used to generate a partial voltage Vrefa of the first ramp 4s Vrampa. The comparator 909 is configured to generate a first shutdown prediction number VoFTPREDICTA according to the Vrampa and a voltage divider Vrefb. • The single pulse generator 910 is configured to generate a second discharge pulse RESETB according to Vselb. The switch 911 is configured to discharge the capacitor 913 in response to RESETB. • The current source 912 and the capacitor 913 are used to generate a ramp signal Vrampb. The operational amplifier 914, the resistor 915 and the resistor 916 are used to generate a voltage divider Vrefb of the second ramp signal Vrampb. The comparator 917 is configured to generate a second shutdown prediction signal VoFFPREDICTB according to the Vrampb and Vrefa. The switch early element 918 is used to render the VoFFPREDICTA and the VoFFPREDICTB parent to generate VoFTPRED under the control of Vsela. 1380560 The CCM operating waveforms of Figures 7, 8, and 9 are shown in Figure 1A, and the DCM operating waveforms of Figures 7, 8, and 9 are shown in Figure U. As shown in Fig. 1 and Fig. u, each pulse of v〇_ appears before the rising edge of V2nddlsehend—small time v__ and Vqffpredictb alternately appear to produce V〇FFPRED. The secondary side switch controller 7G5 of FIG. 7 is realized by using the secondary side closing time adjusting device of the present invention as shown in FIG. 8 and FIG. 9, which can adjust the AC turn-off DC conversion of the second closing time. Have to be presented. Corrected for AC to AC, DC to AC, orDC to DC switching power conversion.兀 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 较佳The change of the smoothing treatment method, etc., is not inconsistent with the fact that the case is based on the purpose, means and technical characteristics, and its first invention is combined with the real =:= society, real sense of virtue. The committee clearly inspected and prayed for the patent as soon as possible. Zhai Jiahui [Simple diagram] The schematic diagram of the device is shown as a change of the AC (four) power converter. Figure 1 b is a 'sounding sound | ^ Pressure discharge. Figure 2 shows a diagram of the change of the AG#Det converter. The change of the DC-to-DC converter is not a conventional circuit. It is used to switch a flyback AC. Figure 3 is a sound map ^ Secondary side. Fig. 4 is a view showing a B characteristic curve of the conventional circuit of Fig. 2. Secondary current relative to time gate, discontinuous current mode, and continuous current mode
圖5為不意圖，其繪示—二次侧電晶體壓降Vos於CCM及DCM 1380560 之工作波形 圖 施例之流程圖 ’以說明本發明關閉二次側電晶體之主要原理。 ^一示意圖’其繪示本發明關閉二次側電晶體一較佳實 圖7為一示意圖， 實施例之方塊圖。 圖8為一示意圖， 方塊圖。 其繪示本發明開關一二次側電晶體一較佳 其繪示圖7中二次側開關控制器之一細部Figure 5 is a schematic diagram showing the operation of the secondary side transistor voltage drop Vos at CCM and DCM 1380560. The flow chart of the embodiment is used to illustrate the main principle of the invention for closing the secondary side transistor. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an embodiment of the present invention. Figure 8 is a schematic, block diagram. It is shown that the switch and the secondary side transistor of the present invention are preferably one of the details of the secondary side switch controller of FIG.
圖10為一不意圖，其繪示圖7，圖8及圖9之CCM工作波妒 圖11為一示意圖，其繪示圖7，圖8及圖9之DCM工作波形FIG. 10 is a schematic diagram showing the CCM operation waveforms of FIG. 7, FIG. 8 and FIG. 9. FIG. 11 is a schematic diagram showing the DCM working waveforms of FIG. 7, FIG. 8 and FIG.
圖9為-示意圖，其繪示圖 細部方塊圖。 【主要元件符號說明】 NM0S 電晶體 1(Π、203、7(Π、703 二極體 103、201 比較器202 比較器8(η、802 反相器804 或閘806 缓衝器808 D塑正反器901 開關 903、911 電容 905、913 電阻 907、908、915、916 開關單元918 中關閉預測信號產生單元之_ 變壓器102、702 電容 104、704 二次側開關控制器705 閂鎖器803 遮蔽時間模組805 SR閂鎖器807 關閉預測信號產生單元809 單發脈波產生器902、91〇 電流源904、912 運算放大器906、914 比較器909、917 12Figure 9 is a schematic view showing a detailed block diagram. [Main component symbol description] NM0S transistor 1 (Π, 203, 7 (Π, 703 diode 103, 201 comparator 202 comparator 8 (n, 802 inverter 804 or gate 806 buffer 808 D plastic positive) 901 switch 903, 911 capacitor 905, 913 resistor 907, 908, 915, 916 switch unit 918 off the prediction signal generating unit _ transformer 102, 702 capacitor 104, 704 secondary side switch controller 705 latch 803 shielding Time module 805 SR latch 807 off prediction signal generation unit 809 single pulse generator 902, 91 〇 current source 904, 912 operational amplifier 906, 914 comparator 909, 917 12