1380399 九、發明說明： 【發明所屬之技術領域】 罩之ΐ==::Γ構的形成方法，特別是關於具硬 【先前技術】 習知要在半導縣板_麟渠，通常 溝渠的位置。然後，再輪被圖案化硬罩二 ί ϊΐίίΓΓ以形成溝渠。—般而言’要形成外觀比值較大 的溝w要厚紐高的硬罩。_，要_化厚度高的硬 較困難。 圖1Α及1Β係顯示以習知技術圖案化基板1〇上之硬罩12 的過程。如圖所示’先在硬罩12上形成圖案化多晶石夕13。然後， 以圖案化多秘13為遮罩’藉由乾式蝴，移除不被圖案化多 晶石夕13所覆蓋之硬罩材料12a。然而，在實作過程中經過乾 触刻後之所職結構摊與職㈣，因為乾式侧在移除硬 材料12a的同時’也很容易侵_圖案化多晶石夕13底下的硬 材料12b。圖1B即顯示這種不符要求的硬罩結構，其中有 分之硬罩_ 12b呈朗凹縣，更有—部分之硬罩⑶因嚴重 的内凹現象崎裂。像這樣的硬罩結構，對於後續要在基板中步 成外觀比值高㈣渠财不良的影響。因此，需要有—種^ 方法來解決習知的問題。 【發明内容】 以形成深 本發明圖案化硬罩之方法係先钱刻一部分之硬罩， 4NTC/06020TW ； 2004-0153-TW 5 1380399 f較J的開口於硬罩層令。接著，在此開口的側壁上形成 層，然後再繼續往下則達到贼的深度。'藉由阻障層保護側 壁，可避免側壁遭侵钱而内凹，如此可解決習知的問題而 合期望的圖案化硬罩結構。、 ^ θ於一方面，本發明係揭示一種半導體結構的形成方法，包含 提供-基板；形成-第-硬罩層於基板上；形成—開口於第一硬 罩層内，開口具有—第一深度且暴露—側壁及_底表面；形成一 共形阻障賴蓋麵及絲面；絲覆蓋絲面的轉^而保留 覆蓋側壁的阻障層；及姓刻底表面以使開口形成大於第一 ' 一第二深度。 又 於另一方面，本發明係揭示一種半導體結構的形成方法，包 含提供一基板；形成一第一硬罩層於基板上；形成一第二硬罩層 於第一硬罩層上；形成一開口於第二硬罩層内，開口暴露一侧^ 及一底表面；形成一共形阻障層覆蓋側壁及底表面；去除覆蓋底 表面的共形阻障層而保留覆蓋側壁的阻障層；蝕刻底表面之第二 硬罩層及第一硬罩層以露出基板。 【實施方式】 以下將參考所附圖式示範本發明之較佳實施例。所附圖式中 相似元件係採用相同的元件符號。應注意為清楚呈現本發明，所 附圖式中之各元件並非按照實物之比例繪製，而且為避免模糊本 發明之内容，以下說明亦省略習知之零組件、相關材料、及其相 關處理技術。 4NTC/06020TW ； 2004-0153-TW 6 、圖2至圖7係依據本發明之—實施例，顯示具硬罩之半導體. =過程的剖面示意L 2所示，本實施例係從提供一基板 開始。基板20可為任何合適的半導體基板或習知的石夕晶圓。 二II言，基板100可為石夕基板、石夕鍺基板、絕緣層上石夕基板、 =:上稍基板或於其他不_雜段辭成品基板。於此實 &列係以石夕基板為例，但不以此為限。 竇力~接^ ’如圖2所示，依序在基板20上沉積各硬罩層。在本 j中’各硬罩層包含墊氧化層2卜氮化矽層22、矽玻璃層 “ ^曰曰石夕層24。可用各種習知技術來形成各硬罩層。舉例而 成墊氧化層21可利用爐管熱氧化法，可沉積厚度約為雇 減層21。軸氮切層22可_齡式健化學氣相 ’可沉積厚度約為⑽埃至2，_埃。石夕玻璃層23的沉 來職四魏鹽(TE0S)作為前驅物，並以化學氣相沉積法 ΐίΐ愈ϋ過程中可視需要換__元素。石夕玻璃層23 例所要形成溝渠的外觀比值有關。本實施 為二驅物215，簡埃為例。多妙層24的沉積可财甲烧作 相沉積法來形成。多晶石夕層24係用作圖案 他各硬罩層所需之遮罩，可沉積厚度約為埃至2，_ 24，以=以f知的光阻微影製程圖案化多晶石夕層 的多晶妙/24為遮罩=、ΓΓ。接著，如圖4所示，以圖案化 夕夕層24為遮罩，飯刻石夕玻璃層23而形成且 产 D1的開口 4卜開口 41暴露出 又 係採用乾式侧來進行，並可獅^^广f面^。此步驟較佳 伴祁對於多晶矽層24，對矽玻璃 4NTC/06020TW : 2004-0〗 53-TW 7 …，〜奸丨王的蝕刻氣體，例如rp A „ 可控制蝕刻時間來決m ca、at及〇2等等< 的較佳範圍在2，_本實施例中第一深度以 表面=t:=rr51覆蓋側壁42及底 氣相沉躲細μ，厚餘錄5 壓化學 在此將覆蓋側壁42的阻障# _2〇埃。為〉月楚地說明， 障層稱為阻障層53 杨為阻障層52，覆蓋絲面43的阻 的阻^5’3 = 11示/執行，刻步驟以去除覆蓋底表面43 m。詳4二度力Γ形成大於第-深度D!的-第二深度 有高選擇性_ ^選彳擇相對於多_層24，射玻璃層23 等二ί例41?6、阳8、々及02等等。將此 體導反應室後，施加高頻賴，以產生《。庫注音 騎轉層53有高選雜的侧氣體。轉^ ’ Μ㈣魏量的賴來縣絲面43上方的 ^ 53 ’就可突破阻障層53而進人魏璃層23。而且，由於 量^= = 壁42之阻障層52的電聚其能 二係^ ^也較弱，所以側壁42上之阻障層2可以保留下 ==阻障層53而進入魏璃層23後，可視需要降低 石夕玻璃心觀體财軸層23的化學反麟續地去除 :第3罙度D2。從上述應可瞭解，第二深度02 底。同時，也射_，以乾式侧去除覆蓋 底表面43的阻障層53及底表面43之魏璃層23，係可在同一 4NTC/06020TW ; 2004-0153-TW 8 反應器中進行。 然後’如圖7所示，進行去除氮化石夕層22及底下之墊氧化 層21的步驟，以暴露出基板20。此步驟可接續上述之乾式姓刻， 在同反應器令進行。換言之，即在姓刻完石夕破璃層Μ之後， 將蝕刻^職成撕㈣玻麟23，職切I 22及對墊氧化 層21有n選擇性的钱刻氣體，例如、CF>4、"及〇2等等， 以完成此夠。餘意在侧氮化_ 22時可能會耗損一部分 圖6及圖7所揭示的步驟中，由於侧壁幻上覆蓋有阻障層 52 ’故可避免於侧過程中形成不良的内凹結構。由此應可瞭曰 本發日月所揭示之方法係可使厚度高的多層硬罩層經由钮刻而 達成符合預期的圖案化多層硬罩層結構。 至繼上述各步驟之後，可利用習知技術再進行姓刻以形成溝 =80於基板2〇中，如圖8所示。如有需要完全移除覆蓋在侧塑 42土的阻障層52，則可使腿式侧，例如將基板浸泡在熱填 酸中即可將阻障層52移除。 以上所述僅為本發明之雛實施_已，麟肋限定本發 明之申請專利凡其它未脫離本發明所揭示之精神下所完成 之等效改變絲飾’均應包含在下狀巾請專利範圍内。 4NTC/06020TW ; 2004-0153-TW 9 1380399 【圖式簡單說明】 圖1A至1B為習知之半導體結構製作過程的剖面圖。 圖2至圖8為本發明之半導體結構製作過程的剖面圖。 【主要元件符號說明】 10, 20基板 12硬罩 13圖案化多晶矽 12a, 12b硬罩材料 21墊氧化層 22氮化矽層 23矽玻璃層 24多晶矽層 42側壁 43底表面 51共形阻障層 52, 53阻障層 80溝渠 4NTC/06020TW ； 2004-0153-TW 101380399 IX. Description of the invention: [Technical field to which the invention belongs] 罩 ΐ ==:: The formation method of the Γ structure, especially regarding the hard [previous technique] It is customary to use the semi-conductor plate _ lin channel, usually ditch position. Then, the wheel is patterned into a hard cover to form a ditch. In general, it is necessary to form a hard cover with a large aspect ratio groove w. _, it is difficult to make the thickness of the hard. 1A and 1B show the process of patterning the hard mask 12 on the substrate 1 by conventional techniques. As shown in the figure, a patterned polycrystalline spine 13 is formed on the hard mask 12. Then, the patterned multi-secret 13 is used as a mask. By the dry butterfly, the hard mask material 12a not covered by the patterned polycrystalline stone 13 is removed. However, in the actual process, after the dry contact, the structure of the job is spread (4), because the dry side is also easy to invade while removing the hard material 12a. The hard material 12b under the patterned polycrystalline stone 13 . Fig. 1B shows the non-required hard cover structure, in which the hard cover _ 12b is in the Langyin County, and the partial hard cover (3) is cracked due to severe concave phenomenon. A hard cover structure like this has an effect on the subsequent appearance of a high ratio of appearance in the substrate (4). Therefore, there is a need to have a method to solve the conventional problems. SUMMARY OF THE INVENTION In order to form a deep hard mask of the present invention, a method of engraving a part of the hard cover, 4NTC/06020TW; 2004-0153-TW 5 1380399 f is a hard cover layer. Next, a layer is formed on the side wall of the opening, and then continues down to reach the depth of the thief. By protecting the side walls by the barrier layer, it is possible to prevent the side walls from being invaded and recessed, so that the conventional problem can be solved and the desired patterned hard mask structure can be solved. In one aspect, the present invention discloses a method of forming a semiconductor structure, comprising: providing a substrate; forming a -first hard mask layer on the substrate; forming - opening in the first hard mask layer, the opening having - first Depth and exposed—sidewall and _ bottom surface; forming a conformal barrier to cover surface and silk surface; wire covering the surface of the silk to retain the barrier layer covering the sidewall; and surname the bottom surface to make the opening form larger than the first ' A second depth. In another aspect, the invention discloses a method for forming a semiconductor structure, comprising: providing a substrate; forming a first hard mask layer on the substrate; forming a second hard mask layer on the first hard mask layer; forming a Opening in the second hard mask layer, the opening exposing the side surface and the bottom surface; forming a conformal barrier layer covering the sidewall and the bottom surface; removing the conformal barrier layer covering the bottom surface while leaving the barrier layer covering the sidewall; The second hard mask layer of the bottom surface and the first hard mask layer are etched to expose the substrate. [Embodiment] Hereinafter, preferred embodiments of the present invention will be exemplified with reference to the accompanying drawings. Like components in the drawings have the same component symbols. It should be noted that the present invention is not to be construed as being limited to the scope of the present invention, and the present description also omits the known components, related materials, and related processing techniques. 4NTC/06020TW; 2004-0153-TW 6 , FIG. 2 to FIG. 7 show a semiconductor having a hard mask according to an embodiment of the present invention. The cross-sectional illustration of the process is shown by L 2 , and this embodiment provides a substrate. Start. Substrate 20 can be any suitable semiconductor substrate or a conventional silicon wafer. In the second statement, the substrate 100 can be a Shixi substrate, a stone substrate, an insulating layer, a substrate, a lower substrate, or another substrate. The actual & column is based on the Shixi substrate, but is not limited thereto. The sinus force is connected to the metal layer as shown in FIG. 2, and the hard mask layers are sequentially deposited on the substrate 20. In the present invention, each of the hard mask layers includes a pad oxide layer 2, a hafnium nitride layer 22, and a hafnium glass layer. The hard cap layer can be formed by various conventional techniques. The layer 21 can be thermally oxidized by a furnace tube, and can be deposited to a thickness of about the employment layer 21. The axial nitrogen layer 22 can be deposited in a thickness of about (10) angstroms to 2, angstroms. Layer 23's Shenwei Siwei salt (TE0S) is used as a precursor, and the chemical vapor deposition method can be used to change the __ element in the process of ΐ ΐ 。 。 。 。 。 。 。 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石 石Implemented as a two-disc 215, Jane is an example. The deposition of the layer 24 can be formed by a phase deposition method. The polycrystalline layer 24 is used as a mask for patterning the hard mask layers. The thickness can be deposited to about 2, _ 24, and the polycrystalline micro-pattern of the polycrystalline lithographic layer can be patterned as a mask =, ΓΓ. The patterning of the layer 24 as a mask, the formation of the stone layer 23 of the stone, and the opening 4 opening 41 of the D1 is exposed and the dry side is used, and Can be lion ^ ^ wide f surface ^. This step is better with 祁 for polycrystalline 矽 layer 24, 矽 glass 4NTC/06020TW : 2004-0〗 53-TW 7 ..., 丨 丨 的 的 etching gas, such as rp A „ The preferred range of controlling the etching time to determine m ca, at, and 〇 2, etc. is 2, in the present embodiment, the first depth covers the side wall 42 and the bottom gas phase sinking fine μ, thick by surface = t:=rr51, thick The residual chemistry 5 will cover the barrier of the sidewall 42# _2 〇. For the description of the moon, the barrier layer is called the barrier layer 53. The yang is the barrier layer 52, and the resistance of the barrier covering the surface of the wire 43 is shown or performed. The engraving step is to remove the cover bottom surface by 43 m. Detailed 4 second-degree force Γ formation is greater than the first-depth D! - the second depth has high selectivity _ ^ selection choice relative to the multi-layer 24, the glass layer 23, etc. two examples 41? 6, yang 8, 々 And 02 and so on. After the body is guided into the reaction chamber, a high frequency is applied to produce ". The library sounding rider layer 53 has a high side gas. Turn ^ Μ 四 (4) Wei amount of the Lai Lai County silk surface 43 above the ^ 53 ′ can break through the barrier layer 53 and enter the Wei glass layer 23 . Moreover, since the electrical conductivity of the barrier layer 52 of the wall 42 is also weak, the barrier layer 2 on the sidewall 42 can remain under the == barrier layer 53 and enter the Wei glass layer. After 23, it is possible to reduce the chemical reversal of the Shixi glass heart and body axis 23 as needed: the third degree D2. It should be understood from the above that the second depth is 02. At the same time, it is also possible to remove the barrier layer 53 covering the bottom surface 43 and the Wei glass layer 23 of the bottom surface 43 by the dry side, which can be carried out in the same 4NTC/06020TW; 2004-0153-TW 8 reactor. Then, as shown in Fig. 7, a step of removing the nitride layer 22 and the underlying pad oxide layer 21 is performed to expose the substrate 20. This step can be followed by the above-mentioned dry type of engraving, in the same reactor order. In other words, after the surname is finished, the glaze layer is etched, and the etched (4) Brin 23, the job I 22 and the pad oxide layer 21 have n selective money engraving gas, for example, CF>4 , " and 〇2, etc., to complete this enough. It may be that some of the steps disclosed in FIGS. 6 and 7 may be avoided in the steps disclosed in FIGS. 6 and 7. Since the sidewall is magically covered with the barrier layer 52', it is possible to avoid formation of a poor recessed structure in the side process. It should be noted that the method disclosed in this publication is to enable a multilayer hard mask layer having a high thickness to be patterned to achieve a desired patterned multilayer hard mask structure. After the above steps, the conventional technique can be used to form a groove = 80 in the substrate 2, as shown in FIG. If it is desired to completely remove the barrier layer 52 overlying the side mold, the barrier layer 52 can be removed by immersing the substrate in a hot fill. The above description is only for the practice of the present invention. The patent application of the present invention is not limited to the scope of the present invention. Inside. 4NTC/06020TW; 2004-0153-TW 9 1380399 BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1B are cross-sectional views showing a conventional semiconductor structure fabrication process. 2 to 8 are cross-sectional views showing a process of fabricating a semiconductor structure of the present invention. [Main component symbol description] 10, 20 substrate 12 hard cover 13 patterned polysilicon 12a, 12b hard mask material 21 pad oxide layer 22 tantalum nitride layer 23 germanium glass layer 24 polysilicon layer 42 sidewall 43 bottom surface 51 conformal barrier layer 52, 53 barrier layer 80 ditch 4NTC/06020TW; 2004-0153-TW 10