TWI379419B - Methods of achieving linear capacitance in symmetrical and asymmetrical emi filters with tvs - Google Patents

Description

1379419 . 1 October 5, 2012, revised invention, invention: [Technical Field] [0001] The present invention generally relates to a circuit structure of a filter circuit with an inductor including a transient suppression diode (TVS) and Production method. More particularly, the present invention relates to an optimized circuit structure and manufacturing method for a filter circuit provided with a resistor-capacitor (RC) or an inductor-capacitor (LC) with increased capacitance, for symmetrical bidirectional modularization including The regulated diode and the regulated diode trigger the transient suppression diode (TVS) of the bipolar transistor. [Prior Art] ® [0002] A method of designing and manufacturing a filter circuit having a resistor-capacitor (RC) or an inductor-capacitor (LC) in the prior art faces the challenge of increasing the capacitance to achieve a certain filtering effect. A typical practice for those of ordinary skill in the art is to increase the connection area for the purpose of increasing capacitance. However, since the device produced by the present method further has a larger wafer size or a thicker oxide layer in the trench, it causes unnecessary device design and degradation of performance. In addition to these technical challenges, the prior art of designing and fabricating chopper circuits such as a combination of a transient suppression diode (TVS) and an electromagnetic interference (Ε Μ I) filter still faces a technical problem, namely The filter performance becomes unreliable due to changes in the capacitance currently used for the EM I filter. In particular, as will be further described below, changes in capacitance are induced by changes in bias voltage and several environmental effects including light and noise. For audio signal reception, the quality of the input signal reception is negatively affected when the performance exhibited by the chirp filter is not accurately controlled. When the operating environment state changes, the change in capacitance in the ΕΜΙ filter may result in signal reception such as cutoff frequency. Form No. 1010101 Page 5 of 32 1379419

12012 1 & 5th, the special function parameters of Amendment I changed. Therefore, there is an urgent need for an effective solution to this problem. In particular, transient suppression diode (TVS) circuits are typically placed with electromagnetic interference (EMI) filters for receiving audio signals. versus

The TVS provided together with the EMI filter may have a symmetrical or asymmetrical structure as shown in FIG. 1A or FIG. 1B, respectively. The MI filter shown in the figure has a resistor-capacitor (RC) and resistor-inductor (RL) combination - integrated with the TVS» EMI filter and TVS integrated circuit as a whole device setup, The improvement is that the EMI filter set with Tvs has better filtering performance. Typically, in low-pass filters, the attenuation of ceUular band signals in the 800MHz to 3GHz range can be at least 35dB. In addition, such devices have low parasitic resistance, capacitance, and inductance. In the (10) 丨 filter set up with TVS as shown in Figures 1A and 1B, the capacitance required for the EM I filter is usually passed through the chopper. The voltage regulator diode is provided to provide, and the Zener diode has an inherent junction capacitance. Therefore, the diode junction capacitance used in the regulated diode of the TVS can also be used as the EM I filter capacitor. However, the junction capacitance of the regulated regulator is also a function of the bias voltage. To achieve the design intent of the EMI filter as shown in Figures 1A and 1B, the bias of the symmetric filter is zero volts, and the offset of the asymmetric filter is V c c / 2 ' where v c c is the supply voltage. However, the capacitance may change with the bias voltage, which causes the chopper's cutoff frequency to vary with the DC bias, resulting in unreliable filtering performance. Figure 1C and Figure 1D show the magnitude of the change in capacitance in a symmetric and asymmetric filter with wafer level package (CSP) and double-column flat no form number A0101 Page 6 of 32 Page 1379419 1 October 2012 On the 5th, the relationship between the DC bias voltages of the DFN (Dual Flat No Lead) package was corrected. When the symmetrical module structure is set together with the symmetrical EMI filter as shown in Figure 1A, in addition to being sensitive to changes in capacitance dependent on DC bias, the junction capacitance of the diode is also for environments such as light and hum. The situation is very sensitive, so set the regulator diode to use a floating connection. When EMI and TVS-integrated devices are packaged in a chip-level package (CSP), the integrated EMI-TVS is required to have a higher capacitance tolerance of approximately 20% to maintain it in environmental conditions such as light. Reliable filterability • Energy. Therefore, there is still a need to provide a new and optimized circuit structure and manufacturing method to solve the above-mentioned difficulties in the field of circuit design and device manufacturing. In particular, the need to provide new optimized EMI filters in combination with TVS to provide linear, controllable capacitance still allows for the limitations and difficulties that can be addressed. • [0003] One aspect of the present invention provides a filter circuit provided with RC and/or LC, such as a TVS protection circuit integrated with an EM I filter. The filter circuit provides a flexible capacitor value by providing a new optimized insulating layer with an adjustable thickness of nitride and oxide layers to form the required filter capacitor value without increasing the wafer connection area and increasing oxidation. Material thickness. Thus, the technical difficulties faced by the above conventional filter circuits can be solved. Another aspect of the present invention provides a TVS protection circuit integrated with an EM I filter, which provides the above-described form number by providing an optimized device structure such that the total capacitance value between the input terminal and the ground terminal is substantially constant. A0101 Page 7 of 32 Page 1379419 12012 1! The limitations and difficulties faced by the prior art of March 5 were resolved. In particular, the TVS lightning path of the invention, the scoop 扛 疋 I 疋 forms a TVb circuit integrated with an EMI filter, including at least one input and ground of the stomach and several capacitors in parallel with the ground In between, where: the electrical offset is loaded at the input to maintain a fixed value. The total capacitance value of each of the present invention is generally another aspect of the present invention in a TVS circuit of a semi-EMI filter, which is turned on and integrated into a semiconducting substrate (4); Material and wide function 'same use-species gasification (S1N) (four) sunset stone octagonal pole groove, and ❹n# 3 4, '邑 edge layer and - type oxide (Si〇2) insulation layer Fill the 'make and ^ u Λ 0 2 s (metal oxide semiconductor) capacitor function' its * gate connection threat... The number of MOS capacitors to the turn-in end is substantially equal to the gate connected to the ground terminal 篁I贞The number of MOS capacitors between turns, so that when different biases are carried between the input and ground, the total capacitance value remains substantially a fixed value. Similarly, two doped regions are formed on the output side of the device with doped regions, having the function of a voltage stabilizing diode. Two sets of trenches filled with insulating material and multiple (four) gates are filled with a nitride (Sl 4 ) insulating layer and an oxide (Si 〇 2 ) insulating layer, the trench being opened in the doping As a function of the M0S capacitor, the number of M〇s capacitors at the gate connection output is substantially equal to the number of MOS capacitors connected to the ground terminal, so that when different bias voltages are loaded at the output terminal and the ground terminal In the meantime, the total capacitance value substantially maintains a fixed value. A preferred embodiment of the present invention generally discloses a transient suppression diode (TVS) circuit using an integrated electromagnetic interference (EMI) data filter into form number A0101. Page 8 of 32 | October 5, 2012 Amendment to electronic devices protected by Minhang. The TVS circuit integrated with the EMI filter further includes at least one voltage stabilizing diode and a plurality of capacitors connected in parallel between the input end and the ground end, when different voltage offsets are loaded at the input end and the ground end, wherein The total capacitance value of the capacitor is substantially maintained at a fixed value. In a typical embodiment, the EMI filter further includes a symmetrical filter having the same number of capacitors connected to the input terminal. In a particular exemplary embodiment, a TVS integrated with an EMI filter is supported by a semiconductor substrate, and a plurality of capacitors include a plurality of shallow trenches formed on the semiconductor substrate, said shallow trenches being filled with an insulator material, It is filled with a nitride (Si N ) insulating layer 〇 4 oxide (S1 〇 2 ) insulating layer. In another exemplary embodiment, a TVS integrated with an EMI filter is supported by a semiconductor substrate, and the EMI filter further includes a symmetrical wave filter having the same number of capacitances as the shallow trenches formed on the semiconductor substrate. The shallow trench is filled with a nitride (w) insulating layer and an oxide (train 2) insulating layer, and is connected between the input terminal and the ground terminal. In another exemplary embodiment, the TVS integrated with the EMI chopper is supported by a semiconductor substrate, wherein the input terminal is formed on the first doped region on the semiconductor substrate, and the ground terminal is formed on the semiconductor substrate. A doped region; the semiconductor substrate further includes an independent deep trench disposed between the first and second doped regions. In another exemplary embodiment, the TVS integrated with the EMI painter supports a first doped region formed on the semiconductor substrate by the semiconductor substrate having the first conductive form, and the ground terminal is formed. a second doped region on the semiconductor substrate, wherein the first and second doped regions are doped by a second conductive form, whereby the first and second regulated diodes can be formed in the second The first and second regions of the conductive form are interposed between the semiconductor substrate having the first type of 1379419 1 October 5, 2012 modified | conductive form. The present invention further discloses a transient suppression diode (TVS) circuit integrated with an electromagnetic interference (EMI) filter supported by a semiconductor substrate having a first conductive form. In the case of a symmetrical module structure, the TVS circuit integrated with the EMI filter includes a ground terminal disposed on the bottom surface and input and output terminals disposed on the top surface, and the semiconductor substrate is provided with at least one voltage stabilizing diode Body and several capacitors, using direct capacitive coupling, without the need to intervene in the floating region to couple the ground to the input and output. In an exemplary embodiment, the TVS circuit integrated with the EMI filter further includes two laterally separated doped regions of the first conductive form disposed in the second conductive type of material to form a doped region. Two-way modular regulator diode. The connected first doped region forms an input and the connected second doped region forms a ground terminal. In addition, a first group of trenches filled with an insulating material and a polysilicon gate and filled with a nitrided (Si3N4) insulating layer and an oxidized (Si2) insulating layer are disposed in the first doped region, and the polysilicon gate is connected to the ground. . This creates a first set of MOS capacitors between the input and ground. Similarly, a second set of trenches filled with an insulating material and a polysilicon gate are disposed in the second doped region, and the polysilicon gate is connected to the input. This creates a second set of MOS capacitors between the input and ground that have opposite conductivities compared to the first set of trench MOS capacitors. Repeat the same design to form a Zener diode and MOS capacitor between the output and ground. The other two are disposed in a second conductive form of the material having a laterally separated doped region of the first conductive form to form a bidirectional module voltage stabilizing diode. The connected fourth doped region forms an output terminal, and the connected third doped region forms a ground terminal "additionally" filled with an insulating material and a polycrystalline porch. Form No. A0101 Page 10 of 32

|October 5, 2012 Revision I The third set of trenches, filled with a nitride (Si N ) insulating layer and an oxide Si 2 ) insulating layer, is placed in the third doped region, and the polysilicon gate is connected. Output. This creates a first set of valleys between the output and ground. Similarly, the fourth group of trenches filled with the insulating material and the polycrystalline silicon gate are filled with a nitride (si N ) insulating layer and an oxide S1 〇 2) insulating layer, and are disposed on the fourth doping. In the area, the polycrystalline shi gate is connected to the base end. This forms a second set of MOS capacitors between the output and ground that have opposite conductivity compared to the first set of trench MOS capacitors. The second and third doped regions are both grounded and shorted by metal. The above and other objects and modifications of the present invention will be apparent to those skilled in the <RTIgt; [Embodiment] Fig. 2 shows a symmetric EMI filter in combination with a TVS in the present invention. The symmetric EMI filter combined with the TVS is supported by a +^ substrate 110 having an N epitaxial layer 115, showing both the input side on the left and the output side on the right. The wheel-in side of the substrate is doped with a P-type dopant into a first body region 120-1 and a second body region 120_2. A Zener diode is formed between the first dopant region 12〇1 and the N epitaxial layer 115. Another Zener diode 122-2 is formed between the second dopant region 12?_2 and the epitaxial layer 115. The formed first body region has a first connection doping region 125-1 and a second connection doping region 125_2 for electrically connecting the electrodes 13〇1 and 130-2 to receive an input voltage therein. The first body region also has a plurality of shallow trenches 135_1, 1 3 5 - 2 and 135-3 filled with an insulating material and a polysilicon gate, which acts as an M〇s capacitor. Trench capacitance, 135_2 1379419

12012, January 5, 倐I and 135-3 are electrically connected to the ground, and the electrical connection is connected to the contact metal 145 disposed on the top surface of the substrate through the metal contacts 140-1 to 140-3. And the contact metal is then connected to the ground to complete. The formed second body region 120-2 also has a first connection doping region 12 5G-1 and a second connection doping region 125G-2 for electrically connecting the electrodes 130G-1 and 1 3 0G-2 to connect the ground voltage. . The second body region 120-2 also has a plurality of shallow trenches 135'-1 to 135'-3 filled with an insulating material and a polysilicon gate, which function as a MOS capacitor. The trench capacitors 135'-1 to 135'-3 are connected to the contact metal 145 provided on the surface of the top layer of the substrate through the metal contacts 140'-1 to 140'-3, respectively, so as to be electrically connected to the input terminal. Two separate deep trenches 150-1 and 150-2 are disposed between the first and second body regions 120-1 and 120-2. Deep trenches 150-1 and 150-2 are used for isolation purposes. The device structure has a lateral parasitic PNP transistor. The addition of deep trenches in the base region of the lateral pnp can significantly reduce the gain of the parasitic transistor, thereby removing any unwanted current paths. The output side of the substrate is also doped with a P-type dopant as a first body region 170-; [and a second body region 170-2. The formed first body region 170-1 has a first connection doping region 175-1 and a second connection doping region 175-2 for electrically connecting the electrodes 18G-1 and 180-2 to provide an output voltage. The voltage stabilizing diode 172 1 is formed between the first etched body regions 170 to 1 and the N - epitaxial layer 115. Another Zener diode 172-2 is formed between the second dopant region i7〇_2 and the N- epitaxial layer 115. The first body region also has a plurality of shallow trenches filled with an insulating material and a polysilicon gate. 185-1, 185-2, and 185-3, functioning as MOS capacitors. The trench capacitors are electrically connected to the ground via contact metal 195 disposed on the top surface of the substrate via metal contacts 190-1 through 190-3, respectively. The formed second body region 17〇_2 also has a form number A0101, page 12/32 pages, a brother-connected MU region 175G-1, and a correction on October 5, 2012 | two-connected doped region 175G -2 is used to electrically connect the electrode 180G'mG_2 to connect the grounding power |. The second body region 17G-2 also has a plurality of shallow trenches 185 1 to 185 -3' filled with an insulating material and a polycrystalline gate, which acts as an M 〇 s capacitor. The trench capacitors 185'-1 to 185, -3 are respectively connected through the metal contacts 19, 丨 to 丨 (4), -3 (4) are disposed on the top surface of the substrate, and then electrically connected to the output voltage. . The two grounding body regions 12〇_2 and 17〇_2 are short-circuited by the metal 200. The input and output terminals 13A and 18B are interconnected by a series resistor 205 which is formed by a polysilicon layer between the input and output terminals of the EMI_TVS device and acts as a filter resistor. Two independent deep trenches 150'-1 and 150, -2 are disposed between the first and second body regions 170-1 and 170-2. Deep trenches 150, _H〇15〇, _2 are used for isolation purposes. The device structure has a lateral parasitic pNp transistor. The addition of deep trenches in the base region of the lateral PNP can significantly reduce the gain of parasitic transistors, thereby removing any unwanted current paths. Figure 2A shows a detailed embodiment of the present invention, where _, M 〇 s capacitors, that is, shallow slots 135-1 to 135-3, 135, -1 to 135, -3, 185-1 to 185-3 And 185, -1 to 185, -3, filled with a polysilicon gate material 101 and a combined insulating layer comprising a nitride insulating layer 1〇2 and an oxide insulating layer 1〇3. The oxidized insulating layer 103 serves to release the film stress of the nitride layer on the surface of the crucible. Since the combined insulating layer including a nitride insulating layer 1 2 and an oxidized insulating layer, the capacitance value can be further increased without increasing the connection area. As shown in the table below, the tantalum nitride layer has a higher dielectric constant than the tantalum oxide layer. Therefore, M3N4 can provide a souther capacitance value with the same film thickness. 1379419 [0005]

Si〇2 Dielectric constant 3. 9 Dielectric strength 107 Nitride (Si3N4)

[2〇12,1〇月5曰修正I Ί. 10 Figure 2 shows the insulation layer that is composed of a combination of a nitrided insulation (Si3N4) layer and an oxidized insulation (Si〇2) layer. In the case where the overall thickness is constant, the capacitance value of the trench capacitor increases as the thickness of the nitride layer increases. Therefore, it is easy to adjust by adjusting the thickness of the nitride insulating layer while keeping the overall thickness of the combined insulating layer constant.

The capacitance value of the filter circuit. The flexibility and range of application of the filter circuit can be extended and optimized by adjusting the corresponding thickness of the nitride and oxide layers in such a tunable capacitor. Figure 3 is a diagram showing the change in capacitance with respect to voltage, that is, the C-V diagram of the M〇s capacitor. The Capacitance-Voltage (C-V) plot shown in Figure 3 is a typical C-V relationship for trench capacitors. Capacitance is formed between the trenches in the shallow trenches. Half of the trench capacitor has its gate connected to the input and the other half of the trench capacitor has its gate connected to ground. Thus, C1 represents half of the total capacitance connected between the input and ground, and C2 represents the other half of the total capacitance connected between the input and ground. The capacitance values C1 and C2 are changed as shown by the C-V curve, and each other is mirrored "the sum of the two capacitance values C1 and C2", that is, Ctotal = Cl + C2, which is maintained at a constant value regardless of the voltage change. The symmetry of the filtering operation is achieved by connecting half of the total number of trenches to the input and the remaining connected to the ground voltage. Figure 4 is a side cross-sectional view of the asymmetric EMI filter in combination with the Tvs circuit 2A in the optimized device structure of the present invention. Form No. A0101 combined with tVS circuit 2〇〇 Page 14 of 32 pages 1379419 1 October 5, 2012 Revision 丨 EMI filter supported by a semiconductor substrate 2〇1 'The semiconductor substrate 2〇1 has a connection to The bottom electrode 205 of the ground voltage. As shown in the figure, the EMI filter and TVS device 200 have an input side on the left and an output side on the right. On the input side, substrate 210 includes a plurality of trenches 207-1, 207-2, and 207_3 disposed on N- epitaxial layer 215 supported by N+ substrate 210. The trenches 207-1 to 207-3 with the epitaxial layer 215 are connected to the input voltage through the metal contacts 265-1 to 265-3 passing through the insulating layer 230. The regulated diode is implemented by using a vertical NPN transistor that is triggered by a laterally regulated diode. The NPN collector is implemented by an N+ doped layer 255 and the base is implemented by a p doped layer 240. The emitter is implemented by an N+ doped substrate 210. The triggering of the NPN is achieved by a lateral voltage stabilizing diode formed between the N + collector 255 and the P base 240. Surface doping of the P-type body region is adjusted by using separate shallow p-type implants to control the regulated breakdown voltage. The p-extreme of the laterally regulated diode is shorted to ground by a shallow P+ implant 245. Separating metal 225 is used to connect the shallow P+ implant to the substrate with a stone implant. On the output side, substrate 2 and through the N + doped layer 220 and the N- epitaxial layer will be shallow P +

The base is connected to the output power by the P-doped layers 240' 〜1 to 265' -3. The NPN collector triggered by the lateral voltage stabilizing diode is formed by the N + doped layer 255'. The emitter is formed by an N+ doped substrate 210. The triggering of the NPN is achieved by a laterally regulated diode formed between the collector milk and the p-base 240'. Surface doping of the p-type body region is adjusted by using a separate shallow P-type implant to control the voltage breakdown breakdown. Form No. A0101 Page 15 / Total 1379419 1 October 5, 2012 Correction pressure. The P-extreme of the laterally regulated diode is shorted to the ground via the shallow p+ implant region 245. A separate metal 225' is used to connect the shallow p+ implant and a shallow P+ implant is connected to the substrate via the N+ doped layer 220 and the N epitaxial layer, and the input and output terminals 250 and 250' are interconnected by a series resistor, The resistor is formed by a polysilicon layer between the input and output of the EMI-TVS device 200, acting as a filter resistor. Similarly, as shown in FIG. 2A, the trenches 207-1 to 207-3 and 207'-1 to 207'-3 functioning as MOS trench capacitors include a nitride insulating layer 102 and an oxidized insulating layer 1. The composite insulating layer of 〇3 is filled, which eliminates the need to increase the wafer size or increase the overall thickness of the insulating layer to increase the capacitance value. In the EMI-TVS integrated device, the input and output terminals 250 and 250' and the ground terminal 205 are directly capacitively coupled without the aid of a floating body therebetween. When the floating body is connected between the input and output terminals and the ground terminal, the value of the mesh capacitance between the two is the series capacitance value of the two contact capacitors, which is much smaller than the independent contact capacitance value. Therefore, the capacitance value needs to be Smaller area. Since direct capacitive coupling is used without the need for a floating substrate, it is not sensitive to changes in light or other environmental conditions. Since the symmetrical capacitance value acts as a positive and negative bias, the filter capacitor value is no longer dependent on the DC bias. Constant capacitance values offer special advancements in practical applications because devices with constant capacitance values can cover the full range of rated voltages of the device by varying the low frequency audio/data signals ranging from + Vcc to _Vcc. The high frequency RF signal filtered by this device will be above the peak of the low frequency signal. In contrast, if the change in the value of the filter capacitor is a function of the voltage, the change in filter benefit is also dependent on the voltage level of the low frequency audio/data signal. At the 〇 bias, the filter generates a height form number for the RF signal. A0101 Page 16 of 32 Page 1379419. 1 October 5, 2012 Correction 1 attenuation, but 'if its capacitance decreases with bias, its attenuation It will be greatly reduced at the +/-Vcc bias. This difficulty can be solved by providing an asymmetric EMI filter combined with the TVS circuit 200 of the present invention. • Figure 5 is a schematic diagram comparing the change in capacitance with DC bias. When the device is in the accumulation mode, the capacitance value is formed between the polysilicon trench and the 1^ epitaxial layer and the N + source region. The capacitance value does not change due to the voltage bias. The reason is that for all positive biases, the N epitaxial layer is in the accumulation mode, and the capacitance value from the gate to the substrate is the M〇s oxide capacitance value. . Although the present invention has been described in terms of the preferred embodiments thereof, it should be understood that such disclosure is not to be construed as limiting. Various changes and modifications will become apparent to those skilled in the <RTIgt; Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and modifications that fall within the true spirit and scope of the invention. • [0006] [Simple diagram of the diagram] Figures 1A and 1B are circuit diagrams of a TVS circuit incorporating an EM I filter. The 1C and 1D diagrams show the capacitance caused by the change in DC bias voltage. Changing chart. Fig. 2 is a side cross-sectional view showing a symmetrical dragon 1 filter incorporating a TVS circuit in the present invention. 2A is a cross-sectional view of an exemplary embodiment in which the formed MOS trench capacitor with a polysilicon filled trench is composed of a nitride (Si N 3 4 ) insulating layer and an oxide (Si 〇) insulating layer. Insulation layer form number A〇l〇l page / total 32 pages 1379419

12012, the first day of the month, the fifth is filled with I. Figure 2B shows the 'trench capacitance' in the case where the overall thickness of the insulating layer composed of a combination of a vaporized (si 3 N 4 ) insulating layer and an oxide (Si 2 ) insulating layer is maintained. The capacitance value increases as the thickness of the nitride layer increases. Fig. 3 is a diagram showing a function between a change in capacitance value and a bias voltage, which causes the total capacitance value to remain substantially constant due to the natural properties of the first and second capacitances provided by the EM I - TVS device of the present invention. Fig. 4 is a side cross-sectional view showing an asymmetric em I ferrite combined with a TVS circuit in the present invention. ® Figure 5 is a plot of the capacitance of the EM I -TVS device in Figure 4 versus DC bias. [Main element symbol description] [0007] 101 polycrystalline germanium gate material 102 nitride insulating layer 103 oxide insulating layer 110 N + basic · 115, 215 N epitaxial layer 120-1, 170-1 first doped region 120- 2, 170-2 The first hand holding region 122-1, 122-2, 172-1, the voltage stabilizing diode 172-2 125-1, 125G-1, 175-1, the first connection doping region 175G -1 125-2, 125G-2, 175-2, second connection doped region 175G-2 Form No. A0101 Page 18 of 32

1379419 . 1 October 5, 2012 Amendment I 130, 250 Input 130-Bu 130-2, 130G-1, Electrical connection electrode 130G-2, 180-1, 180-2, 180G-1 '180G-2 135 small 135-2, 135-3, 135 shallow groove, trench capacitor '-1, 135'-2, 135'-3, 185-1, 185-2, 185-3, 185 '-1, 185' -2 , 185' -3 140-b 140-2, 140-3, 140 metal contacts '-1, 140'-3, 190-1, 190-2, 190-3, 190, -1, 190'-2 , 190, -3, 265-1, 265-2, 265-3, 265' -1, 265, -2, 265, -3 145, 145, 195 Contact metal 150 small 150-2, 150' - 1. Deep trench 150, -2 180, 250' output 195, connection metal 200 metal, TVS circuit, TVS device 205 resistor, bottom electrode, ground terminal 210 substrate 220 N + doped layer 225, 225, separation metal 230 , 230, Insulation 240, 240' P-doped layer, P-base form number A0101 Page 19 / Total 32 pages 1379419 10 October 5, 2012 Amendment 丨245, 245' Shallow P + implant 255, 255' N + doped layer, N + collector

Form No. A0101 Page 20 of 32

Claims (1)

1379419 . 1 October 5, 2012 Revision VII, 1 'Scope of application: An electronic device protected by a bidirectional symmetric modular transient suppression diode circuit integrated with an EMI filter, where: The transient suppression diode of the electromagnetic interference filter further includes at least one voltage stabilizing diode and a plurality of capacitors connected in parallel between the input terminal and the ground terminal, wherein when the input terminal and the grounding The total capacitance between the input terminal and the ground terminal is substantially at a constant value when a reverse bias is applied between the terminals; and • the transient suppression diode integrated with the electromagnetic interference filter Supported by a semiconductor substrate, the plurality of capacitors comprise a plurality of shallow trenches filled with an insulating material formed on the semiconductor substrate, and the shallow trenches comprise a nitride insulating layer and an oxide insulating layer The combined insulating layer is composed for filling. The electronic device of claim 1, wherein: the electromagnetic interference filter further comprises a symmetric filter, in the symmetric filter, connecting the input terminal and connecting the The number of capacitors at the ground is the same. The electronic device according to claim 1, wherein the electromagnetic interference filter further comprises a symmetric filter having the same number of shallow grooves formed on the semiconductor substrate, wherein the shallow groove is The combined insulating layer comprising a vapor-gas insulating layer and an oxide insulating layer is filled with a lamp which functions as a capacitance connected between the input terminal and the ground terminal. The electronic device according to claim 1, wherein the transient suppression triode integrated with the electromagnetic dry (four) wave is composed of half of the form number A0101 page 21 / total 32 pages _ 1__ year On October 5, the v-substrate domain is repaired, and the input (four) is pure to the first doped region on the -1 bulk substrate. The ground terminal is formed on the semiconductor substrate. a second doped region; and the semiconductive substrate further comprises a separate deep trench disposed between the first and second doped regions. The electronic device of claim 1, wherein the transient suppression diode integrated with an electromagnetic interference filter is supported by a semiconductor substrate having a first conductive form, the input The terminal is formed in a first dummy region on the semiconductor substrate, the ground terminal is formed in a second dummy region on the semiconductor substrate, wherein the first and second doped regions are second a conductive form, whereby the first and second voltage stabilizing diodes can be formed in the first and second doped regions having the second conductive form and having the first conductive form Between the semiconductor substrates. A transient suppression integrated with an electromagnetic interference filter: a polar body circuit supported by a semiconductor substrate having a first conductive form, the transient suppression diode circuit further comprising: having a second conductive form The first and second doped regions cooperate with the semiconductor substrate having the first conductive form to form the first and second voltage stabilizing diodes, and the first and second groups have the same number of openings a shallow trench filled by the insulating material and the semiconductor thumb electrode on the first and second doped regions, thereby serving as a metal oxide semiconductor capacitor, the metal oxide semiconductor capacitor comprising a nitride insulating layer and The combined insulating layer of the vaporized insulating layer is filled. 7. The transient suppression diode integrated with the electromagnetic interference chopper according to claim 6 of the patent application further includes: Form No. AG1G1 I 22 I / # 32 I 10 11 12 Form No. A0101 is set in the above - an independent deep trench between the second and the second mixed area = . The transient suppression diode integrated with the electromagnetic dry (four) waver described in claim 6 further includes: a wheeled end of the metal contact, A first metal contact electrically connects the first: field to a wheeling voltage, and a ground end comprising a second metal contact electrically connects the second doped region to a ground voltage. • The transient suppression diode integrated with the electromagnetic interference ship described in the sixth paragraph of the patent specification (4) further includes: “the third and fourth doped regions having the first conductive form and the first type The conductive semiconductor substrates cooperate to form third and fourth voltage stabilizing bodies, and the third and fourth groups have the same number of insulating materials and the first and second doped regions: The semiconductor gate, the shallow trench &amp; includes a combined insulating layer of a nitrided insulating layer and an oxidized insulating layer for filling the material as a junction capacitance. σ fly; to the integrated patent electromagnetic interference according to item 9 of the patent The transient suppression diode of the 遽, the waver further comprises: an independent deep trench disposed between the first and second doped regions. 2 The integrated electromagnetic interference data device according to the scope of claim 9 The transient suppression diode further includes: - an output including a third metal contact, the third metal contact electrically connecting the first domain to an output voltage, and a germanium contact including the fourth metal contact Four holdings of the electrical area are electrically connected to the grounding ', medium, said A fourth doped region is disposed beside the second doped region. ', a one-way modular transient suppression diode integrated with an electromagnetic interference slot device. Page 23 / Total 32 pages 1379419 12012 10 The fifth modification. The circuit is supported by a semiconductor substrate having a first conductive form, the one-way modular transient suppression diode circuit further comprising: a ground terminal disposed at the bottom of the semiconductor substrate and setting At the input and output ends of the top surface, at least one voltage stabilizing diode and a plurality of capacitors are disposed on the semiconductor substrate, and the direct current coupling is used, and the grounding end and the input end and the output end are not required to be used in the method of interposing the floating body region. Coupling; and a first set of shallow trenches, each filled with an insulating layer comprising a combination of a nitride insulating layer and an oxidized insulating layer, filled with an insulating material and a polysilicon gate, and connected to the input a metal oxide semiconductor capacitor is formed between the input terminal and the ground terminal. 13. The transient suppression diode integrated with the electromagnetic interference filter according to claim 12 The body further includes: a voltage stabilizing diode connected in parallel between the input and the ground, as a vertical NPN transistor triggered by the lateral diode, the body region of the NPN transistor also acts as an electrode of the lateral diode, passing through The separated metal contact is connected to the substrate 14. The transient suppression diode integrated with the electromagnetic interference filter according to claim 12 further includes: a second group of shallow grooves, each of which comprises one A combination insulating layer of a nitride insulating layer and an oxide insulating layer is filled, further filled with an insulating material and a polysilicon gate, and connected to the output end, thereby forming a metal oxide between the output end and the ground end The semiconductor capacitor 15. The transient suppression diode integrated with the electromagnetic interference filter according to claim 14 further includes: a voltage stabilizing diode connected in parallel between the output terminal and the ground terminal as a form No. A0101 Page 24 of 32 1379419 1 October 5, 2012 Revision I Vertical NPN transistor triggered by a lateral diode, the body region of the NPN transistor also acts as an electrode of the lateral diode, passing through the separation gold Contact to the substrate. 16 A method of protecting an electronic device by a transient suppression diode circuit integrated with an electromagnetic interference filter, comprising: by connecting at least one voltage stabilizing diode in parallel with a plurality of capacitors between the input terminal and the ground terminal Integrating a transient suppression diode having the electromagnetic interference filter, and simultaneously, when a reverse bias is applied between the input terminal and the ground terminal, the input terminal and the ground terminal The total capacitance value is substantially at a constant value; and the plurality of capacitors are formed on the semiconductor substrate by opening a plurality of shallow trenches on the semiconductor substrate, in each of the shallow trenches The shallow trench sidewall is first filled with a combined insulating layer comprising a nitride insulating layer and an oxide insulating layer, and the shallow trench is filled with an insulating material. 17. The method of claim 16, wherein: the step of integrating the transient suppression diode with the electromagnetic interference filter further comprises the steps of: A method of respectively connecting the same number of capacitors to the input terminal and the output terminal to integrate a symmetric electromagnetic interference filter and a wave filter. The method of claim 16, wherein: the step of integrating the transient suppression diode with the electromagnetic interference filter further comprises the step of: passing on the semiconductor substrate a plurality of shallow trenches are formed to form the plurality of capacitors on the semiconductor substrate, and then a trench of each of the trenches is filled with a combined insulating layer comprising a nitride insulating layer and an oxide insulating layer The side wall of the groove is filled with the insulating material, and the same number of functions are respectively connected to the electric form number A0101. Page 25/32 pages 1379419 12012 ίο月5日 Revision I is opened on the semiconductor substrate A shallow trench is applied to the input terminal and the output terminal to form a symmetric electromagnetic interference filter coupled to the transient suppression diode. 19. The method of claim 16, further comprising: forming a first doped region on the semiconductor substrate for connecting the input terminal, and forming on the semiconductor substrate A second doped region is used to connect the ground terminal, and a separate deep trench in the semiconductor substrate is formed between the first and second doped regions. The method of claim 16, wherein: the step of φ the parallel voltage stabilizing diode and the plurality of capacitors further comprises the step of: forming in a semiconductor substrate having the first conductive form; a step of having first and second doped regions in a second conductive form, whereby two stabilizing polar bodies are formed between the first and second doped regions and the semiconductor substrate And opening a plurality of shallow trenches, then filling the trench sidewalls of each of the trenches with a combined insulating layer comprising a nitride edge layer and an oxide insulating layer, and filling the trenches with an insulating material, thereby A plurality of junction capacitances are formed in the first and second doped regions, and the first and second impurity-changing regions are further connected to the input terminal and the ground terminal, respectively. The method of claim 20, wherein: the method of f &amp; second doped region-like plurality of trenches further comprises the step of: opening the same number in the semi-hetero-region Ditch _ _ and the first - doping ...,, χ, ^ #槽, ,, when the reverse constant β value is set between the input and the grounded ground is substantially at - page 26 / form The method of claim 16, wherein the method of claim 16 further comprises: • forming a second on the semiconductor substrate having the first conductive form Third and fourth doped regions in a conductive form, whereby third and fourth stabilizing diodes are formed between the third and fourth doped regions and the semiconductor substrate, and Opening a plurality of shallow trenches, then filling a trench sidewall of each of the trenches with a combined insulating layer comprising a nitride insulating layer and an oxide insulating layer, and filling the trenches with an insulating material, thereby Forming a plurality of junction capacitances in the third and fourth doped regions, further The first and second doped regions are respectively connected to the output end and the ground end 23. The method of claim 22, wherein: a plurality of the third and fourth doped regions are opened The method of trenching further includes the steps of: opening the same number of trenches in the third and fourth doped regions on the semiconductor substrate, such that when disposed between the output terminal and the ground terminal When reverse biased, the total capacitance value is essentially at a constant value. Form No. A0101 Page 27 of 32