TWI379277B - - Google Patents

Description

IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a source drive to drive a bias current of a regulator, while at the same time achieving a miscellaneous drive device with a lower turn-off and power reduction. -Pre-voltage level [Prior Art] y-phase liquid crystal displays are widely used in various applications...for example, personal digital assistants and mobile phones. However, with the development of the product, the size of the liquid crystal display is larger, and the battery (4) is long. It is extra important. Power consumption φ 4® 重 The low power of handheld electronic products means longer battery life, as long as the power consumption of the internal parts of the handheld electronic products can be extended, the battery life can be extended directly and effectively. There are mainly two kinds of driving components on the driving device of the display, which are a source driver (S〇urce Driver) for driving the horizontal axis and a gate driver (Gate Driver) for the vertical axis. In today's thin film transistor liquid crystal display (TFT-LCD) manufacturing technology, the trend toward higher resolution and larger size is also more detailed and complicated in component construction. In addition to the horizontally and vertically arranged signal lines (the display panel) In addition to the Data Line) and the Gate Line, components such as thin-film transistors (TFTs) and common lines (Common Line), which are complex in structure, are single-chip liquid crystal drivers that are common in handheld electronic products. Its power consumption occupies an important proportion in handheld electronic products. Manufacturers of hand-held electronic products are all committed to reducing the power consumption of this single crystal 1379277 liquid crystal driver, and analyzing the power consumption of the conventional liquid crystal driver's power consumption of the source driver is more than 50%. Please refer to "1" and "2". In the conventional liquid crystal driver and its driving method, 'the liquid crystal driver 10 outputs an accurate analogy for a gate time Tgate (time of the gate line). The gamma voltage level provides a sufficient and fixed bias current Isource_bias of the source driver 11 to cause the voltage of the source channel loading 22 on the signal line 21 of the liquid crystal display panel 20 to be £V. )urce_cham^, can be quickly climbed or dropped to the specified gamma voltage level, assuming that the time required for this climb or fall is Trf source. Moreover, sufficient reaction time is reserved in the gate time Tgate for the TFT cell loading 23' so that the voltage level VTFT of the storage capacitor CTFT in the thin film transistor unit load 23 rises or falls. To the specified gamma voltage level, assume that the time required for this climb or fall is Trf TFT. Therefore, we can list its private type. Tgate — Trf_source + Trf_TFT 0 It is known to output an accurate analog gamma voltage® level within a gate time Tgate for the function of the source driver 11, but with the liquid crystal display panel An increase in size of 20 will shorten the gate time Tgate. Therefore, the source driver 11 needs to increase the current driving capability of its output to comply with the shortened gate time Tgate. Conventionally, increasing the bias current IsQurcebias of the source driver U can effectively and directly increase the current driving capability of its output, but increasing the bias current Isource bias of the source driver 11 will drastically increase the power consumption of the liquid crystal driver 10. In summary, the conventional driving device and method have the following disadvantages: 6 1379277 1. The voltage level Vtft of the storage capacitor CTFT retained in the semiconductor transistor load 23 of the thin film transistor is up or down to a specified gamma. The time Trf tfT of the voltage level of the voltage is still given to the source driver 11 in the same bias current IS〇Urce_biaS in the Trf_source time. However, at this time, the voltage vscmrcechannel of the source channel load 22 of the liquid crystal display panel .20 has reached the specified gamma voltage level, for example, 99% of vgamma. Therefore, at this time, the source driver 11 still inputs a fixed bias current IS() Ulxe_bias, which will only cause power consumption. 2. When the voltage of the source channel climbs or falls to the specified gamma voltage level, the time Trf_source 5 gives the source driver 11 a fixed bias current Isource_bias 'see Figure 2, but only in the first 1/ 4 Trf_sourc time 'source channel load 22 voltage vscurce_channel only has a sharp transient change' remaining Trf_S () urc and Trf TFT time, input fixed bias current Isource a bias, will only cause power consumption. SUMMARY OF THE INVENTION Therefore, in order to solve the above-mentioned deficiency and avoid the existence of a defect, the main object of the present invention is to achieve the output of the gamma voltage level and also reduce the power dissipation of the Lu liquid crystal driver. Based on the above reasons, the present invention proposes a low-rate source driver technique for a liquid crystal driver that adjusts the bias voltage of the source driver in a stepwise manner while achieving a reduction in output and power consumption of the gamma voltage level. And as the number of bias current segments of the source driver increases, the power consumption can be further reduced. The invention relates to a low-power source driving device, which is applied to a liquid crystal driver for driving a liquid channel load on a signal line of a display panel and a semiconductor load of a 7 1379277 thin film transistor. The source driving device includes: The sequence control digital circuit is configured to generate different digital signal combinations according to the load requirement of the liquid crystal display panel during a gate time, and the digital signal combinations have only one digital signal logic level at the same time. 1; and a dynamic. The adjusted source driver bias circuit generates different analog level bias currents according to the combination of the digital signals described above; and a plurality of source drivers that utilize the aforementioned bias currents to generate corresponding The output drive capability allows the load on the LCD panel to climb or fall to a specified gamma voltage level during a gate time. Wherein the digital signal combination is at least a combination of two digital signals; and the dynamically adjusted source driver bias circuit generates a bias current of at least two analog levels according to the combination of the digital signals, at each gate time The beginning of the normal bias current is generated, so that the source drivers generate sufficient driving capability to cause the load voltage of the liquid crystal display panel to climb or fall to a specified gamma voltage level, and generate at least one of the remaining gate time. The lower bias current allows the source drivers to produce stable drive capability. The closer to the end of each gate time, the smaller the bias current generated by the dynamically adjusted source driver bias circuit. Another embodiment of the present invention replaces the source drivers by a combination of a plurality of gamma drivers and a plurality of digital analog converters. The number of the gamma drivers is the same as the number of gray levels to be presented by the liquid crystal display panel. The aforementioned bias currents respectively generate gray scale voltages to be presented, and the digital analog converters output desired gray scale voltages to the source channel loads, so that the load of the liquid crystal display panel can be in a gate time Climb or lower 1379277 to the specified gamma voltage level. The gamma drivers are further composed of a plurality of gamma pre-drivers and resistors located between each of the gamma pre-drivers, and respectively use the aforementioned bias currents to separately generate the gray scale voltages to be presented. The invention has the advantages that the bias current of the source driver can be adjusted stepwise in a gate line time time, and the output of the gamma voltage level and the power consumption are reduced, and the source driver can be reduced by about 20 by using the invention. % power consumption. And as the number of bias current segments increases, its φ power consumption can be further reduced. The embodiments and the technical description of the present invention are further described in the following examples, but it should be understood that the embodiments are merely illustrative and should not be construed as being The limit. As shown in FIG. 3, the present invention is a low power source driving device applied to a liquid crystal driver 100 for driving a source channel load 220 and a thin film transistor unit load 230 on a signal line 210 of a liquid crystal display panel 200. The driving device includes: a timing control digit circuit 120 for generating different digital signal combinations ΑΡ0~APX according to the load requirement of the liquid crystal display panel 200 during a gate time Tgate, and the digital signal combination ΑΡ0~APX have only one digital signal with a logic level of 1 at the same time. The dynamically adjusted source driver bias circuit 130 generates different analog level bias current Is 〇urce_bias according to the foregoing digital signal combinations ΑΡ0~APX; when the logic level of the digital signal ΑΡ0 is 1, the representative selects The dynamically adjusted source driver bias circuit 130 has the highest bias current i 9 1379277 IS〇Urce_biaS; when the logic level of the digital signal APX is 1, it represents the lowest bias of the dynamically adjusted source driver bias circuit 130. Current. And a plurality of source drivers 110, which use the aforementioned bias current Isource bias to control the source voltage levels Vsource "eve" input by the source drivers 110 to generate corresponding output driving capabilities, so that the source of the liquid crystal display panel 200 The channel load 220 and the thin film transistor unit load 230 can climb or fall to a beat gamma voltage level within a gate time Tgate. In addition, in order to cope with the description of the present invention, the equivalent source channel resistances Rsource_channel_l~Rsource_channel_N of the source channel load 220 of the liquid crystal display panel 200 are connected to the output terminals of the source drivers 110, and the equivalent source channel valleys CS0Urce_chamiel_l~CSOUrce_channel_N' and The equivalent monomer resistance of the thin film transistor unit load 230 RTFT_i~RTFT N and the equivalent storage capacitor c TFT_ 1 to CtfT_N ° The digital signal combination ΑΡ0~APX of the present invention is at least a combination of two digit signals; and the dynamic adjustment The source driver bias circuit 130 generates at least two analog-level biased Lu currents Isource_bias according to the digital signal combinations 〜0~APX to generate a normal bias current Is〇urce_bias at the beginning of each gate time Tgate, The source driving IS 11 〇 generates sufficient driving capability to cause the voltage VSOUrce_channel of the source channel load 220 of the liquid crystal display panel 200 to climb or fall to the gamma voltage level of the fingerprint, and the remaining gate time Tgate ' Producing at least a lower bias current Is (wee bias) to stabilize the source drivers 110 The driving ability. The closer to the end of each gate time Tgate, the bias current IS generated by the dynamically adjusted source driver bias circuit 130 (nm:e bias is smaller. 1379277 See "Fig. 4" According to a first embodiment of the present invention,

The timing control digital circuit 120 is used to force PB to call the voltage drop 1 for a combination of APO AP1 and a digital signal within a gate time Tgate. In the present embodiment, in the inter-strip line time Tgate, the bias currents 1: U^e_bias of the source drives B 110 are divided into two segments, respectively, which are the L-line 210 of the liquid crystal display panel 2 The voltage VS〇Urce_channel of the source channel load 22〇 can quickly climb or not drop to the specified gamma voltage level Trf source, and the storage capacitor CTFT within 23 负载 of the thin film transistor load The voltage level vTFT is the time Trf TFT required to climb or fall to the specified gamma voltage level. During the Trf source time, the timing control digital circuit 120 causes the logic level of the digital signal ΑΡ0 to 1' to cause the dynamically adjusted source driver bias circuit 13 to generate a higher bias current Isource_bias (IAP()). Therefore, the source driver 110 is caused to generate sufficient driving capability to cause the voltage Vsc)ujxe_channei of the source channel load 20 of the liquid crystal display panel 200 to climb or fall to a specified gamma voltage level 'such as 99% of the gamma voltage level. During the remaining Trf_TFT time, the timing control digital circuit 120 sets the logic level of the digital signal API to 1, causing the dynamically adjusted source driver bias circuit 130 to generate a lower bias current IS()urce_bias(IAP1), The source driver 110 is thus caused to have a stable driving capability to cause the voltage level VTFT of the thin film transistor unit load 230 to climb or fall to a specified gamma voltage level, such as a 99% gamma voltage level. The source channel load 220 and the voltage of the thin film transistor storage unit load 230 are Vsource_channe and VtFT, and the bias voltage of the source driver 11 is 11 1379277 2r: bias6 is shown in FIG. 5, this embodiment The power consumption (or average current) of the 11G is equal to the power consumption (or average current) P〇 of the conventional source: P1/P0= GapoxTV— + lAp丨χΤ(τρτ )/( Αρ〇χ & 1. For example, if Rs〇urce channei is 8K〇hm, q. - calendar, 2PF, RTFT is 15MOhm, Ctft is 〇5pF, a closed line time is '50uS, and the source voltage is made by 〇5V rises to 4 5v, you can get iAp〇

77.1 nA 'Trf source is 27.2uS, I AP1 is 48·7ηΑ, and Trf-TFT is 22.8uS'. From the above formula, Pl/PO = 83.2% can be obtained. Referring to Fig. 6, in accordance with a second embodiment of the present invention, the timing control digital circuit 120 is operative to generate a combination of AP0~AP2 binary signals during a gate time. In the present embodiment, during a gate time Tgate, the bias current .channel of the source drivers 110 is climbed or dropped to a specified gamma voltage level.

Lun^bias is divided into three segments, which is divided into (3/5)xTrf sourc^(2/5)xTrf source, and the monolithic transistor is loaded with the voltage Vf between the source channel and the voltage Trf_s〇urce. The voltage level of the storage capacitor cTFT in 230 is the time Trf TFT required for the VTFT to rise or fall to the specified gamma voltage level. During the (3/5) xTrf source time, the timing control digital circuit 120 sets the logic level of the digital signal ΑΡ0 to 1 to cause the dynamically adjusted source driver bias circuit 130 to generate a higher partial current. _bias(lAP0), thus causing the source driver 11 to generate sufficient driving capability to cause the battery channel load 220 of the liquid crystal display panel 200 to climb or fall to the gamma voltage level of the ,, such as 12 1379277 81.2 % gamma voltage level. During the (2/5)xTrf source time, the sequence control digital circuit 120 causes the logic level of the digital signal API to be 1, so that the dynamically adjusted source driver bias circuit 130 generates the second highest bias current Isource. -bias(lAPl) 'The voltage VSQUrce_channel of the source channel load 220 of the liquid crystal display panel 200 is raised or lowered to a specified gamma voltage level, such as a 99% gamma voltage level. During the remaining Trf TFT time, the timing control digital circuit 12 causes the logic level of the digital signal AP2 to be 1 to cause the dynamically adjusted source driver bias circuit 13 to generate a lower bias current, thereby The source driver 110 produces a stable drive capability to cause the voltage level VTFT of the thin film transistor unit load 230 to climb or fall to a specified gamma voltage level, such as a 99% gamma voltage level. The waveforms of the voltages of the source channel load 220 and the thin film transistor storage unit load VSV()Uree_ehaiiTiel and VTFT' and the bias current IS〇UrCe_biaS of the source driver 11〇 are as shown in FIG. 7 , this embodiment The power consumption (or average current) P2 of the source driver 110 is approximately the same as the power consumption (or average current) p〇 of the conventional source driver 11: p2/p〇= (lAP〇x(3/5 ) xTrf source+iAplx(2/5)xTrf source+ IAP2xTrf_TFT ) /(I apox Tgate). For example, 'If Rs. (4) _channeI is 8K 〇hm, Cs〇uree ch is 2 for 2pF RTFT is i5MOhm, CTFT is 〇.5pF, and one gate time is 〇uS, and the source voltage is climbed from 〇.5V to 4.5V. lAp(^ 77.1 nA ' Trf source is 27.2iiS ' I AP1 is 57.3nA, I AP2 is 48.8nA 'Trf TFT is 22.8uS'. From the above formula, P2//p〇=77 9 13 1379277

= In this type of push-to-gate time U, the present invention can be used to divide the source driver 11 偏压 bias to produce a bit-source source-bias into a plurality of segments (as in "Figure"). At the gate line time τ (four), the starting digit circuit 120 causes the digital signal to be tempered, and the logic level of β is made to cause the dynamically adjusted source driver bias circuit 13U to be relatively defective. The bias current Isource is biased to enable the source driver 11 to generate sufficient driving capability to cause the liquid crystal display panel 22 to have a source channel load of 22 〇.

^ v source_channel swells or drops to the specified gamma voltage level. At the end of the -gate time, the timing control digital circuit 12 causes the logic level of the digital signal to be 1 so that the dynamically adjusted source driver bias circuit produces the lowest bias current Is 〇urce The bias, thus causing the source driver to produce a stable drive capability, causes the voltage level VTFT of the thin film transistor unit load 230 to climb or fall to a specified gamma voltage level. The above implementation architecture has a respective source driver 110 for each source channel, and another embodiment of the present invention may be analogous to a plurality of gamma drivers and a plurality of digital analogs without departing from the spirit and scope of the present invention. The converter combination replaces the source drivers 110. As in the third embodiment of the present invention, unlike the foregoing embodiments, each source channel does not have a respective source driver 110 in such a manner that each source channel of the same gray level is driven by the same source driver, such a source. The drive we call a gamma drive. Referring to FIG. 8 , the present embodiment is applied to a driving device for driving a source pass 1379277 load 420 and a thin film transistor unit load 430 on a signal line 410 of the liquid crystal display panel 400. The method includes: the timing control digital circuit 320 and the dynamically adjusted source driver bias_circuit 330, and a plurality of gamma drivers 310, the number of the gamma drivers 310 being the same as the gray level to be presented, for example, a gray There are M gamma drivers 310, which are controlled by the front bias voltage Xml Isource_bias, so that the corresponding input gamma voltage levels Vgamma"evel_l~Vgamma"evei_M correspond to the output gray 13⁄4 Voltages G1 to GN1. The gray scale voltages G1 GM GM, and then a plurality of digital analog converters 340 as the source drivers, according to the digital selection data (GS 〇〇 ~ GSQY, ..., GSN 〇 ~ GSNY), the appropriate gray scale voltage G1 to GM are transmitted so that the voltage of the liquid crystal display panel 400 (source channel load 420 and thin film transistor unit load 430) can climb or fall to a specified gamma voltage level within a gate time Tgate. The timing control digital circuit 320 is configured to generate different digital signal combinations ΑΡ0~APX' according to the load of the liquid crystal display panel 400 in a gate time Tgate, and the digital signal combinations ΑΡ0~APX are in the same time. The logical level of only one digital signal is 1. The dynamically adjusted source driver bias circuit 330 generates different analog level bias current Is 〇urce bias according to the foregoing digital signal combinations ΑΡ0~APX; when the logic level of the digital signal ΑΡ0 is 1, it represents The highest bias current of the dynamically adjusted source driver bias circuit 330 is selected. The operation method of this embodiment is the same as the foregoing technique. In a gate time Tgate, the bias current Is 〇urcebias of the gamma drivers 31 分成 is divided into a plurality of segments. At the beginning of a idle time Tgate, the timing control digital circuit 1379277

320 causes the logic level of the digital signal APO to be 1 to cause the dynamically adjusted source driver bias circuit 330 to generate a higher bias current Is 〇 urcebias, so that each gamma driver 310 generates sufficient driving capability to enable the liquid crystal display panel The voltage of the source channel load 420 of 〇〇{mrce channe rises or falls to the specified gamma voltage level. At the end of a gate time, the timing control digital circuit 320 causes the logic level of the digital signal APX to cause the dynamically adjusted source driver bias circuit 330 to generate the lowest bias current isourcejjias' thus Each gamma driver 310 produces a stable drive capability 'to cause the voltage level Vtft of the thin film transistor unit load 430 to climb or drop to a specified gamma voltage level. Referring to FIG. 9 , the fourth embodiment of the present invention is different from the previous embodiment in that the gamma drivers 31 can be connected to a plurality of gamma pre-drivers 311. The gamma pre-driver 3 ι is composed of resistors 312 (R1 R Rk), that is, each source channel of the same gray scale is driven by the same resistor divider and source driver. k The voltage drive point is generated by the gamma pre-drivers 311 and the resistors are divided by the number of voltage drive points being the same as the number of gray levels to be presented. The number of gamma pre-drivers 311 (1 to Z) and the voltage of the divided resistors 312 are large = the number of teams ~ called engineering applications. The gamma pre-driver 祀 is controlled by the bias current and the current Is 〇 urce_bias, so that the input gamma pre-voltage levels Vga_preJeveL1 VVrereJeveLZ output pre-voltage levels are generated by dividing the voltages 312. Required grayscale voltage = ~^. The gray scale voltages G1 GM GM are further selected by the plurality of digital analog converters 340 according to the digits (4) I379277 ^Sn〇~gsny), and the appropriate gray scale voltages G1 GM GM are transmitted to make the liquid appear daily. The load on panel 400 (source channel minus 42 〇 and thin film transistor unit, load 430) can climb or fall to a specified gamma voltage level within one line time τ (four). • The timing control digital circuit 320 is used to generate different digital signal combinations ΑΡ0~APX' during the -gate time Tgate, ', the liquid daily display of the load of the panel 4G0 and the digital signal combination Ap〇 ~Αρχ Only one digital signal has a logic level of 1 at the same time. The source driver bias circuit 33 of the dynamic adjustment ♦ generates different analog level bias currents according to the foregoing digital signal combinations 〜0~APX; when the logic level of the digital signal APG is 丨, the representative selects the The dynamically adjusted source driver bias circuit 330 has the highest bias current Is_plus. The operation method of this embodiment is based on the gate line time U, and the bias current Is 〇urcebias of the gamma pre-drivers 311 is divided into a plurality of segments. At the beginning of a gate time Tgate, the timing control digital circuit 32 causes the logic level of the digital signal ΑΡ0 to make the source of the dynamic adjustment generate a higher bias voltage η-heart, so that each gamma pre-drive ^ 311 generates sufficient driving capability to cause the voltage Vsource channe of the source channel load 420 of the liquid crystal display panel 4 to rise or fall to a specified gamma voltage level. At the end of a gate time Tgate, the timing control digital circuit 320 causes the logic bit of the digital signal APX to be quasi-丨, so that the dynamically adjusted source driver bias circuit 330 generates the lowest bias current I m Each gamma pre-driver 311 produces a stable drive capability "to cause the voltage level VTFT of the thin film transistor unit load 430 to climb or fall to a specified 17 1379277 gamma voltage level. However, the foregoing is merely a preferred embodiment of the present invention. The scope of the present invention is not limited to the scope of the present invention. All changes and modifications made in accordance with the scope of the present invention are covered by the scope of the invention. 1379277 [Simple description of the drawing], Figure 1 Schematic diagram of the known source driver driving the liquid crystal display load. 1 Fig. 2 is a waveform diagram of the source channel load and the voltage of the thin film transistor storage unit load, and the bias current of the source driver according to Fig. 1. Fig. 3 is a waveform diagram of the bias current of the source driver The source driver drives the liquid crystal display load diagram _ Fig. 4 is a schematic view of the first embodiment of the present invention. Fig. 5 is the source channel load and the thin film transistor of Fig. 4. FIG. 6 is a schematic diagram of a second embodiment of the present invention. FIG. 7 is a schematic diagram of a second embodiment of the present invention. FIG. 7 is a source channel load and a thin film transistor storage unit of FIG. The waveform of the load, and the waveform of the bias current of the source driver. Fig. 8. is a schematic view of a third embodiment of the present invention. Fig. 9 is a schematic view of a fourth embodiment of the present invention. 10, 100, 300: Liquid crystal driver • 11, 110: source driver 120, 320: timing control digital circuit 130, 330: dynamically adjusted source driver bias circuit 20, 200, 400: liquid crystal display panel 21, 210, 410 : Signal line 22, 220, 420: source channel load 23, 230, 430: thin film transistor unit load 310: gamma driver 1379277 311: gamma pre-driver 312: resistor 340: digital analog converter

Tgate: brake line time

Isource_bias · Bias current ΑΡ0~APX digital signal ^source level "Source Voltage level

Rsource_channel_l~Rsource_channel_N · Csource channel 1 ~Cs〇urce channel N · Equivalent source channel resistance Equivalent source channel capacitance

RtFT 1 to RtFT N : equivalent monomer resistance C TFT_ 1 to CtfT_N : equivalent storage capacitor. Vgamma_level_l~Vgamma_level_M · Gamma voltage level G1 to GM: Gray scale voltage.

Vga_pre_level_l~V ga_pre_ievei-z _ pre-voltage

Gprel~Gprez: Pre-voltage level

20

Claims (1)

1379277 X. Patent application scope · · L Low-power source driving device is applied to liquid crystal driver driver 1. The load on the liquid crystal display panel includes: a timing control digital circuit, which is within a gate time Generating different digital signal combinations, and the digital signal combination has only one digital signal logic level at the same time; the dynamically adjusted source drives the II bias circuit according to the foregoing digital signals Combining different bias currents to generate different analog levels; and Φ a plurality of source drivers, which are controlled by the aforementioned bias current to generate a phase-effect output driving the moonlight force, so that the load of the liquid crystal display panel can be in the -gate line Climb or fall to the specified gamma voltage level within time. 2. The low power source driving device of claim 1, wherein the digital signal combination is at least a combination of two digital signals; and the dynamically adjusted source driver bias circuit is based on the digital signals as described above. Combining to generate a bias current of at least two analog levels, generating a normal bias current at the beginning of each line time, so that the source drivers generate sufficient driving capability to cause the source channel load voltage of the liquid crystal display panel to rise or fall. At least a lower bias current is generated to the specified gamma electric waste level, and at the remaining gate time, the sources are driven to generate a stable driving force. - The low power source drive device described in item 2 of the patent scope is claimed. The biased current generated by the dynamically adjusted source driver bias circuit is smaller near the end of the master gate time. 4. A low-profile driving device for a liquid crystal driver to drive a load of a 21 1379277 liquid crystal display panel, comprising: a timing control digital circuit that generates different '(10) bit signal combinations during the inter-line time, And the digital signal combination has only one digital signal logic level at the same time; - two dynamically adjusted source driver (four) circuits, which generate different analog level deviations according to the aforementioned 'digital signal combination" >1 current, · and I number of gamma drivers' are controlled by the above-mentioned partial (four) flow, respectively, to generate the gray-scale electrical energy to be presented, and then by a plurality of digital analog converters The load of the liquid crystal display panel can be climbed or dropped to a specified gamma voltage level within a gate time. 5. The low power source driving device of claim 4, wherein the digital signal combination is at least a combination of two digital signals, and the dynamically adjusted source drives the H (four) circuit according to the foregoing number = The signal combination generates a bias current of at least two analog levels, wherein a normal bias current is generated at the beginning of each gate time, so that the gamma drivers generate sufficient driving capability to enable the liquid crystal display panel: Climb or fall to a specified gamma voltage level, and at least one lower bias current is generated during the remaining gate time, allowing the gamma drivers to produce stable drive capability. 6. The low power source driving device of claim 5, wherein the closer to the end of each gate time, the smaller the bias current generated by the dynamically adjusted source driver bias circuit. The low power source driving device of claim 4, wherein the gamma drivers are further composed of a plurality of gamma pre-drivers and 22 1379277 resistors between each gamma pre-driver, The aforementioned bias current control separately divides the voltage to generate a gray scale voltage to be presented. 8. The low power source driving device of claim 7, wherein the digital signal combination is at least a combination of two digital signals; and the dynamically adjusted source driver bias circuit is generated according to the digital signal combination. At least two types of bias currents of a specific level, wherein a normal bias current is generated at the beginning of each gate time, so that the gamma pre-drivers generate sufficient driving capability to cause the load voltage of the liquid crystal display panel to climb or fall to The specified gamma voltage level, and at the remaining open time, produces at least a lower bias current to cause the gamma pre-driver to produce a stable drive capability. The invention relates to a low-power source driving device according to item 7 of the patent (4), which is close to the end of the mother-gate time, and the dynamically adjusted source driver bias circuit generates (4) (4) the smaller the flow. twenty three