FT377661 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種基板及其製法，尤指一種適用於堆 疊式封裝結構（package on package, PoP )，以縮小封裝尺 5 寸並增加可靠度及良率之封裝基板及其製法。 【先前技術】 丨目前電子產品隨著市場的需求及在先進製程技術相互 配合之下，再加上各項3C產品不斷強調可攜式的便利性和 10市場需求的普及化，傳統的單一晶片封裝技術已逐漸無法 滿足日漸新穎化市場需求，具備輕、薄'短、小的產品特 性和增加封裝密度及低成本特性之設計製造已經是眾所皆 知的產品趨勢。在輕、薄、短、小的前提下將各種不同功 能的積體電路（1C)利用各種不同封裝方式整合來減少封 15裝體積和封裝厚度，是目前各種封裝產品開發市場研究的 主流。為迎合產品多功能之需求’目前業界積極發展相關 >堆疊式封裝結構（PoP，Package 〇n package )，其係將個別 具有積體電路之封裝體，藉由錫球或透過打線將複數個封 裝體進行堆疊，提昇電性功能，以符合目前市場的需求。 20 α目料疊式封裝結構H，其係主要將封裝體與 封裝體或與封裝基板進行堆疊，透過打線技術或焊球接ς 技術進行電性連接。如圖k封裝結構剖視圖所示，第二二 裝體3與第-封裝體R間放置點著層4〇進行堆疊，透過打 線技術使用谭線17連接兩者之打線塾而構成堆疊式封裝结 4 1377661 ’ 構。其中’第二封裝體3主要由封裝基板3〇及經焊線37連接 封裝基板30之半導體晶片38所組成’且封裝基板3〇相對於 配置半導體晶片38之另一表面，具有用於連接至印刷電路 板之焊料球36，而第一封裝體丨之封裝基板1〇係藉由焊料凸 5 塊16以覆晶方式電性連接另一半導體晶片50。 然而，用於電性連接兩封裝體之習知打線技術，其中 所形成之線弧高度約為1〇至15密爾（mil)，雖然可藉著調 正線弧參數、外形及型式，但僅可將弧高降低至約ό密爾 ,(ππΐ)，此已是最小弧高，倘若弧高更低將使焊線受損而 1〇劣化其拉力。亦即當使用習知打線技術進行兩封裝體電性 連接％，封裝結構的厚度適必受限於焊線之最小弧高而 不利於薄型化封裝結構。如同圖1所示，於第二封裝體3之 封裝基板3 〇及第一封裝體丨之封裝基板丨〇兩者之間電性連 ?的焊線17 ’其具有一定高度的弧高，因此後續進行封膠 15時，勢必因谭線狐高而增加封膠厚度，進而增加封裝结構 产的厚度。因此，若能夠改善或克服上述限制，將更有^於 • 符合現今封裝結構積集化及微型化之需求。 、 【發明内容】 20 =發明之主要目的係在提供—種供㈣封裝之基板及 二本發明降低打線墊，使封裝基板表面與打線塾之 B形成洛差’且此落差為基板厚度的一半以上， 封裝時封裝基板即具有足夠空間容納焊線弧高，合因 焊線弧高增加厚度，同時也可減短焊線長度並降低焊二焊 5 1377661 5FT377661 VI. Description of the Invention: [Technical Field] The present invention relates to a substrate and a method of fabricating the same, and more particularly to a package on package (PoP) for reducing the package size by 5 inches and increasing reliability. And yield package substrate and its preparation method. [Prior Art] At present, with the market demand and advanced process technology, and the 3C products continue to emphasize the convenience of portable and the popularization of 10 market demands, the traditional single chip Packaging technology has gradually failed to meet the increasingly new market demand. Design and manufacturing with light and thin 'short and small product characteristics and increasing package density and low cost characteristics are well-known product trends. Under the premise of light, thin, short and small, the integrated circuit (1C) of various functions is integrated by various packaging methods to reduce the package volume and package thickness, which is the mainstream of various package product development market research. In order to meet the needs of product versatility, the current industry is actively developing related packages (PoP, Package 〇n package), which will be individually packaged with integrated circuits, which will be used by solder balls or through wires. The package is stacked to enhance electrical functions to meet current market demands. 20α mesh stacking structure H, which mainly stacks the package with the package or with the package substrate, and electrically connects through the wire bonding technology or the solder ball bonding technology. As shown in the cross-sectional view of the package structure of FIG. k, the second two bodies 3 and the first package R are placed with a layer 4 〇 for stacking, and the wire bonding method is used to connect the two wires to form a stacked package by a wire bonding technique. 4 1377661 ' Construction. The second package 3 is mainly composed of a package substrate 3 and a semiconductor wafer 38 connected to the package substrate 30 via a bonding wire 37. The package substrate 3 is disposed on the other surface of the semiconductor wafer 38 with respect to the other surface of the semiconductor wafer 38. The solder ball 36 of the printed circuit board, and the package substrate 1 of the first package body is electrically connected to the other semiconductor wafer 50 by flip-chip bonding by the solder bumps 5. However, the conventional wire bonding technique for electrically connecting two packages has a line arc height of about 1 〇 to 15 mils, although by adjusting the arc parameters, shape and type of the arc, Only the arc height can be reduced to about ό mil, (ππΐ), which is the minimum arc height. If the arc height is lower, the wire will be damaged and the tension will be deteriorated. That is, when the two-package electrical connection is made using the conventional wire bonding technique, the thickness of the package structure is necessarily limited by the minimum arc height of the bonding wire, which is disadvantageous for the thin package structure. As shown in FIG. 1 , the bonding wire 17 ′ electrically connected between the package substrate 3 第二 of the second package 3 and the package substrate 第一 of the first package 其 has an arc height of a certain height, so When the sealant 15 is subsequently applied, it is bound to increase the thickness of the sealant due to the height of the Tan line fox, thereby increasing the thickness of the package structure. Therefore, if the above limitations can be improved or overcome, it will be more suitable for the integration and miniaturization of today's package structures. [Invention] 20 = The main purpose of the invention is to provide a substrate for (4) package and two inventions to reduce the wire bonding pad, so that the surface of the package substrate and the B of the wire bond are formed as a difference, and the drop is half of the thickness of the substrate. In the above, the package substrate has sufficient space to accommodate the arc height of the bonding wire, and the thickness of the bonding wire is increased by the arc height, and the length of the bonding wire can be shortened and the welding second welding can be reduced. 5 1377661 5
10 15 20 接處文損的機率，有利於製造過程，進而達到縮小封裝尺 寸增加產品可罪度及良率、提高訊息傳遞速度。 為達上述目的，本發明提供一種供堆疊封裝之基板的 裏法’包括.提供-核心板，該核^板係由—具有相對之 第表面及一第二表面之載板、以及分別設於該第—表 面及該第二表面之—圖案化金屬層及一線路層所構成，其 中，該線路層具有複數打線墊及複數電性連接塾，該複數 電性連接墊係呈陣列排列形成—陣列區，該複數打線墊設 於°亥陣列區週緣’以構成-圍繞該陣列區之環框區，且該 圖案化金屬層具有一第一開口及複數第一開孔，以分別對 應該環框區及該複數電性連接塾；於該第—表面及該第二 表面分別形成-第—介電層及一第二介電層，以覆蓋該圖 案化金屬層及該線路層；以及於該載板及該第-介電層對 應該第-開口分別形成一第二開口及一第三開口，以顯露 出該味框區，並於對應該複數第一開孔的位置分別形成複 數第-開孔及複數第三開孔’以顯露出該複數電性連接 墊，其中’該第-介電層與該複數打線墊表面形成一落差。 本發明上述方法中，該第二開口、該第三開口 '該複 數第二開孔及該複數第三開孔可藉由雷射形成。 本發明上述方法復可包括於已顯露之該複數打線塾及 該複數電性連接整表面分別形成—第—處理層及一第二處 理層此外1再包括於該第二處理層上形成複數焊料凸 塊。 6 1377661 . …本發明上述方法復可包括於該複數電性連接墊上形成 稷數金屬凸塊。此外’可再包括於該複數打線塾及該複數 金屬凸塊上分別形成一第一處理層及一第二處理層。 本發明上述方法於形成該第二開口及該複數第二開孔 5之前，復可包括於該第一介電層及該第二介電層表面分別 形成-第-防焊層及一第二防焊層，其中，該第一防焊層 具有-第四開口及複數第四開孔以分別肖應該環框區及 該複數電性連接塾。 * 揭明亦提供一種供堆疊封裝之基板，其可由上述方 10法製得，包括：一核心板，係由一具有相對之一第一表面 及一第二表面之載板、以及分別設於該第一表面及該第二 表面之一圖案化金屬層及一線路層所構成，其中，該線路 層具有複數打線塾及複數電性連接塾，該複數電性連接塾 係呈陣列排列形成一陣列區，該複數打線墊設於該陣列區 15週緣，以構成一圍繞該陣列區之環框區，且該圖案化金屬 層具有一第一開口及複數第一開孔，以分別對應該環框區 • 及該複數電性連接墊，該載板具有一第二開口及複數第二 開孔，以分別顯露出該環框區及該複數電性連接墊；—第 一介電層，係配置於該載板之該第一表面且覆蓋該圖案化 20金屬層，其中，該第一介電層具有一第三開口及複數第三 開孔，以分別顯露出該環框區及該複數電性連接墊，且該 第一介電層與該複數打線墊表面形成一落差；以及—第二 介電層，係配置於該載板之該第二表面且覆蓋該線路層； 其中該落差大於該基板厚度的一半。 7 1377661 本發明上述基板復可包括一第一處理層及一第二處理 層，分別配置於該複數打線墊及該複數電性連接墊表面。 此外，可再包括複數焊料凸塊配置該第二處理層表面。 本發明上述基板復可包括複數金屬凸塊配置於該複數 5 電性連接墊表面。此外，可再包括一第一處理層及一第_ 處理層分別配置於該複數打線墊及該複數金屬凸塊表面。 本發明上述基板復可包括一第一防焊層及一第二防焊 層分別配置於該第一介電層及該第二介電層表面，其中， I 该第一防焊層具有一第四開口及複數第四開孔，以分別顯 10 露出該環框區及該複數電性連接墊。 本發明上述基板中，該第一開口之尺寸可分別大於該 第二開口、及該第三開口。 本發明上述基板中，該複數第一開孔之尺寸可分別大 於該複數第二開孔、及該複數第三開孔。 15 本發明上述基板中，該第二開口及該第三開口之尺寸 可相同，且該複數第二開孔及該複數第三開孔之尺寸可相 丨同。 【實施方式】 -0 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用’本說明書中的各項細節亦 可基於不同觀點與應用’在不悖離本發明之精神下進行各 8 1377661 種修飾與變更。 實施例1 參考圖2A至2F，其為本實施例供堆疊封裝之基板的製 法的流程示意剖面圖。 5 首先，如圖2A所示，提供一核心板2〇,，該核心板2〇, 係由一具有相對之一第一表面2〇a及一第二表面2〇b之載板 2〇、以及分別設於該第一表面2〇a及該第二表面2〇b之金屬 層21’及22,所構成。 齡如圖2B所示，透過蝕刻將金屬層2丨，及22，分別形成圖 10案化金屬層2丨及線路層22，其中，該線路層22具有複數打 線墊221及複數電性連接墊222。參考圖2B，所示，其為圖2B 之底視圖，該複數電性連接墊222係呈陣列排列形成一陣列 區A ’該複數打線墊221設於該陣列區a週緣，以構成一圍 繞該陣列區A之環框區B，並可藉由導線223電性連接至陣 15 列區A之電性連接墊222。同時參考圖2B及2B，，該圖案化 金屬層21具有一第一開口211及複.數第一開孔212，以分別 & 對應該環框區B及該複數電性連接墊222。 接著，如圖2C所示’於該第一表面2〇a及該第二表面2〇b 分別形成一第一介電層23及一第二介電層23,，以覆蓋該圖 20 案化金屬層21及該線路層22。 參考圖2D所示，於該載板20及該第一介電層23對應該 圖案化金屬層21之第一開口 211，使用雷射分別形成一第二 開口 201及一第三開口 231 ’以顯露出該環框區b，並於對應 該複數.案一開孔212的位置分別形成複數第二開孔2〇2及複 9 數第三開孔23 2，以顯露出該複數電性連接塾222，其中， 該第一介電層23與該複數打線墊221表面形成一落差e。由 此可知，該第一開口211之尺寸分別大於該第二開口2〇1、 及該第二開口 231，且該複數第一開孔212之尺寸係分別大 於該複數第二開孔202、及該複數第三開孔232。此外，該 第二開口 201及該第三開口 231之尺寸係相同，且該複數第 二開孔202及該複數第三開孔232之尺寸係相同。 再如圖2E所示，於已顯露之該複數打線墊22丨及該複數 電性連接墊222表面分別形成一第一處理層271及一第二處 理層272。 最後，參考圖2F所示，於該第二開孔2〇2及該第三開孔 232内之第二處理層272上形成複數焊料凸塊28。 本貫施例復提供一種供堆疊封裝之基板，參考圖21?及 圖2B’所示’包括：一核心板2〇,，係由一具有相對之一第 一表面20a及一第二表面2〇b之載板20、以及分別設於該第 —表面20a及該第二表面20b之一圖案化金屬層21及一線路 層22所構成，其中，該線路層22具有複數打線墊221及複數 電性連接墊222，該複數電性連接墊222係呈陣列排列形成 一陣列區A，該複數打線墊22丨設於該陣列區a週緣，以構 成一圍繞該陣列區A之環框區B，且該圖案化金屬層21具有 一第一開口 211及複數第一開孔212，以分別對應該環框區B 及該複數電性連接墊222，該載板20具有一第二開口 2〇1及 複數第二開孔202，以分別顯露出該環框區B及該複數電性 連接墊222，一第一介電層23，係配置於該載板2〇之該第一 !377661 表面20a且覆蓋該圖案化金屬層21，其中，該第—介電声η 具有-第三開口 231及複數第三開孔232,以分別顯露^該 環框區B及該複數電性連接墊222,且該第一介電層23與該 複數打線墊221表面形成一落差e ;以及一第二介電層23,， 5係配置於該載板20之該第二表面20b且覆蓋該線路層22，其 中該落差e大於基板厚度的一半。此外，本實施例供堆疊封 裝之基板，可復包括一第一處理層271及一第二處理層272 •分別配置於该複數打線墊22丨及該複數電性連接墊222表 ^ 面，以及再包括複數焊料凸塊28配置該第二處理層272表 1〇 面。 實施例2 參考圖3A至3D，其為本實施例供堆疊封裝之基板的製 法的流程示意剖面圖。 15 首先’重複實施例1圖2 A至2B之步驟，可得到圖2C所 不之結構’亦即本實施例圖3 A所示之結構。 % 隨後，如圖3B所示，於該第一介電層23及該第二介電 層23’表面分別形成一第一防焊層24及一第二防焊層24，，其 中’該第一防焊層24具有一第四開口241及複數第四開孔 2〇 242 ’以分別對應該環框區B及該複數電性連接墊222。 接著’參考圖3C所示’於該載板20及該第一介電層23 對應該圖案化金屬層21之第一開口 211，使用雷射分別形成 一第二開口 2〇1及一第三開口 231，以顯露出該環框區B，並 於對應該複數第一開孔212的位置分別形成複數第二開孔 25 202及複數第三開孔232，以顯露出該複數電性連接墊222， 1377661 其中，5玄第一介電層23與該複數打線墊221表面形成一落差 e ° 再如圖3D所不，於已顯露之該複數打線墊22丨及該複數 電連接塾222表面分別形成一第一處理層27丨及一第二處 5 理層272。 本貫施例復提供一種供堆疊封裝之基板，如圖3d所 不，其結構類似於實施例丨之基板，不同點在於本實施例之 基板復包括一第一防焊層24及一第二防焊層24，分別配置 > 於該第一介電層23及該第二介電層23,表面，其中，該第一 10防焊層24具有一第四開口 241及複數第四開孔242，以分別 顯露出該環框區B及該複數電性連接墊222。 實施例3 參考圖4A至4D，其為本實施例供堆疊封裝之基板的製 15 法的流程示意剖面圖。 首先’重複實施例1圖2A至2C之步驟，可得到圖2D所 | 示之結構。 隨後，如圖4A所示，於打線墊221上形成一阻層25。再 如圖4B所示’於該複數電性連接墊222上，透過電鍍形成複 20 數金屬凸塊26。 接著’如圖4C所示’移除該阻層25。再如圖4D所示， 於該複數打線塾2 2 1及該複數金屬凸塊2 6上分別形成一第 一處理層271及一第二處理層272。 本實施例復提供一種供堆疊封裝之基板，如圖4D所 25 示’其結構類似於實施例1之基板’不同點在於本實施例之 12 1377661 5 圖1係習知技術中堆疊式封裝結構的剖視圖。 圖2A至2F係、本發明實施例丨中供堆疊封裝之基板製法的流 程示意剖面圖。 圖2B’係本發明實施中圖2_示供堆疊封裝《基板的上 視圖。10 15 20 The probability of picking up the loss is beneficial to the manufacturing process, which in turn reduces the package size, increases the product's guilt and yield, and improves the speed of message transmission. In order to achieve the above object, the present invention provides a substrate for a package package comprising: a supply-core plate, the core plate having a carrier plate having a first surface and a second surface, and The first surface and the second surface are formed by a patterned metal layer and a circuit layer, wherein the circuit layer has a plurality of wire pads and a plurality of electrical connections, and the plurality of electrical connection pads are arranged in an array. In the array region, the plurality of wire pads are disposed on the periphery of the array region to form a ring frame region surrounding the array region, and the patterned metal layer has a first opening and a plurality of first openings to respectively correspond to the ring a frame region and the plurality of electrical connections; forming a first-dielectric layer and a second dielectric layer on the first surface and the second surface to cover the patterned metal layer and the circuit layer; The carrier plate and the first dielectric layer respectively form a second opening and a third opening corresponding to the first opening to expose the taste frame region, and respectively form a plurality of positions corresponding to the plurality of first openings - opening and plural third opening To reveal the plurality of conductive pads, wherein 'the first - forming a dielectric layer gap of the plurality of wire pad surface. In the above method of the present invention, the second opening, the third opening 'the plurality of second openings and the plurality of third openings may be formed by laser. The method of the present invention may include forming the plurality of wire bonding wires and the plurality of electrical connection entire surfaces, respectively forming a first processing layer and a second processing layer, and further comprising forming a plurality of solder on the second processing layer Bump. 6 1377661. The above method of the present invention may further comprise forming a plurality of metal bumps on the plurality of electrical connection pads. Further, a first processing layer and a second processing layer are respectively formed on the plurality of wires and the plurality of metal bumps. The method of the present invention includes forming a first-pre-solder layer and a second on the surface of the first dielectric layer and the second dielectric layer before forming the second opening and the plurality of second openings 5 The solder resist layer, wherein the first solder resist layer has a fourth opening and a plurality of fourth openings to respectively correspond to the ring frame region and the plurality of electrical connections. * The invention also provides a substrate for stacking and packaging, which can be obtained by the above method 10, comprising: a core plate, which is provided by a carrier having a first surface and a second surface, and is respectively disposed on the substrate The first surface and the second surface are formed by a patterned metal layer and a circuit layer, wherein the circuit layer has a plurality of wires and a plurality of electrical connections, and the plurality of electrical connections are arranged in an array to form an array. a plurality of wire pads are disposed on the periphery of the array region 15 to form a ring frame region surrounding the array region, and the patterned metal layer has a first opening and a plurality of first openings to respectively correspond to the ring frame And a plurality of electrical connection pads, the carrier plate has a second opening and a plurality of second openings to respectively expose the ring frame region and the plurality of electrical connection pads; - the first dielectric layer, the configuration On the first surface of the carrier and covering the patterned 20 metal layer, wherein the first dielectric layer has a third opening and a plurality of third openings to respectively expose the ring frame region and the plurality of wires Sex connection pad, and the first interface The electrical layer forms a drop with the surface of the plurality of wire pads; and a second dielectric layer is disposed on the second surface of the carrier and covers the circuit layer; wherein the drop is greater than half the thickness of the substrate. 7 1377661 The substrate of the present invention further includes a first processing layer and a second processing layer disposed on the surface of the plurality of wire pads and the plurality of electrical connection pads. Additionally, a plurality of solder bumps can be included to configure the second handle layer surface. The substrate of the present invention may include a plurality of metal bumps disposed on the surface of the plurality of electrical connection pads. In addition, a first processing layer and a first processing layer may be respectively disposed on the plurality of wire pads and the surface of the plurality of metal bumps. The substrate of the present invention includes a first solder resist layer and a second solder resist layer respectively disposed on the surface of the first dielectric layer and the second dielectric layer, wherein the first solder resist layer has a first The four openings and the plurality of fourth openings respectively expose the ring frame region and the plurality of electrical connection pads. In the above substrate of the present invention, the first opening may have a size larger than the second opening and the third opening, respectively. In the above substrate of the present invention, the plurality of first openings may be larger than the plurality of second openings and the plurality of third openings, respectively. In the substrate of the present invention, the second opening and the third opening may have the same size, and the plurality of second openings and the plurality of third openings may be different in size. [Embodiment] - 0 The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can readily appreciate the other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments. The details of the present invention can also be modified and changed without departing from the spirit and scope of the invention. Embodiment 1 Referring to Figures 2A to 2F, which are schematic cross-sectional views showing the flow of a method for a substrate for stacking and packaging in the present embodiment. 5 First, as shown in FIG. 2A, a core board 2〇 is provided, which is composed of a carrier board 2 having a first surface 2〇a and a second surface 2〇b, And the metal layers 21' and 22 respectively disposed on the first surface 2a and the second surface 2b. As shown in FIG. 2B, the metal layers 2 and 22 are respectively formed by etching to form the patterned metal layer 2 and the circuit layer 22 of FIG. 10, wherein the circuit layer 22 has a plurality of wire pads 221 and a plurality of electrical connection pads. 222. Referring to FIG. 2B, which is a bottom view of FIG. 2B, the plurality of electrical connection pads 222 are arranged in an array to form an array area A'. The plurality of wire bonding pads 221 are disposed on the periphery of the array area a to form a surrounding area. The ring frame area B of the array area A can be electrically connected to the electrical connection pads 222 of the array of 15 columns A by wires 223. Referring to FIGS. 2B and 2B, the patterned metal layer 21 has a first opening 211 and a plurality of first openings 212 to respectively correspond to the ring frame region B and the plurality of electrical connection pads 222. Then, as shown in FIG. 2C, a first dielectric layer 23 and a second dielectric layer 23 are formed on the first surface 2a and the second surface 2b, respectively, to cover the FIG. The metal layer 21 and the wiring layer 22. Referring to FIG. 2D, in the first opening 211 of the carrier layer 20 and the first dielectric layer 23 corresponding to the patterned metal layer 21, a second opening 201 and a third opening 231' are respectively formed by using lasers. The ring frame region b is exposed, and a plurality of second openings 2〇2 and a plurality of third holes 23 2 are respectively formed at positions corresponding to the openings 212 to reveal the plurality of electrical connections.塾222, wherein the first dielectric layer 23 forms a drop e with the surface of the plurality of wire pads 221 . It can be seen that the size of the first opening 211 is larger than the second opening 2〇1 and the second opening 231, respectively, and the plurality of first openings 212 are respectively larger than the plurality of second openings 202, and The plurality of third openings 232. In addition, the second opening 201 and the third opening 231 are the same size, and the plurality of second openings 202 and the plurality of third openings 232 are the same size. As shown in FIG. 2E, a first processing layer 271 and a second processing layer 272 are respectively formed on the surface of the plurality of bonding pads 22 and the plurality of electrical connection pads 222. Finally, referring to FIG. 2F, a plurality of solder bumps 28 are formed on the second processing layer 272 in the second opening 2〇2 and the third opening 232. The present invention provides a substrate for stacking and packaging, and as shown in FIG. 21 and FIG. 2B', includes a core plate 2, which has a first surface 20a and a second surface 2; a carrier board 20 of 〇b, and a patterned metal layer 21 and a circuit layer 22 respectively disposed on the first surface 20a and the second surface 20b, wherein the circuit layer 22 has a plurality of wire pads 221 and plural The electrical connection pads 222 are arranged in an array to form an array area A. The plurality of wire pads 22 are disposed on the periphery of the array area a to form a ring frame area B surrounding the array area A. The patterned metal layer 21 has a first opening 211 and a plurality of first openings 212 for respectively corresponding to the ring frame area B and the plurality of electrical connection pads 222. The carrier board 20 has a second opening 2〇 1 and a plurality of second openings 202 to respectively expose the ring frame region B and the plurality of electrical connection pads 222, and a first dielectric layer 23 disposed on the first surface of the carrier board 377661 20a and covering the patterned metal layer 21, wherein the first dielectric sound η has a third opening 231 and a complex The third opening 232 is formed to respectively expose the ring frame region B and the plurality of electrical connection pads 222, and the first dielectric layer 23 forms a drop e with the surface of the plurality of wire bonding pads 221; and a second dielectric Layers 23, 5 are disposed on the second surface 20b of the carrier 20 and cover the circuit layer 22, wherein the drop e is greater than half the thickness of the substrate. In addition, the substrate for stacking and packaging of the present embodiment may further include a first processing layer 271 and a second processing layer 272, respectively disposed on the surface of the plurality of bonding pads 22 and the plurality of electrical connecting pads 222, and A plurality of solder bumps 28 are further included to configure the second processing layer 272. Embodiment 2 Referring to Figures 3A to 3D, which are schematic cross-sectional views showing the flow of a method for a substrate for stacking and packaging in the present embodiment. 15 First, the steps of Figs. 2A to 2B of the embodiment 1 are repeated, and the structure shown in Fig. 2C, that is, the structure shown in Fig. 3A of the present embodiment, can be obtained. %, then, as shown in FIG. 3B, a first solder resist layer 24 and a second solder resist layer 24 are formed on the surface of the first dielectric layer 23 and the second dielectric layer 23', respectively, wherein A solder mask 24 has a fourth opening 241 and a plurality of fourth openings 2 〇 242 ′ to respectively correspond to the ring frame region B and the plurality of electrical connection pads 222 . Then, referring to FIG. 3C, the first opening 211 corresponding to the patterned metal layer 21 is formed on the carrier 20 and the first dielectric layer 23, and a second opening 2〇1 and a third are respectively formed by using lasers. Opening 231 to expose the ring frame region B, and forming a plurality of second openings 25 202 and a plurality of third openings 232 at positions corresponding to the plurality of first openings 212 to reveal the plurality of electrical connection pads 222, 1377661, wherein the first dielectric layer 23 and the surface of the plurality of wire bonding pads 221 form a drop e°, and as shown in FIG. 3D, the plurality of wire bonding pads 22 and the surface of the plurality of electrical connectors 222 are exposed. A first processing layer 27A and a second portion 5 layer 272 are formed respectively. The substrate of the present invention is similar to the substrate of the embodiment, as shown in FIG. 3d. The difference is that the substrate of the embodiment includes a first solder resist layer 24 and a second layer. The solder resist layer 24 is respectively disposed on the surface of the first dielectric layer 23 and the second dielectric layer 23, wherein the first 10 solder resist layer 24 has a fourth opening 241 and a plurality of fourth openings 242, to expose the ring frame area B and the plurality of electrical connection pads 222, respectively. Embodiment 3 Referring to Figures 4A to 4D, there are shown schematic cross-sectional views of a method for manufacturing a substrate for stacking and packaging. First, the steps of Figs. 2A to 2C of Embodiment 1 are repeated, and the structure shown in Fig. 2D can be obtained. Subsequently, as shown in FIG. 4A, a resist layer 25 is formed on the wire pad 221. Further, as shown in FIG. 4B, a plurality of metal bumps 26 are formed by electroplating on the plurality of electrical connection pads 222. The resist layer 25 is then removed as shown in Fig. 4C. As shown in FIG. 4D, a first processing layer 271 and a second processing layer 272 are formed on the plurality of wires 塾2 2 1 and the plurality of metal bumps 26, respectively. In this embodiment, a substrate for stacking and packaging is provided, as shown in FIG. 4D, which is similar to the substrate of Embodiment 1. The difference is that in the present embodiment, 12 1377661 5 FIG. 1 is a stacked package structure in the prior art. Cutaway view. 2A to 2F are schematic flow cross-sectional views showing a method of manufacturing a substrate for stacking and packaging in an embodiment of the present invention. Figure 2B is a top view of the substrate for the stacked package of Figure 2 in the practice of the present invention.
10 圖3A至3D縣發明實施例2中供堆疊封裝之基板製法的流 程示意剖面圖。 圖4A至侧系本發明實施例3中供堆疊封裝之基板製法的流 程示意剖面圖。 圖5係本發明所應用之堆疊式封装結構的剖面圖。10 is a schematic flow cross-sectional view showing a method of manufacturing a substrate for stacking and packaging in Inventive Example 2 of Figs. 3A to 3D. 4A to 4 are schematic flow cross-sectional views showing a method of manufacturing a substrate for stacking and packaging in Embodiment 3 of the present invention. Figure 5 is a cross-sectional view of a stacked package structure to which the present invention is applied.
【主要元件符號說明】 1 第一封裝體 3 10,30 封裝基板 16 ^,27,37 焊線 20， 20 載板 201 202 第二開孔 20a 20b 第二表面 21，，22, 21 圖案化金屬層 211 212 第一開孔 22 221 打線墊 222 223 導線 23 23， 第二介電層 231 232 第三開孔 24 第二封裝體 焊料凸塊 核心板 第二開口 % 一表面 金屬層 第一開口 線路層 電性連接墊 第一介電層 第三開口 第一防焊層 14 1377661 245 第二防焊層 241 第四開口 242 第四開孔 25 阻層 26 金屬凸塊 271 第一處理層 272 第二處理層 28 焊料凸塊 36 焊料球 38,50 半導體晶片 40 間隔物 A 陣列區 B 環框區 e 落差[Main component symbol description] 1 First package 3 10, 30 package substrate 16 ^, 27, 37 bonding wire 20, 20 carrier 201 202 second opening 20a 20b second surface 21, 22, 21 patterned metal Layer 211 212 first opening 22 221 wire pad 222 223 wire 23 23, second dielectric layer 231 232 third opening 24 second package solder bump core plate second opening % one surface metal layer first opening line Electrical connection pad first dielectric layer third opening first solder resist layer 14 1377661 245 second solder resist layer 241 fourth opening 242 fourth opening 25 resist layer 26 metal bump 271 first processing layer 272 second Processing layer 28 solder bumps 36 solder balls 38, 50 semiconductor wafer 40 spacer A array area B ring frame area e drop
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