TWI377368B - Thin film transistor substrate, fabricating method thereof, and electro-wetting display - Google Patents

Thin film transistor substrate, fabricating method thereof, and electro-wetting display Download PDF

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TWI377368B
TWI377368B TW97116297A TW97116297A TWI377368B TW I377368 B TWI377368 B TW I377368B TW 97116297 A TW97116297 A TW 97116297A TW 97116297 A TW97116297 A TW 97116297A TW I377368 B TWI377368 B TW I377368B
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layer
disposed
thin film
film transistor
substrate
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TW97116297A
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TW200946955A (en
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Rei Yun Lee
Shuo Ting Yan
Jung Lung Huang
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Chimei Innolux Corp
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1377368 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種薄膜電晶體基板、薄膜電晶體基板製 造方法及電濕潤式顯示裝置。 【先前技術】 如今,諸多光電技術正在快速的發展且應用於下一代平 板顯示器,如投影顯示器(Projection Display)、可撓式顯示 器(Flexible Dispaly)等。在此環境下,一種基於電濕潤原理 的顯示裝置由於其響應速度快、視角廣、耗電量小、輕薄便 攜等優點受到廣泛的關注。 請參閱圖1,係一種先前技術揭示的基於電濕潤原理的 反射式顯示裝置的平面結構示意圖。該顯示裝置1包括複數 呈矩陣排列之像素10,通過控制該像素10顯示不同的灰階 以組成該顯示裝置1所需顯示之晝面。 請參閱圖2,係圖1所示顯示裝置1之一像素10的放大 剖視結構示意圖。該像素10包括一對向基板11、一與其相 對之薄膜電晶體基板12及設置於該二基板11、12之間的四 間隔壁13,該四間隔壁13依序首尾相接並與該二基板11、 12形成一收容空間14。 該對向基板11係使用透光材料製成,如玻璃或塑膠。 該對向基板11鄰近該收容空間14之表面設置有一公共電極 111,該公共電極111由透明的導電材質製成。 該收容空間14由互不相融(Immiscible)的一第一液體15 及一第二液體16充滿。例如,該第一液體15可以是導電的 6 1377368 ‘ 水,該第二液體16可以是黑色的油。 該薄膜電晶體基板12鄰近該收容空間14之表面依序設 ‘ 置有一主動元件(圖未示)、一反射電極121及一絕緣層122。 由於該反射電極121採用純鋁製成,故具有較高的反射率。 該絕緣122係由疏水性(Hydrophobic)材料製成,如無定型 的含氟聚合物(Amorphous Fluoropolymer)。 由於該絕緣層122之疏水性,即在該絕緣層122、第一 液體15及第二液體16三者之間的表面張力(Interfacial • Tension)作用下,該第二液體16充分覆蓋該絕緣層122。由 於該第二液體16呈黑色,其吸收了絕大部份自該對向基板 11方向射入之光束,故此時之像素10為暗態(Off State)。 請一併參閱圖3,係圖2所示像素10亮態結構示意圖。 當一電壓差被施加於該公共電極111與該反射電極121之間 時,由於該第一液體15與該公共電極111相接觸使該第一 液體15與該公共電極111上之電壓相同。該第一液體15與 0 該反射電極121各自所載之異性電荷的吸引力破壞了暗態時 分子張力的平衡態,即此時電勢能的介入使該絕緣層122與 第一液體15傾向於接觸,故該第一液體15將該第二液體16 排開,從而自該對向基板11方向射入之光束經過上述被排 開的部份所對應的反射電極121反射,實現亮態(On State)。 惟,由於為該公共電極111及反射電極121分別提供電 壓差之驅動電路(圖未示)通常設置在該薄膜電晶體基板 12,故位於薄膜電晶體基板12之該驅動電路需要與位於對 向基板11之公共電極111電連接,因此該顯示裝置1結構 較複雜。同時,該公共 _^ $ 电稂111對先具有一定吸收作用,使 該顯不裝置1光利用率下降,光學品質較差。 【發明内容】 ⑽有此’提供—種結構簡單且光學品質較佳之電濕潤 式顯不裝置實為必需。 ,時供該電濕潤式顯示裝置所採用之薄膜電晶體 板亦為必需。 鲁-種薄膜電晶體基板,其包括—顯示區、位於該顯示區 •至^側之至少-接觸區、一包圍該顯示區及該接觸區並用 於:置框膠之㈣設置區、複數設置於該顯示區之像素電極 及-又置於該至少《•接觸區之至少—公共電極,且該薄膜電晶 體基板裸露出該至少一公共電極之至少一部份。 種電濕潤式顯示裝置,其包括一對向基板、一與該對 向基板相對设置之薄膜電晶體基板、設置於該對向基板及該 薄膜電晶體基板之間並與該對向基板及該薄膜電晶體基板 Φ配合形成一收容空間之一框膠、一設置於該收容空間内之極 性之第一液體及一與該第一液體不相融且設置於該收容空 間内之非極性之第二液體,其中,該薄膜電晶體基板包括位 於該框膠於該薄膜電晶體基板界定之區域内之至少一接觸 區、位於該框膠於該薄膜電晶體基板限定之區域内之一顯示 區、複數設置於該顯示區之像素電極、一設置於該像素電極 之親油性絕緣層圖案及至少一設置於該至少一接觸區之公 /、電極’且該薄膜電晶體基板裸露出該至少一公共電極之至 少一部份。 1377368 * 一種薄膜電晶體基板,其包括一第一區域、一位於該第 一區域外圍用於設置框膠之框膠設置區、設置於該第一區域 内之複數像素電極及至少一設置於該第一區域内之公共電 極,該公共電極與該像素電極絕緣,且該薄膜電晶體基板裸 露出該至少一公共電極之至少一部份。 一種電濕潤式顯示裝置,其包括一對向基板、一與該對 向基板相對設置之薄膜電晶體基板、設置於該對向基板及該 薄膜電晶體基板之間並與該對向基板及該薄膜電晶體基板 ® 配合形成一收容空間之一框膠、交叉設置於該對向基板及該 薄膜電晶體基板之複數間隔壁、一設置於該收容空間内之極 性之第一液體及一第二液體,該框膠於該薄膜電晶體基板上 界定一第一區域,該間隔壁位於該第一區域内,該第二液體 位於該間隔壁界定之區域内,其中,該薄膜電晶體基板包括 設置於該間隔壁界定之區域内之複數像素電極及至少一設 置於該第一區域内之公共電極,該公共電極與該像素電極絕 I 緣,且該薄膜電晶體基板裸露出該至少一公共電極之至少一 部份。 一種薄膜電晶體基板製造方法,其包括如下步驟:提供 一基底;於該基底上形成至少一電容電極線及複數掃描線; 於該電容電極線、該掃描線及該基底上形成一第一絕緣層; 於該第一絕緣層上形成複數資料線;於該第一絕緣層及該資 料線上形成一鈍化層;對應該電容電極線位置形成一貫穿該 鈍化層及該第一絕緣層之通孔;於該鈍化層上間隔形成一公 共電極及複數像素電極,使該公共電極藉由該通孔與該電容 1377368 電極線電連接;於該像素電極上形成一親油性絕緣層圖案, 並裸露出該至少一公共電極之至少一部份。 一種薄膜電晶體基板,其包括一基底、一設置於該基底 上之複數閘極、複數掃描線及複數電容電極線、一設置於該 複數閘極、該掃描線、電容電極線及該基底上之閘極絕緣 層、設置於該閘極絕緣層上之一半導體圖案及複數資料線、 設置於該半導體圖案及該閘極絕緣層上之複數源極及複數 汲極、一設置於該閘極絕緣層、該資料線、該源極、該汲極 及該半導體圖案上之鈍化層、設置於該鈍化層上之複數像素 電極及一公共電極及一設置於該像素電極上之親油性絕緣 層圖案,該薄膜電晶體基板裸露出該至少一公共電極之至少 一部份。 一種電濕潤式顯示裝置,其包括一對向基板、一與該對 向基板相對設置之薄膜電晶體基板、設置於該對向基板及該 薄膜電晶體基板之間並與該對向基板及該薄膜電晶體基板 配合形成一收容空間之一框膠、一設置於該收容空間内之極 性之第一液體及一設置於該收容空間内之非極性之第二液 體,其中,該薄膜電晶體基板包括一基底、一設置於該基底 上之複數閘極、複數掃描線及複數電容電極線、一設置於該 複數閘極、該掃描線、電容電極線及該基底上之閘極絕緣 層、設置於該閘極絕緣層上之一半導體圖案及複數資料線、 設置於該半導體圖案及該閘極絕緣層上之複數源極及複數 汲極、一設置於該閘極絕緣層、該資料線、該源極、該汲極 及該半導體圖案上之鈍化層、設置於該鈍化層上之複數像素 1377368 電極及一公共電極及一設置於該像素電極上之親油性絕緣 層圖案,該薄膜電晶體基板裸露出該至少一公共電極之至少 一部份。 一種薄膜電晶體基板製造方法,其包括如下步驟:提供 一基底;於該基底上形成複數閘極、複數掃描線及複數電容 電極線;於該複數閘極、該掃描線、電容電極線及該基底上 形成一閘極絕緣層;於該閘極絕緣層上形成一半導體圖案及 複數資料線;於該半導體圖案及該閘極絕緣層上形成複數源 極及複數汲極;於該閘極絕緣層、該資料線、該源極、該汲 極及該半導體圖案上形成一鈍化層;於該鈍化層上形成複數 像素電極及一公共電極;於該像素電極上形成一親油性絕緣 層圖案,並裸露出該至少一公共電極之至少一部份。 與先前技術相比,本發明之電濕潤式顯示裝置由於其公 共電極及像素電極均位於該薄膜電晶體基板上,無須將公 共電壓導接到對向基板上,且不會對用於顯示畫面之光束造 成影響,故該電濕潤式顯示裝置結構較簡單,光學品質較佳。 與先前技術相比,本發明之薄膜電晶體基板及薄膜電晶 體基板製造方法由於其公共電極及像素電極均位於該薄膜 電晶體基板上’無須將公共電壓導接到其他基板上’故該薄 膜電晶體基板使用較方便。 【實施方式】 請參閱圖4,係本發明電濕潤式顯示裝置第一實施方式 之局部結構示意圖。該電濕潤式顯示裝置4係透射式顯示裝 置,其包括一對向基板41、一與該對向基板41相對設置之 11 1377368 薄膜電晶體基板42、一位於該對向基板41及該薄膜電晶體 基板42之間的框膠49、位於該對向基板41及該薄膜電晶體 基板42之間的複數成行列交叉排列之間隔壁43及一與該薄 膜電晶體基板42鄰近設置之背光模組(圖未示)。該薄膜電晶 體基板42包括一框膠設置區(未標示)。該框膠49設置於該 框膠設置區且抵接該二基板41、42並與該二基板41、42配 合形成一封閉之第一收容空間441,且該框膠49於該薄膜電 晶體基板42界定一第一區域48。該第一區域48包括一顯示 區481及一接觸區482。該間隔壁43設置於該薄膜電晶體基 板42之顯示區481並界定複數呈矩陣排列之像素區40,且 該間隔壁43與該薄膜電晶體基板42配合形成複數第二收容 空間442。其中,該間隔壁43之高度小於該框膠49之高度。 該第一收容空間441内由互不相融的一第一液體45及 一第二液體46充滿。該第二液體46位於每一第二收容空間 442中,且該第二液體46相對於該薄膜電晶體基板42之高 度小於該間隔壁43之高度。該第一液體45可以是水或鹽溶 液等導電液體或極性液體,如氯化鉀(KC1)溶解於水和普通 酒精(Ethyl Alcohol)混合液後所形成的溶液。該第二液體46 可以是著黑色的鏈烷或烷烴(Alkane)等非極性液體,如十六 烧(Hexadecane)或油,以作為一種遮蔽液體。 請一併參閱圖5及圖6,圖5係圖4所示電濕潤式顯示 裝置4薄膜電晶體基板42之平面結構局部示意圖,圖6係 圖5所示薄膜電晶體基板42沿VI-VI方向剖視示意圖。該 薄膜電晶體基板42包括一玻璃之基底420、設置於該基底 12 Ϊ377368 42〇上之複數閘極421、複數相互平行間隔之掃描線422及 * "^數相互平行間隔之電容電極線423、設置於該閘極421、 掃,線422及該電容電極線423上之閘極絕緣層424、設置 於該間極絕緣層424上之—半導體圖案425及複數相互平行 間隔之貢料線426、設置於該半導體圖案425及該閘極絕緣 f 424上之複數源極427及複數汲極428、一設置於該閘極 、名緣層424、該資料線426、該源極427、該汲極428及該半 •導體圖案425上之鈍化層429、設置於該鈍化層429上之複 數像素電極430及一公共電極431、及一設置於該像素電極 430上之親油性絕緣層圖案432。 該資料線426平行於該顯示區481與該接觸區482之交 界線。該掃描線422與該資料線426相互垂直,每一掃描線 422及每一資料線426均對應一間隔壁43並夾於間隔壁u 於基底420之間,二相鄰掃描線422與二相鄰資料線a%交 叉界定的最小區域與該像素區4G —對應。該電容電極線 籲423自該接觸區482延伸至該顯示區481並與該掃描線 交替設置,使每一電容電極線423穿過一行像素區4〇。每一 閘極421、每一源極427、每一汲極428、每一像素電極43〇 對應一像素區40,該閘極421電連接至對應之掃描線芯2, 該源極427電連接至對應之資料線426,該汲極428藉由— 貫穿該鈍化層429之第一通孔433電連接至對應之像素電極 430。該公共電極431位於該接觸區482,並藉由一貫穿該鈍 化層429及該閘極絕緣層424之第二通孔434電連接至該電 容電極線423。該公共電極431及該像素電極43〇由透明導 13 1377368 ’電材質製成^氧化__)或氧化銦鋅(IZ0)。 對於每像素區40,該閘極421、該閘極絕緣層㈣、 該半導體圖案425、該滿权jh 原極427及該汲極428配合形成一薄 膜電晶體’用來控制對"座+ μ 利對應之像素電極430之充電或不充電; 穿過該像素區40之電容電極線伯、該閉極絕緣層424、該 純化層429及該像素電極43〇層疊形成一儲存電容,用來維 持該像素電極430的電麗^ • 該電濕潤式顯示裝置4工作時,該公共電極431被施加 一公共電壓’每一像素電極43〇被施加對應的灰階電壓。由 於该公共電極431與位於該接觸區482之該第一液體45接 觸,可以使該第一液體45與該公共電極431電連接從而具 有與公共電極431相同的電壓。藉由改變每一像素電極43〇 被施加之灰階電壓的大小來控制該第一液體45排開該第二 液體46多募來使該電濕潤式顯示裝置4正常顯示圖像。 相較於先前技術,本發明電濕潤式顯示裝置4由於其公 鲁共電極431及像素電極430均位於該薄膜電晶體基板42, 無須將公共電壓導接至該對向基板41上,故該電濕潤式顯 不裝置4結構較簡單。且,由於該公共電極431位於該像素 區40旁邊,因此不會對穿過像素區4〇的光束造成影響,故 該電濕潤式顯示裝置4光學品質較佳。 請一併參閱圖7,係圖6所示薄膜電晶體基板42之製造 流程圖。該薄膜電晶體基板42之製造方法包括如下步驟: 步驟S1 :形成閘極金屬層; 提供一玻璃基底420,在該基底420上依序形成一閘極 1377368 金屬層及一第一光阻層。 步驟S2:形成閘極421、掃描線422及電容電極線423 ; 提供一第一光罩對該第一光阻層進行曝光顯影,從而形 成一預定之第一光阻圖案;以第一光阻圖案為阻擋物對該閘 極金屬層進行蝕刻,形成該閘極421、掃描線422及電容電 極線423之圖案,移除第一光阻圖案。 步驟S3 :形成閘極絕緣層424及半導體層; 於該閘極421、該掃描線422、該電容電極線423及該 玻璃基底420上形成該閘極絕緣層424、一半導體層及一第 二光阻層。 步驟S4 :形成半導體圖案425 ; 提供一第二光罩對該第二光阻層進行曝光顯影,從而形 成一預定之第二光阻圖案;以第二光阻圖案為阻擋物對該摻 雜非晶矽層及該非晶矽層進行蝕刻,進而形成該半導體圖案 425,移除第二光阻圖案。 步驟S5 :形成源/汲極金屬層; 於該玻璃基底420及該半導體圖案425上形成一源/汲 極金屬層及一第三光阻層。 步驟S6 :形成源極427、汲極428及該資料線426 ; 提供一第三光罩對該第三光阻層進行曝光顯影,從而形 成一預定之第三光阻圖案;以第三光阻圖案為阻擋物對該源 /汲極金屬層進行蝕刻,進而形成該源極427、該汲極428及 該資料線426,移除第三光阻圖案。 步驟S7 :形成鈍化層429 ; 15 1377368 於該閘極絕緣層424、源極447、汲極448、該資料線 426及該半導體圖案423上依序沈積形成該鈍化層424及一 第四光阻層。 步驟S8:形成貫穿該鈍化層424之第一通孔433及第二 通孔434 ; 提供一第四光罩對該第四光阻層進行曝光顯影,從而形 成一預定第四光阻圖案;以第四光阻圖案為阻擋物對該鈍化 層424進行钱刻,進而形成該第一通孔433及該第二通孔 434,移除第四光阻圖案。 步驟S9 :形成一透明導電層; 於該鈍化層424上及該二通孔433、434内形成一透明 導電層層及一第五光阻層。 步驟S10 :形成公共電極431及像素電極430 ; 提供一第五光罩對該第五光阻層進行曝光顯影,從而形 成一預定之第五光阻圖案;以第五光阻圖案為阻擋物對該透 明導電層進行蝕刻,進而定義出該公共電極431及像素電極 430之圖案,移除第五光阻圖案。 步驟S11 :形成親油性絕緣層圖案432 ; 於該像素電極430上形成該親油性絕緣層圖案432。 請參閱圖8,係本發明電濕潤式顯示裝置第二實施方式 之局部結構剖視示意圖。該電濕潤式顯示裝置5與該電濕潤 式顯示裝置4大體相同,其主要區別在於:該電濕潤式顯示 裝置5為反射式顯示裝置,其薄膜電晶體基板52之像素電 極530由反射率較高的金屬鋁(A1)製成。 16 1377368 該薄膜電晶體基板52之製造方法與該薄膜電晶體基板 42之製造方法大體相同,該薄膜電晶體基板52之製造方法 為: 步驟S1 :形成閘極金屬層; 步驟S2 :形成閘極521、掃描線(圖未示)及電容電極線 523 ; 步驟S3 :形成閘極絕緣層524及半導體層; 步驟S4 :形成半導體圖案525 ; 步驟S5 :形成源/汲極金屬層; 步驟S6 :形.成源極527、汲極528及該資料線526 ; 步驟S7 :形成鈍化層529 ; 步驟S8:形成貫穿該鈍化層524之第一通孔533及第二 通孔534 ; 步驟S9:形成一透明導電層; 步驟S10 :形成公共電極531 ; 步驟S11 :形成一金屬鋁層; 於該鈍化層524上、該公共電極531及該第一通孔533 内依序形成一金屬銘層及一第六光阻層。 步驟S12 :形成像素電極530 ; 提供一第六光罩對該第六光阻層進行曝光顯影,從而形 成一預定之光阻圖案;對該金屬鋁層進行蝕刻,進而定義出 該像素電極530之圖案,移除第六光阻層。 步驟S13 :形成親油性絕緣層圖案532。 請參閱圖9,係本發明電濕潤式顯示裝置第三實施方式 17 1377368 之結構示意圖。該電濕潤式顯示裝置6與該電濕潤式顯示裝 置5大體相同,其主要區別在於:該電濕潤式顯示裝置6之 薄膜電晶體基板62之像素電極630為多層結構。該像素電 極630包括一設置於該鈍化層624上之連接層651、一設置 於該連接層651上之阻障層652、一設置於該阻障層652上 之反射層653及一設置於該反射層653上之保護層654。該 連接層651由質地較堅固之氧化銦錫製成,該反射層653由 反射率較高的金屬鋁製成,該阻障層652由與氧化銦錫及鋁 均化學穩定之鉬(Mo)製成,該保護層654由化學性質穩定 且透光率較高之氧化鋁(A1203)製成。 相較與第一實施方式,由於該電濕潤式顯示裝置6之像 素電極630為多層結構,該連接層651可以使該反射電極630 電連接更為可靠,該保護層654可以防止該反射層653被腐 蝕,故該電濕潤式顯示裝置6可靠性更佳。 該薄膜電晶體基板62之製造方法與該薄膜電晶體基板 52之製造方法大體相同,該薄膜電晶體基板62之製造方法 為: 步驟S1 :形成閘極金屬層; 步驟S2 :形成閘極621、掃描線(圖未示)及電容電極線 623 ; 步驟S3 :形成閘極絕緣層624及半導體層; 步驟S4 :形成半導體圖案625 ; 步驟S5 :形成源/汲極金屬層; 步驟S6 :形成源極627、汲極628及該資料線626 ; 18 1377368 步驟S7 :形成鈍化層629 ; 步驟S8:形成貫穿該鈍化層624之第一通孔623及第二 通孔634 ; 步驟S9 :形成一透明導電層; 步驟S10 :形成公共電極631及該連接層651 ; 步驟S11:依序形成一金屬鉬層、一金屬鋁層及一氧化 鋁層; ^ 於該鈍化層624上、該公共電極631及該連接層651上 依序形成一金屬鉬層及一金屬鋁層。其中該金屬鋁層為純鋁 材質’厚度為1000A。爾後置於大氣壓化學氣相沈積 (Atmospheric Pressure Chemical Vapor Deposition, APCVD) 或電聚辅助化學氣相沈積(Plasma Enhanced Chemical Vapor Deposition,PECVD)之氣室(Chamber)中並通入氧氣以產生 氧電漿,利用該氧電漿與該純鋁材料進行化學反應,於該純 鋁表面形成一氡化鋁(A1203)層,操作溫度於25至600攝氏 秦度間,壓力約為1.333x104至6.555xl04N/m2,操作時間小 於等於1分鐘。於該氧化鋁層表面沈積一第六光阻層。其中, 該氧電漿力量的作用可以使該純鋁表面自然形成的突起平 坦化。 步驟S12 :形成像素電極630 ; 提供一第六光罩對該第六光阻層進行曝光顯影,從而形 成一預定之光阻圖案;對該金屬鉬層及金屬鋁層進行蝕刻, 進而定義出該阻障層652、該反射層653及該保護層654, 進而形成該像素電極630,移除第六光阻層。 步驟S13 :形成親油性絕緣層圖案632 β .裝置=一 t參閲圖1〇及圖丄1,圖1〇係本發明電濕潤式顯示 " 四實施方式之局部結構剖視示意圖。圖11係圖10所 ^濕润式顯Μ之薄膜電晶體基板72之局部結構平面示 ::=電濕潤式顯示裝置7與該電濕潤式顯示裝置4大體 2其主要區別在於:該電濕潤式顯示裝置7之薄 體基板72句杠% ^ 括一接觸區782及位於該二接觸區782間之一 • 區:81。* 一接觸區782設置有-公共電極731。該至 )電谷電極線723自一接觸區782延伸至另一接觸區 782 ^每一公共電極731電連接至該電容電極線723。 °° —相車父於第一實施方式,由於該電濕潤式顯示裂置7之電 谷電極線723與該第一液體75並聯,故該電濕潤式顯示裝 置7之公共電壓均勻性較佳。 綜上所述’本發明確已符合發明之要件,纽法提出專 利申請。惟’以上所㈣僅為本發明之較佳實财式,本發 鲁明之範圍並PX上特财式輕,舉凡熟_本案技藝之又 士援依本發明之精神所作之等效修飾或變化,皆應涵蓋於以 下申請專利範圍内。 【圖式簡單說明】 圖1係一種先前技術揭示的基於電濕潤原理的反射式顯 示裝置的平面結構示意圖。 圖2係圖1所示顯示裝置之—像素的放大剖視結構示意 圖。 圖3係圖2所示像素亮態結構示意圖。 1377368 圖4係本發明電濕潤式顯示裝置第一實施方式之局部結 構示意圖。 圖5係圖4所示電濕潤式顯示裝置薄膜電晶體基板之平 面結構局部示意圖。 圖ό係圖5所示薄膜電晶體基板沿vi-VI方向剖視示咅、 圖。 圖7係圖6所示薄膜電晶體基板之製造流程圖。 圖8係本發明電濕潤式顯示裝置.第二實施方式之局部結 構剖視示意圖。 ° ~ 意圖 圖9係本發明電濕潤式顯示裝置第三實施方式之結構示 圖Η)係本發明電濕潤式顯示裝置第四實施方式 結構剖視示意圖。 圖 圖U係圖Η)所示電濕潤式顯示I之局部結構平 面示意 •【主要元件符號說明】 電濕潤式顯示裝置 像素區 4、5、6 ' 7 ,向基板 40 薄膜電晶體基板 41 間隔壁 42、52 第一液體 43 第二液體 45、75 第—區域 46 樞膠 48 基底 49 420 21 1377368 • 閘極 掃描線 . 電容電極線 閘極絕緣層 半導體圖案 資料線 源極 汲極 純化層 像素電極 •公共電極 親油性絕緣層圖案 第一通孔 第二通孔 第一收容空間 第二收容空間 顯不區 接觸區 連接層 Φ 阻障層 反射層 保護層 421 、 521 、 621 422 423、523、623、723 424 ' 524 ' 624 425 ' 525 ' 625 426 、 526 、 626 427 ' 527 ' 627 428 、 528 、 628 429 、 529 、 629 430 、 530 、 630 431、531、631、731 432、532、632 433 > 533 ' 633 434、534、634 441 442 481 、 781 482 ' 782 651 652 653 654 221377368 IX. Description of the Invention: The present invention relates to a thin film transistor substrate, a thin film transistor substrate manufacturing method, and an electrowetting display device. [Prior Art] Today, many optoelectronic technologies are rapidly developing and applied to next-generation flat panel displays such as Projection Display and Flexible Dispaly. In this environment, a display device based on the electrowetting principle has received wide attention due to its fast response speed, wide viewing angle, low power consumption, and light and portable. Referring to FIG. 1, a schematic diagram of a planar structure of a reflective display device based on the electrowetting principle disclosed in the prior art. The display device 1 includes a plurality of pixels 10 arranged in a matrix, and the pixels 10 are controlled to display different gray scales to constitute the surface to be displayed by the display device 1. Referring to FIG. 2, an enlarged cross-sectional structural view of a pixel 10 of the display device 1 shown in FIG. The pixel 10 includes a pair of substrates 11 , a thin film transistor substrate 12 opposite thereto, and four partition walls 13 disposed between the two substrates 11 and 12 . The four partition walls 13 are sequentially connected end to end and the two The substrates 11, 12 form a receiving space 14. The opposite substrate 11 is made of a light transmissive material such as glass or plastic. A common electrode 111 is disposed on the surface of the opposite substrate 11 adjacent to the receiving space 14, and the common electrode 111 is made of a transparent conductive material. The accommodating space 14 is filled with a first liquid 15 and a second liquid 16 which are incompatible with each other. For example, the first liquid 15 can be electrically conductive 6 1377368 'water, and the second liquid 16 can be black oil. The thin film transistor substrate 12 is sequentially disposed adjacent to the surface of the receiving space 14 with an active component (not shown), a reflective electrode 121 and an insulating layer 122. Since the reflective electrode 121 is made of pure aluminum, it has a high reflectance. The insulation 122 is made of a hydrophobic material such as an amorphous fluoropolymer (Amorphous Fluoropolymer). Due to the hydrophobicity of the insulating layer 122, that is, under the surface tension (Interfacial • Tension) between the insulating layer 122, the first liquid 15 and the second liquid 16, the second liquid 16 sufficiently covers the insulating layer. 122. Since the second liquid 16 is black, it absorbs most of the light beam incident from the opposite substrate 11, so that the pixel 10 at this time is in an off state. Please refer to FIG. 3 together, which is a schematic diagram of the bright state of the pixel 10 shown in FIG. When a voltage difference is applied between the common electrode 111 and the reflective electrode 121, the voltage of the first liquid 15 and the common electrode 111 is the same because the first liquid 15 is in contact with the common electrode 111. The attraction force of the opposite charges carried by the first liquid 15 and the reflective electrode 121 destroys the equilibrium state of the molecular tension in the dark state, that is, the intervention of the potential energy causes the insulating layer 122 and the first liquid 15 to tend to Contacting, the first liquid 15 discharges the second liquid 16 so that the light beam incident from the opposite substrate 11 is reflected by the reflective electrode 121 corresponding to the discharged portion to achieve a bright state (On State). However, since a driving circuit (not shown) for providing a voltage difference between the common electrode 111 and the reflective electrode 121 is usually disposed on the thin film transistor substrate 12, the driving circuit located on the thin film transistor substrate 12 needs to be located opposite to each other. The common electrode 111 of the substrate 11 is electrically connected, so that the structure of the display device 1 is complicated. At the same time, the public _^ $ electric 稂 111 has a certain absorption effect first, so that the light utilization rate of the display device 1 is lowered, and the optical quality is poor. SUMMARY OF THE INVENTION (10) It is necessary to provide an electrowetting display device which is simple in structure and excellent in optical quality. It is also necessary to use a thin film transistor for the electrowetting display device. Lu-type thin film transistor substrate, comprising: a display area, at least a contact area located on the display area to the side, a surrounding the display area and the contact area, and used for: (4) setting area, plural setting The pixel electrode of the display area and the at least one of the at least one of the contact regions are disposed, and the thin film transistor substrate exposes at least a portion of the at least one common electrode. An electrowetting display device comprising a pair of substrates, a thin film transistor substrate disposed opposite to the opposite substrate, and disposed between the opposite substrate and the thin film transistor substrate and the opposite substrate The thin film transistor substrate Φ is formed to form a sealant in a receiving space, a first liquid having a polarity disposed in the receiving space, and a non-polar one not integrated with the first liquid and disposed in the receiving space a second liquid, wherein the thin film transistor substrate comprises at least one contact region in a region defined by the sealant in the thin film transistor substrate, and a display region in a region defined by the sealant in the thin film transistor substrate, a pixel electrode disposed in the display area, a lipophilic insulating layer pattern disposed on the pixel electrode, and at least one male/electrode disposed on the at least one contact region, and the thin film transistor substrate exposes the at least one common At least a portion of the electrode. 1377368 * A thin film transistor substrate, comprising: a first region, a sealant setting region for providing a sealant on a periphery of the first region, a plurality of pixel electrodes disposed in the first region, and at least one disposed on the a common electrode in the first region, the common electrode is insulated from the pixel electrode, and the thin film transistor substrate exposes at least a portion of the at least one common electrode. An electrowetting display device comprising a pair of substrates, a thin film transistor substrate disposed opposite the opposite substrate, disposed between the opposite substrate and the thin film transistor substrate, and the opposite substrate and the The thin film transistor substrate is formed to form a frame of a receiving space, a plurality of partition walls disposed on the opposite substrate and the thin film transistor substrate, a first liquid disposed in the receiving space, and a second a liquid, the sealant defines a first region on the thin film transistor substrate, the partition wall is located in the first region, and the second liquid is located in a region defined by the partition wall, wherein the thin film transistor substrate comprises a setting a plurality of pixel electrodes in the region defined by the partition wall and at least one common electrode disposed in the first region, the common electrode and the pixel electrode are separated from each other, and the thin film transistor substrate exposes the at least one common electrode At least part of it. A method for manufacturing a thin film transistor substrate, comprising the steps of: providing a substrate; forming at least one capacitor electrode line and a plurality of scan lines on the substrate; forming a first insulation on the capacitor electrode line, the scan line and the substrate Forming a plurality of data lines on the first insulating layer; forming a passivation layer on the first insulating layer and the data line; forming a through hole penetrating the passivation layer and the first insulating layer corresponding to the position of the capacitor electrode line Forming a common electrode and a plurality of pixel electrodes on the passivation layer, such that the common electrode is electrically connected to the capacitor 1377368 electrode line through the through hole; forming a lipophilic insulating layer pattern on the pixel electrode, and exposing At least one portion of the at least one common electrode. A thin film transistor substrate comprising a substrate, a plurality of gate electrodes, a plurality of scan lines and a plurality of capacitor electrode lines disposed on the substrate, a plurality of gate electrodes, the scan lines, the capacitor electrode lines and the substrate a gate insulating layer, a semiconductor pattern and a plurality of data lines disposed on the gate insulating layer, a plurality of source and a plurality of drain electrodes disposed on the semiconductor pattern and the gate insulating layer, and a gate is disposed on the gate An insulating layer, the data line, the source, the drain and the passivation layer on the semiconductor pattern, a plurality of pixel electrodes disposed on the passivation layer, a common electrode, and a lipophilic insulating layer disposed on the pixel electrode a pattern, the thin film transistor substrate exposing at least a portion of the at least one common electrode. An electrowetting display device comprising a pair of substrates, a thin film transistor substrate disposed opposite the opposite substrate, disposed between the opposite substrate and the thin film transistor substrate, and the opposite substrate and the The thin film transistor substrate is formed to form a frame sealant, a first liquid of a polarity disposed in the receiving space, and a non-polar second liquid disposed in the receiving space, wherein the thin film transistor substrate The invention comprises a substrate, a plurality of gates disposed on the substrate, a plurality of scan lines and a plurality of capacitor electrode lines, a gate insulating layer disposed on the plurality of gates, the scan lines, the capacitor electrode lines and the substrate, and a setting a semiconductor pattern and a plurality of data lines on the gate insulating layer, a plurality of source and a plurality of drain electrodes disposed on the semiconductor pattern and the gate insulating layer, and a gate insulating layer, the data line, a source, a drain, a passivation layer on the semiconductor pattern, a plurality of pixels 1377368 disposed on the passivation layer, a common electrode, and a common electrode disposed on the pixel electrode Oily insulating layer pattern, the thin film transistor substrate exposed out of the at least one of the at least a portion of the common electrode. A method for manufacturing a thin film transistor substrate, comprising the steps of: providing a substrate; forming a plurality of gates, a plurality of scan lines, and a plurality of capacitor electrode lines on the substrate; and the plurality of gates, the scan lines, the capacitor electrode lines, and the Forming a gate insulating layer on the substrate; forming a semiconductor pattern and a plurality of data lines on the gate insulating layer; forming a plurality of source and a plurality of drain electrodes on the semiconductor pattern and the gate insulating layer; and insulating the gate Forming a passivation layer on the layer, the source, the drain, and the semiconductor pattern; forming a plurality of pixel electrodes and a common electrode on the passivation layer; forming a lipophilic insulating layer pattern on the pixel electrode, And exposing at least a portion of the at least one common electrode. Compared with the prior art, the electrowetting display device of the present invention has a common electrode and a pixel electrode on the thin film transistor substrate, and does not need to connect the common voltage to the opposite substrate, and is not used for display. The light beam has an influence, so the electrowetting display device has a simple structure and a good optical quality. Compared with the prior art, the thin film transistor substrate and the thin film transistor substrate manufacturing method of the present invention have a common electrode and a pixel electrode on the thin film transistor substrate, and the common voltage is not required to be connected to other substrates. The transistor substrate is convenient to use. [Embodiment] Please refer to Fig. 4, which is a partial structural view of a first embodiment of an electrowetting display device according to the present invention. The electrowetting display device 4 is a transmissive display device comprising a pair of substrates 41, a 11 1377368 thin film transistor substrate 42 disposed opposite the opposite substrate 41, and a counter substrate 41 and the thin film. a sealant 49 between the crystal substrate 42 , a plurality of partition walls 43 arranged in a row and row between the opposite substrate 41 and the thin film transistor substrate 42 , and a backlight module disposed adjacent to the thin film transistor substrate 42 (not shown). The thin film electromorph substrate 42 includes a sealant setting area (not shown). The sealant 49 is disposed in the sealant setting area and abuts the two substrates 41 and 42 and cooperates with the two substrates 41 and 42 to form a closed first receiving space 441, and the sealant 49 is on the thin film transistor substrate. 42 defines a first area 48. The first area 48 includes a display area 481 and a contact area 482. The partition wall 43 is disposed on the display area 481 of the thin film transistor substrate 42 and defines a plurality of pixel regions 40 arranged in a matrix, and the partition wall 43 cooperates with the thin film transistor substrate 42 to form a plurality of second receiving spaces 442. The height of the partition wall 43 is smaller than the height of the sealant 49. The first receiving space 441 is filled with a first liquid 45 and a second liquid 46 which are incompatible with each other. The second liquid 46 is located in each of the second receiving spaces 442, and the height of the second liquid 46 relative to the thin film transistor substrate 42 is smaller than the height of the partition wall 43. The first liquid 45 may be a conductive liquid such as water or a salt solution or a polar liquid such as a solution in which potassium chloride (KC1) is dissolved in a mixture of water and an ordinary alcohol (Ethyl Alcohol). The second liquid 46 may be a non-polar liquid such as a black alkane or an alkane (Alkane) such as Hexadecane or oil as a masking liquid. 5 and FIG. 6, FIG. 5 is a partial schematic view showing the planar structure of the thin film transistor substrate 42 of the electrowetting display device 4 shown in FIG. 4, and FIG. 6 is the thin film transistor substrate 42 shown in FIG. A schematic cross-sectional view. The thin film transistor substrate 42 includes a glass substrate 420, a plurality of gate electrodes 421 disposed on the substrate 12 Ϊ 377 368 42 、, a plurality of scanning lines 422 spaced apart from each other, and a capacitor electrode line 423 spaced apart from each other. a gate insulating layer 424 disposed on the gate electrode 421, the scan line 422, and the capacitor electrode line 423, a semiconductor pattern 425 disposed on the inter-electrode insulating layer 424, and a plurality of tributary lines 426 spaced apart from each other a plurality of source electrodes 427 and a plurality of drain electrodes 428 disposed on the semiconductor pattern 425 and the gate insulating layer 424, and a gate electrode, a boundary layer 424, the data line 426, the source electrode 427, and the gate electrode The passivation layer 429 on the pole 428 and the semi-conductor pattern 425, the plurality of pixel electrodes 430 and a common electrode 431 disposed on the passivation layer 429, and a lipophilic insulating layer pattern 432 disposed on the pixel electrode 430. The data line 426 is parallel to the boundary line between the display area 481 and the contact area 482. The scan line 422 and the data line 426 are perpendicular to each other. Each scan line 422 and each data line 426 correspond to a partition wall 43 and are sandwiched between the partition wall u and the substrate 420. Two adjacent scan lines 422 and two phases The smallest area defined by the adjacent data line a% crosses corresponds to the pixel area 4G. The capacitor electrode line 423 extends from the contact region 482 to the display region 481 and is alternately disposed with the scan line such that each capacitor electrode line 423 passes through a row of pixel regions 4 〇. Each of the gates 421, each of the source electrodes 427, each of the drain electrodes 428, and each of the pixel electrodes 43A corresponds to a pixel region 40. The gate electrode 421 is electrically connected to the corresponding scan core 2, and the source electrode 427 is electrically connected. To the corresponding data line 426, the drain 428 is electrically connected to the corresponding pixel electrode 430 by a first via 433 extending through the passivation layer 429. The common electrode 431 is located in the contact region 482 and is electrically connected to the capacitor electrode line 423 via a second via 434 extending through the passivation layer 429 and the gate insulating layer 424. The common electrode 431 and the pixel electrode 43 are made of a transparent material 13 1377368' to be made of oxidized __) or indium zinc oxide (IZ0). For each pixel region 40, the gate electrode 421, the gate insulating layer (4), the semiconductor pattern 425, the full weight jh pole 427 and the drain 428 are combined to form a thin film transistor 'for controlling the pair of seats + The pixel electrode 430 corresponding to the pixel electrode 430 is charged or not charged; the capacitor electrode line passing through the pixel region 40, the closed electrode insulating layer 424, the purification layer 429 and the pixel electrode 43 are stacked to form a storage capacitor for Maintaining the electric power of the pixel electrode 430. When the electrowetting display device 4 is operated, the common electrode 431 is applied with a common voltage 'each pixel electrode 43' is applied with a corresponding gray scale voltage. Since the common electrode 431 is in contact with the first liquid 45 located in the contact region 482, the first liquid 45 can be electrically connected to the common electrode 431 to have the same voltage as the common electrode 431. The first liquid 45 is controlled to discharge the second liquid 46 by changing the magnitude of the gray scale voltage applied to each of the pixel electrodes 43A to cause the electrowetting display device 4 to normally display an image. Compared with the prior art, the electrowetting display device 4 of the present invention has a common common electrode 431 and a pixel electrode 430 located on the thin film transistor substrate 42 without guiding a common voltage to the opposite substrate 41. The structure of the electrowetting display device 4 is relatively simple. Moreover, since the common electrode 431 is located beside the pixel region 40, it does not affect the light beam passing through the pixel region 4, so the electrowetting display device 4 has better optical quality. Referring to Fig. 7, a flow chart for manufacturing the thin film transistor substrate 42 shown in Fig. 6 is shown. The manufacturing method of the thin film transistor substrate 42 includes the following steps: Step S1: forming a gate metal layer; providing a glass substrate 420 on which a gate 1377368 metal layer and a first photoresist layer are sequentially formed. Step S2: forming a gate 421, a scan line 422, and a capacitor electrode line 423; providing a first mask to expose and develop the first photoresist layer to form a predetermined first photoresist pattern; The pattern is a barrier to etch the gate metal layer to form a pattern of the gate 421, the scan line 422 and the capacitor electrode line 423, and the first photoresist pattern is removed. Step S3: forming a gate insulating layer 424 and a semiconductor layer; forming the gate insulating layer 424, a semiconductor layer, and a second on the gate electrode 421, the scan line 422, the capacitor electrode line 423, and the glass substrate 420. Photoresist layer. Step S4: forming a semiconductor pattern 425; providing a second mask to expose and develop the second photoresist layer to form a predetermined second photoresist pattern; and using the second photoresist pattern as a barrier to the doping The germanium layer and the amorphous germanium layer are etched to form the semiconductor pattern 425, and the second photoresist pattern is removed. Step S5: forming a source/drain metal layer; forming a source/dano metal layer and a third photoresist layer on the glass substrate 420 and the semiconductor pattern 425. Step S6: forming a source 427, a drain 428 and the data line 426; providing a third mask to expose and develop the third photoresist layer to form a predetermined third photoresist pattern; The pattern is a barrier to etch the source/drain metal layer to form the source 427, the drain 428, and the data line 426 to remove the third photoresist pattern. Step S7: forming a passivation layer 429; 15 1377368 sequentially depositing the passivation layer 424 and a fourth photoresist on the gate insulating layer 424, the source 447, the drain 448, the data line 426, and the semiconductor pattern 423. Floor. Step S8: forming a first through hole 433 and a second through hole 434 penetrating the passivation layer 424; providing a fourth mask to expose and develop the fourth photoresist layer to form a predetermined fourth photoresist pattern; The fourth photoresist pattern is a barrier for the passivation layer 424 to form the first via 433 and the second via 434 to remove the fourth photoresist pattern. Step S9: forming a transparent conductive layer; forming a transparent conductive layer and a fifth photoresist layer on the passivation layer 424 and the two via holes 433 and 434. Step S10: forming a common electrode 431 and a pixel electrode 430; providing a fifth mask to expose and develop the fifth photoresist layer to form a predetermined fifth photoresist pattern; and using the fifth photoresist pattern as a barrier pair The transparent conductive layer is etched to define a pattern of the common electrode 431 and the pixel electrode 430 to remove the fifth photoresist pattern. Step S11: forming a lipophilic insulating layer pattern 432; forming the lipophilic insulating layer pattern 432 on the pixel electrode 430. Referring to Figure 8, there is shown a partial cross-sectional view of a second embodiment of the electrowetting display device of the present invention. The electrowetting display device 5 is substantially the same as the electrowetting display device 4. The main difference is that the electrowetting display device 5 is a reflective display device, and the pixel electrode 530 of the thin film transistor substrate 52 has a higher reflectance. Made of high metal aluminum (A1). 16 1377368 The method for manufacturing the thin film transistor substrate 52 is substantially the same as the method for manufacturing the thin film transistor substrate 42. The method for manufacturing the thin film transistor substrate 52 is as follows: Step S1: forming a gate metal layer; Step S2: forming a gate 521, a scan line (not shown) and a capacitor electrode line 523; Step S3: forming a gate insulating layer 524 and a semiconductor layer; Step S4: forming a semiconductor pattern 525; Step S5: forming a source/drain metal layer; Step S6: Forming a source 527, a drain 528 and the data line 526; Step S7: forming a passivation layer 529; Step S8: forming a first via 533 and a second via 534 extending through the passivation layer 524; Step S9: forming a transparent conductive layer; step S10: forming a common electrode 531; step S11: forming a metal aluminum layer; forming a metal layer and a layer on the passivation layer 524, the common electrode 531 and the first via 533 The sixth photoresist layer. Step S12: forming a pixel electrode 530; providing a sixth mask to expose and develop the sixth photoresist layer to form a predetermined photoresist pattern; etching the metal aluminum layer to define the pixel electrode 530 Pattern to remove the sixth photoresist layer. Step S13: forming a lipophilic insulating layer pattern 532. Please refer to FIG. 9, which is a schematic structural view of a third embodiment 17 1377368 of the electrowetting display device of the present invention. The electrowetting display device 6 is substantially the same as the electrowetting display device 5. The main difference is that the pixel electrode 630 of the thin film transistor substrate 62 of the electrowetting display device 6 has a multilayer structure. The pixel electrode 630 includes a connection layer 651 disposed on the passivation layer 624, a barrier layer 652 disposed on the connection layer 651, a reflective layer 653 disposed on the barrier layer 652, and a reflective layer 653 disposed thereon. A protective layer 654 on the reflective layer 653. The connection layer 651 is made of a relatively strong indium tin oxide, the reflective layer 653 is made of metal aluminum having a high reflectivity, and the barrier layer 652 is made of molybdenum (Mo) which is chemically stable with both indium tin oxide and aluminum. The protective layer 654 is made of alumina (A1203) which is chemically stable and has a high light transmittance. Compared with the first embodiment, since the pixel electrode 630 of the electrowetting display device 6 has a multi-layer structure, the connection layer 651 can make the reflective electrode 630 electrically connected more reliably, and the protective layer 654 can prevent the reflective layer 653 from being prevented. Corroded, the electrowetting display device 6 is more reliable. The method for manufacturing the thin film transistor substrate 62 is substantially the same as the method for manufacturing the thin film transistor substrate 52. The method for manufacturing the thin film transistor substrate 62 is as follows: Step S1: forming a gate metal layer; Step S2: forming a gate 621, a scan line (not shown) and a capacitor electrode line 623; Step S3: forming a gate insulating layer 624 and a semiconductor layer; Step S4: forming a semiconductor pattern 625; Step S5: forming a source/drain metal layer; Step S6: forming a source a pole 627, a drain 628 and the data line 626; 18 1377368 step S7: forming a passivation layer 629; step S8: forming a first via 623 and a second via 634 extending through the passivation layer 624; step S9: forming a transparent a conductive layer; Step S10: forming a common electrode 631 and the connection layer 651; Step S11: sequentially forming a metal molybdenum layer, a metal aluminum layer and an aluminum oxide layer; ^ on the passivation layer 624, the common electrode 631 and A metal molybdenum layer and a metal aluminum layer are sequentially formed on the connection layer 651. The metal aluminum layer is made of pure aluminum and has a thickness of 1000A. Then placed in a chamber of Atmospheric Pressure Chemical Vapor Deposition (APCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) and oxygen is introduced to generate oxygen plasma. The oxygen plasma is chemically reacted with the pure aluminum material to form an aluminum (A1203) layer on the surface of the pure aluminum. The operating temperature is between 25 and 600 degrees Celsius, and the pressure is about 1.333x104 to 6.555xl04N/ M2, the operation time is less than or equal to 1 minute. A sixth photoresist layer is deposited on the surface of the aluminum oxide layer. Wherein, the action of the oxygen plasma force can make the protrusion naturally formed on the surface of the pure aluminum flat. Step S12: forming a pixel electrode 630; providing a sixth mask to expose and develop the sixth photoresist layer to form a predetermined photoresist pattern; etching the metal molybdenum layer and the metal aluminum layer to define the The barrier layer 652, the reflective layer 653 and the protective layer 654 further form the pixel electrode 630 to remove the sixth photoresist layer. Step S13: forming a lipophilic insulating layer pattern 632 β. Device = a t Refer to FIG. 1 and FIG. 1 , and FIG. 1 is a schematic cross-sectional view showing a partial structure of the electrowetting display of the present invention. 11 is a partial structural plan view of the wet-type thin film transistor substrate 72 of FIG. 10::= The electrowetting display device 7 and the electrowetting display device 4 are substantially different in that: the electrowetting The thin body substrate 72 of the display device 7 has a contact area 782 and a region between the two contact areas 782. * A contact area 782 is provided with a common electrode 731. The electric valley electrode line 723 extends from a contact region 782 to another contact region 782. Each common electrode 731 is electrically connected to the capacitor electrode line 723. In the first embodiment, since the electric valley electrode line 723 of the electrowetting display crack 7 is connected in parallel with the first liquid 75, the common voltage uniformity of the electrowetting display device 7 is better. . In summary, the present invention has indeed met the requirements of the invention, and Newfa has filed a patent application. However, the above (4) is only the preferred real financial formula of the present invention, the scope of the present Luming and the special wealth of the PX, and the equivalent modification or change of the skill of the present invention in accordance with the spirit of the present invention. All should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing the structure of a reflective display device based on electrowetting principle disclosed in the prior art. Fig. 2 is a schematic cross-sectional structural view showing a pixel of the display device shown in Fig. 1. FIG. 3 is a schematic diagram showing the structure of the pixel in a state shown in FIG. 1377368 Fig. 4 is a partial structural view showing the first embodiment of the electrowetting display device of the present invention. Fig. 5 is a partial schematic view showing the planar structure of the thin film transistor substrate of the electrowetting display device shown in Fig. 4. Figure 5 is a cross-sectional view of the thin film transistor substrate shown in Figure 5 taken along the vi-VI direction. Fig. 7 is a flow chart showing the manufacture of the thin film transistor substrate shown in Fig. 6. Figure 8 is a cross-sectional view showing a partial structure of a second embodiment of the electrowetting display device of the present invention. Fig. 9 is a structural view showing a third embodiment of the electrowetting display device of the present invention. Fig. 9 is a cross-sectional view showing a fourth embodiment of the electrowetting display device of the present invention. Figure U is a schematic diagram showing the local structure of the electrowetting display I. [Key element symbol description] Electro-wet display device pixel area 4, 5, 6 ' 7 , to the substrate 40 thin film transistor substrate 41 Partition wall 42, 52 First liquid 43 Second liquid 45, 75 First-area 46 Puncture 48 Substrate 49 420 21 1377368 • Gate scan line. Capacitance electrode line gate insulation semiconductor pattern data line source depolarization purification layer pixel Electrode/common electrode lipophilic insulating layer pattern first through hole second through hole first receiving space second receiving space display area contact area connecting layer Φ barrier layer reflective layer protective layer 421, 521, 621 422 423, 523, 623,723 424 ' 524 ' 624 425 ' 525 ' 625 426 , 526 , 626 427 ' 527 ' 627 428 , 528 , 628 429 , 529 , 629 430 , 530 , 630 431 , 531 , 631 , 731 432 , 532 , 632 433 > 533 ' 633 434, 534, 634 441 442 481 , 781 482 ' 782 651 652 653 654 22

Claims (1)

1377368 第97116297號專利申請案補充、修正無劃線之申請專利範圍替換頁 修正日期:101年09月 十、申請專利範圍 1^1 m 曰修正本 1. 一種薄膜電晶體基板,其包括: 一顯示區; 至少一接觸區,其位於該顯示區至少一側; 一框膠設置區5其包圍該顯不區及該接觸區,用於設置框 膠; 複數像素電極,設置於該顯示區;及 至少一公共電極,設置於該至少一接觸區,且該薄膜電晶 體基板裸露出該至少一公共電極之至少一部份。 2. 如申請專利範圍第1項所述之薄膜電晶體基板,其中,該 薄膜電晶體基板進一步包括至少一電容電極線,該至少一 電容電極線與該像素電極絕緣層疊,該至少一公共電極與 該至少一電容電極線電連接。 3. 如申請專利範圍第2項所述之薄膜電晶體基板,其中,該 至少一電容電極線自該至少一接觸區延伸至該顯示區。 4. 如申請專利範圍第1項所述之薄膜電晶體基板,其中,該 薄膜電晶體基板所包括之該至少一接觸區之數量為二 個,該薄膜電晶體基板所包括之該至少一公共電極之數量 為二個,該二接觸區分別設置於該顯示區相對二側,每一 該接觸區設置有一該公共電極。 5. 如申請專利範圍第4項所述之薄膜電晶體基板,其中,該 薄膜電晶體基板進一步包括至少一電容電極線,該至少一 電容電極線與該像素電極絕緣層疊,該二公共電極與該至 少一電容電極線電連接。 23 1377368 6.2請專利範圍第】項所述之薄” 像素電極由至少一種材質 —基板,其令,該 種材質與該至少—公北 1請素電極中有至少一 7 . ώ 〆、电極之材質相同〇 .如申請專利範圍第6項所述 像素電極及該至少一公共#極體基板,其中,該 化銦辞。 貝同為氧化銦錫或氧 8.:Γ=:範圍第6項所述之薄膜電晶體基板,μ,, 像素電極為一多層結構 板/、令,该 層上之阻障#、一⑼署认 接層、一設置於連接 兮;^層該阻障層上之反射層及一設置於 =鋅1上之保護層’該連接層之材質為氧化銦錫或氧化 護層之該反㈣之材f為銘’該保 層之材質相同ό化紹°亥至少一公共電極之材質與該連接 ★申二專利範圍S 1項所述之薄膜電晶體基板,其令,該 極之材質為銘’該至少—公共電極之材質為氧化鋼 錫或氧化銦鋅。 1 〇.種電濕潤式顯示裝置,其包括·· 一對向基板; 薄膜電晶體基板,其與該對向基板相對設置; 才匡膠’其設置於該對向基板及該薄膜電晶體基板之間, 並與5亥對向基板及該薄膜電晶體基板配合形成一收容空 間; 極性之第—液體,其設置於該收容空間内;及 與5亥第一液體不相融之非極性之第二液體,其設置於該 24 1377368 收容空間内; 其中,該薄膜電晶體基板包括: 至少-接觸區及-顯示區,該至少—接觸區及該 =該轉於該薄膜電晶體基板界定之區域内;… 複數像素電極,設置於該顯示區; -親油性絕緣層圖案’設置於該像素電極,及 至少一公共電極,設置於該至少一接觸區 體基板裸露出該至少一公共電極之至少一部份:晶 申請專利範圍第10項所述之電濕潤式顯示褒置,1 中’該至少一公共電極與該第一液體 : 與該第-液體相絕緣。 接觸錢素電極 2=申睛專職圍第1()項所述之電濕潤式顯 I:該=晶體基板進一步包括至少-電容電極線,該 v 电今电極線與該像素電極絕緣層疊,該至少—八/ 電極與該至少一電容電極線電連接。 夕么共 13.如申請專利範圍第12項所述之電濕潤式顯示裝置,1 ^該至少-電容電極線自該至少_接觸區延伸至該顯^ 如申請專利範圍帛10 $所述之電濕潤式顯示裝置,盆 中,該薄膜電晶體基板所包括之該之至少一接觸區之數2 為二個,該薄膜電晶體基板所包括之該至少一里 如曰JA A六电極之 為二個,該二接觸區分別設置於該顯示區相對二側, 务一该接觸區設置有一該公共電極。 1S.如申請專利範圍第14項所述之電濕潤式顯示裝置,其 25 中,該薄膜電晶體基板進— 至少—恭A + h ώ 步包括至少一電容電極線,該 ㈣至ΓΓ線與該像素電極絕緣層疊,該二公共電極 …亥至少-電容電極、線電連帛。 -冤極 16. 如申請專利範圍第1〇 中’該像素電極由至少一種…二濕潤式顯示裝置’其 中有至少一錄好所访分 貝構成,其中,該像素電極 17. 如申請專利範圍貝第、^至少―、公共電極之材質相同。 中’該像素電極及該至少示裝置,其 或氧化銦鋅。 …極之材質同為氧化銦錫 18. 如申請專利範圍第16 中,該像素電極為一多層二潤?示裝置’其 ^ ± ’尽、口稱,其包括一連接層、一 ·^罢 於連接層上之阻障層、—設 。又 ^ ^ ^ c A 直於°亥阻障層上之反射層及一 σ置於献射層上之保護層,該連接層 或氧化鋼辞,該阻障層之材質為鉬二反射層之議 保護層之材質為氧化銘,該至少—公共電極之材質 ,、β亥連接層之材質相同。 ' 19. 如申請專利範圍第1〇項所述之電濕潤式顯示裝置,1 像素電極之材質為紹,該至少—公共電極之材質為 氧化鋼錫或氧化銦辞。 20. —種薄膜電晶體基板,其包括: 一弟一區域; 一位於該第-區域外圍之框膠設置區,該框膠設置區用於 設置框膠; 、 设置於該第一區域内之複數像素電極;及 26 1377368 至少一設置於該第一區域内之公共電極,該至少一公共電 極與該像素電極絕緣,且該薄膜電晶體基板裸露出該至少 一公共電極之至少一部份。 21. 如申請專利範圍第20項所述之薄膜電晶體基板,其中, 該薄膜電晶體基板進一步包括至少一電容電極線,該至少 一電容電極線與該像素電極絕緣層疊,該至少一公共電極 與該至少一電容電極線電連接。 、 22. 如申請專利範圍第21項所述之薄膜電晶體基板,其中, 該至少一公共電極之數量為二個,該二公共電極分別設置 於該像素電極相對二側且均與該至少一電容電極線電連 接。 23. 如申請專利範圍第21項所述之薄膜電晶體基板,其中, 該薄膜電晶體基板進一步包括一基底、複數相互平行間隔 設置之掃描線,複數與該掃描線垂直且間隔設置之資料 線、一第一絕緣層、一鈍化層及一親油性絕緣層圖案,該 電容電極線及該掃描線設置於該基底,該第一絕緣層設置 於該至少一電容電極線、掃描線及該基底,該資料線設置 於該第一絕緣層,該鈍化層設置於該第一絕緣層及該資料 線,該至少一公共電極及該像素電極間隔設置於該鈍化 層,該親油性絕緣層圖案設置於該像素電極上。 24. —種電濕潤式顯示裝置,其包括: 一對向基板; 一薄膜電晶體基板,其與該對向基板相對設置; 一框膠’其設置於該對向基板及該薄膜電晶體基板之間’ 27 1377368 該框膠與該對向基板及該薄膜電晶體基板配合形成一收 容空間,並於該薄膜電晶體基板界定一第一區域; 複數交叉之間隔壁,設置於該第一區域内; 一極性之第一液體,其設置於該收容空間内;及 一非極性之第二液體,其設置於該間隔壁界定之區域内; 其中,該薄膜電晶體基板包括: 設置於該間隔壁界定之區域内之複數像素電極;及 至少一設置於該第一區域内之公共電極,該公共電極與該 # 像素電極絕緣,且該薄膜電晶體基板裸露出該至少一公共 電極之至少一部份。 25. 如申請專利範圍第24項所述之電濕潤式顯示裝置,其 中,該公共電極與該第一液體電接觸,該像素電極與該第 一液體相絕緣。 26. 如申請專利範圍第24項所述之電濕潤式顯示裝置,其 中,該薄膜電晶體基板進一步包括至少一電容電極線,該 I 電容電極線與至少一像素電極絕緣層疊,該公共電極與該 電容電極線電連接。 27. 如申請專利範圍第26項所述之電濕潤式顯示裝置,其 中*該公共電極之數量為二個*該二公共電極分別設置於 該像素電極相對二側且均與該電容電極線電連接。 28. 如申請專利範圍第26項所述之電濕潤式顯示裝置,其 中,該薄膜電晶體基板進一步包括一基底、複數相互平行 間隔設置之掃描線,複數與該掃描線垂直且間隔設置之資 料線、一第一絕緣層、一鈍化層及一親油性絕緣層圖案, 28 1377368 該電容電極線及該掃描線設置於該基底,該第一絕緣層設 置於該電容電極線、掃描線及該基底’該資料線設置於該 第一絕緣層,該鈍化層設置於該第一絕緣層及該資料線, 該公共電極及該像素電極間隔設置於該純化層,該親油性 絕緣層圖案設置於該像素電極上。 29. —種薄膜電晶體基板製造方法,其包括如下步驟: 提供一基底; 於該基底上形成至少一電容電極線及複數掃描線; 於該電容電極線、該掃描線及該基底上形成一第一絕緣 層; 於該第一絕緣層上形成複數資料線; 於該第一絕緣層及該資料線上形成一鈍化層; 對應該電容電極線位置形成一貫穿該鈍化層及該第一絕 緣層之通孔; 於該鈍化層上間隔形成一公共電極及複數像素電極,使該 公共電極藉由該通孔與該電容電極線電連接; 於該像素電極上形成一親油性絕緣層圖案,並裸露出該至 少一公共電極之至少一部份。 30. —種薄膜電晶體基板,其包括: 一基底; 一設置於該基底上之複數閘極、複數掃描線及複數電容電 極線; 設置於該複數閘極、該掃描線、電容電極線及該基底上 之閘極絕緣層; 29 設置於該閘極絕绫爲 設置於該半導體g:之一半導體圖案及複數資料線; 數汲極; U該間極絕緣層上之複數源極及複 一設置於該閘極絕緣層、該 半導體圖案上之鈍化層;χ、’、、· 、〇源極、該汲極及該 設置於該鈍化層上; -設置於該像素電極上之公共電極;及 體基板裸露出該至少_八;^巴緣層圖案’該薄膜電晶 3】.如申請專利範圍 :4極之至少一部份。 該像素電極膜電晶體基板,其令, 應之沒極。 、…4化層之第一通孔電連接至對 利範㈣31項所述之薄膜電晶體基板,並中, :電連:藉由一貫穿該鈍化層及該閘極絕緣層:第二 電連接至该電容電極線。 專利範圍第3G項所述之薄膜電 f共電極之材f為氧化銦錫或氧化銦辞。八中 .口申凊專利範圍第30 該像素電極由至少一種材質構成體基板,其中’ 3至少-種材質與該公共電極之材質㈣’。_素電極中有 項所述之薄㈣晶體基板,其中, 連接芦構,其包括—設置於該鈍化層上之 上置於連接層上之阻障層、一設置於該阻障層 反射層及置於該反射層上之保護層。 • °申請專利範圍第35項所述之薄膜電晶體基板,其中, 30 1377368 該連接層之材質為氧化銦錫或氧化銦鋅,該阻障層之材質 為銦,該反射層之材質為銘,該保護層之材質為氧化I呂。 37. —種電濕潤式顯示裝置,其包括: 一對向基板; 一薄膜電晶體基板,其與該對向基板相對設置; 一框膠,其設置於該對向基板及該薄膜電晶體基板之間, 並與該對向基板及該薄膜電晶體基板配合形成一收容空 間; 一極性之第一液體,其設置於該收容空間内;及 一非極性之第二液體,其設置於該收容空間内; 其中,該薄膜電晶體基板包括: 一基底; 一設置於該基底上之複數閘極、複數掃描線及複數電容電 極線; 一設置於該複數閘極、該掃描線、電容電極線及該基底上 之閘極絕緣層; 設置於該閘極絕緣層上之一半導體圖案及複數資料線; 設置於該半導體圖案及該閘極絕緣層上之複數源極及複 數汲極; 一設置於該閘極絕緣層、該資料線、該源極、該汲極及該 半導體圖案上之鈍化層; 設置於該鈍化層上之複數像素電極及一公共電極;及 設置於該像素電極上之親油性絕緣層圖案,該薄膜電晶體 基板裸露出該至少一公共電極之至少一部份。 31 137.7368 %·如申請專利範圍第37項 带基 中,該像素電極藉由—貫穿化^式顯示裝置,其 對應之沒極。 胃牙祕化層之第—通孔電逹接至 範圍第38項所述之電m顯示&置,1 中=共電極藉由-貫穿該純化層及該閉第 -通孔電連接至該電容電極線。 象廣之第 4〇.如申請專利範圍第 貝所迷之电濕潤式顯示裝置,其 ^ A 電極之材質為氧化銦錫或氧化銦鋅。 =口申請專利範圍第37項所述之電濕潤式顯示裝置,盆 中’该像素電極由至少—種姑皙塞 中古“ 少種材貝構成,其中’該像素電極 有至v —種材質與該公共電極之材質相同。 42·如申凊專利範圍第37項所述之電濕潤式顯示褒置,其 中,該像素電極為-多層結構,其包括一設置於該純化層 上之連接層、一設置於連接層上之阻障層、-設置於該i 障層上之反射層及一設置於該反射層上之保護層。 43·如申請專利範圍第42項所述之電濕潤式顯示裴置,其 中β亥連接層之材質為氧化銦錫或氧化銦鋅,該阻障層之 材質為鉬,該反射層之材質為鋁,該保護層之材質為氧化 鋁。 44·一種薄膜電晶體基板製造方法,其包括如下步驟: 提供一基底; 於該基底上形成複數閘極、複數掃描線及複數電容電極 線; 於該複數閘極、該掃描線、電容電極線及該基底上形成一 32 1377368 閘極絕緣層; 上?成—半導體圖案及複數資料線; 汲^; a0术及°亥閉極絕緣層上形成複數源極及複數 緣層、該資料線、該源極、該沒極及該半導體 圖案上形成一純化層; ===上形成複數像素電極及一公共電極;及 ,二H形成-親油性絕緣層圖案’並裸露出該至 ^'一公共電極之至少一部份。 45·如中請專利範圍帛44項所述之薄膜電晶體基板製造方 法,其中,該薄膜電晶體基板製造方法進一步包括一步 驟:形成一對應該汲極位置並貫穿該鈍化層之第—通孔^ 一對應該電容電極線位置並貫穿該減層及該閘極絕緣 層之第二通孔。1377368 Patent Application No. 97116297 Supplementary, Amendment, Unlined Patent Application Replacing Page Revision Date: September 10, 101, Patent Application Range 1^1 m 曰 Amendment 1. A thin film transistor substrate comprising: a display area; at least one contact area, at least one side of the display area; a sealant setting area 5 surrounding the display area and the contact area for setting a sealant; a plurality of pixel electrodes disposed in the display area; And at least one common electrode disposed on the at least one contact region, and the thin film transistor substrate exposes at least a portion of the at least one common electrode. 2. The thin film transistor substrate of claim 1, wherein the thin film transistor substrate further comprises at least one capacitor electrode line, the at least one capacitor electrode line being insulated from the pixel electrode, the at least one common electrode And electrically connected to the at least one capacitor electrode line. 3. The thin film transistor substrate of claim 2, wherein the at least one capacitive electrode line extends from the at least one contact region to the display region. 4. The thin film transistor substrate of claim 1, wherein the thin film transistor substrate comprises two at least one contact region, and the thin film transistor substrate includes the at least one common The number of the electrodes is two, and the two contact regions are respectively disposed on opposite sides of the display area, and each of the contact areas is provided with the common electrode. 5. The thin film transistor substrate of claim 4, wherein the thin film transistor substrate further comprises at least one capacitor electrode line, the at least one capacitor electrode line being insulated from the pixel electrode, the two common electrodes and The at least one capacitor electrode line is electrically connected. 23 1377368 6.2 The scope of the patent scope is as follows: the thin pixel pixel is composed of at least one material-substrate, and the material and the at least one of the electrodes are at least one of the electrodes. ώ 〆, electrode The material is the same as 〇. The pixel electrode according to claim 6 and the at least one common # pole substrate, wherein the indium is expressed. The same as indium tin oxide or oxygen 8.: Γ =: range 6 The thin film transistor substrate, μ, and the pixel electrode are a multi-layer structure board, and the barrier layer on the layer, the (1) layer is connected to the connection layer, and the layer is disposed on the connection layer. a reflective layer on the layer and a protective layer disposed on the zinc 1 'the material of the connecting layer is indium tin oxide or the anti-oxidation coating layer. The material f is the same as the material of the protective layer. At least one common electrode material of the sea and the thin film transistor substrate described in the above-mentioned patent scope S1, wherein the material of the pole is Ming' at least - the material of the common electrode is oxidized steel tin or indium oxide Zinc. 1 〇. Electric humidification display device, including · · one-way base a thin film transistor substrate disposed opposite to the opposite substrate; the glue is disposed between the opposite substrate and the thin film transistor substrate, and is formed by cooperating with the 5H counter substrate and the thin film transistor substrate a accommodating space; a liquid-first liquid disposed in the accommodating space; and a non-polar second liquid that is incompatible with the first liquid of the 5H, disposed in the accommodating space of the 24 1377368; wherein the film The transistor substrate comprises: at least a contact region and a display region, the at least the contact region and the region of the film defined by the thin film transistor substrate; ... a plurality of pixel electrodes disposed in the display region; - lipophilic insulation The layer pattern is disposed on the pixel electrode, and the at least one common electrode is disposed on the at least one contact region substrate to expose at least a portion of the at least one common electrode: the electrowetting type described in claim 10 of the patent application scope The display device, 1 in the 'at least one common electrode and the first liquid: is insulated from the first liquid. Contacting the money electrode 2 = the electrowetting type described in Item 1 () I: The = crystal substrate further comprises at least a capacitor electrode line, the v-electrode electrode line is insulated from the pixel electrode, and the at least eight-electrode is electrically connected to the at least one capacitor electrode line. The electrowetting display device according to claim 12, wherein the at least-capacitive electrode line extends from the at least _ contact region to the electrowetting display device as described in the patent application 帛10 $ In the basin, the number of the at least one contact region included in the thin film transistor substrate is two, and the thin film transistor substrate includes at least one of the at least one such as 曰JA A six electrodes. The two contact areas are respectively disposed on opposite sides of the display area, and the contact area is provided with the common electrode. 1 . The electrowetting display device of claim 14, wherein the thin film transistor substrate comprises, at least, a K + A h step comprising at least one capacitor electrode line, the (four) to ΓΓ line and The pixel electrode is insulated and laminated, and the two common electrodes are at least - a capacitor electrode and a wire harness. - 冤 pole 16. As in the scope of the patent application, the pixel electrode is composed of at least one ... two-wet display device, wherein at least one of the recorded decibels is recorded, wherein the pixel electrode 17. The first, ^ at least, and the material of the common electrode are the same. The pixel electrode and the at least device, or indium zinc oxide. The material of the pole is the same as indium tin oxide. 18. In the 16th patent application, the pixel electrode is a multi-layered two-run? The device ''±'', nickname, includes a connecting layer, a barrier layer on the connecting layer, and a device. And ^ ^ ^ c A is directly opposite to the reflective layer on the barrier layer and a protective layer on the concentrating layer, the connecting layer or the oxidized steel, the barrier layer is made of a molybdenum reflective layer The material of the protective layer is oxidized, and at least the material of the common electrode and the material of the β-elective layer are the same. 19. The electrowetting display device of claim 1, wherein the material of the 1-pixel electrode is: at least the material of the common electrode is oxidized steel tin or indium oxide. 20. A thin film transistor substrate, comprising: a younger-one area; a sealant setting area located at a periphery of the first-area, the sealant setting area for setting a sealant; and being disposed in the first area a plurality of pixel electrodes; and 26 1377368 at least one common electrode disposed in the first region, the at least one common electrode being insulated from the pixel electrode, and the thin film transistor substrate exposing at least a portion of the at least one common electrode. The thin film transistor substrate of claim 20, wherein the thin film transistor substrate further comprises at least one capacitor electrode line, the at least one capacitor electrode line being insulated from the pixel electrode, the at least one common electrode And electrically connected to the at least one capacitor electrode line. The thin film transistor substrate of claim 21, wherein the number of the at least one common electrode is two, and the two common electrodes are respectively disposed on opposite sides of the pixel electrode and are at least one The capacitor electrode wires are electrically connected. The thin film transistor substrate according to claim 21, wherein the thin film transistor substrate further comprises a substrate, a plurality of scanning lines arranged in parallel with each other, and a plurality of data lines perpendicular to the scanning line and spaced apart from each other a first insulating layer, a passivation layer, and a lipophilic insulating layer pattern, the capacitor electrode line and the scan line are disposed on the substrate, the first insulating layer is disposed on the at least one capacitor electrode line, the scan line, and the substrate The data line is disposed on the first insulating layer, the passivation layer is disposed on the first insulating layer and the data line, the at least one common electrode and the pixel electrode are spaced apart from the passivation layer, and the lipophilic insulating layer is patterned On the pixel electrode. 24. An electrowetting display device comprising: a pair of substrates; a thin film transistor substrate disposed opposite the counter substrate; a sealant disposed on the counter substrate and the thin film transistor substrate Between the '27 1377368 and the opposite substrate and the thin film transistor substrate, a receiving space is formed, and a first region is defined on the thin film transistor substrate; a plurality of intersecting partition walls are disposed in the first region a first liquid of a polarity disposed in the receiving space; and a second liquid of a non-polarity disposed in the region defined by the partition wall; wherein the thin film transistor substrate comprises: a plurality of pixel electrodes in a region defined by the partition walls; and at least one common electrode disposed in the first region, the common electrode is insulated from the # pixel electrode, and the thin film transistor substrate exposes at least one of the at least one common electrode Part. 25. The electrowetting display device of claim 24, wherein the common electrode is in electrical contact with the first liquid, the pixel electrode being insulated from the first liquid. 26. The electrowetting display device of claim 24, wherein the thin film transistor substrate further comprises at least one capacitor electrode line, the I capacitor electrode line being insulated from the at least one pixel electrode, the common electrode being The capacitor electrode line is electrically connected. 27. The electrowetting display device of claim 26, wherein the number of the common electrodes is two; the two common electrodes are respectively disposed on opposite sides of the pixel electrode and are electrically connected to the capacitor electrode connection. 28. The electrowetting display device of claim 26, wherein the thin film transistor substrate further comprises a substrate, a plurality of scan lines arranged in parallel with each other, and a plurality of data perpendicular to and spaced apart from the scan line. a line, a first insulating layer, a passivation layer, and a lipophilic insulating layer pattern, 28 1377368, the capacitor electrode line and the scan line are disposed on the substrate, the first insulating layer is disposed on the capacitor electrode line, the scan line, and the The substrate is disposed on the first insulating layer, the passivation layer is disposed on the first insulating layer and the data line, the common electrode and the pixel electrode are spaced apart from the purification layer, and the lipophilic insulating layer pattern is disposed on the substrate On the pixel electrode. 29. A method of fabricating a thin film transistor substrate, comprising the steps of: providing a substrate; forming at least one capacitor electrode line and a plurality of scan lines on the substrate; forming a capacitor on the capacitor electrode line, the scan line, and the substrate a first insulating layer; forming a plurality of data lines on the first insulating layer; forming a passivation layer on the first insulating layer and the data line; forming a passivation layer and the first insulating layer corresponding to the position of the capacitor electrode line a via hole is formed on the passivation layer to form a common electrode and a plurality of pixel electrodes, and the common electrode is electrically connected to the capacitor electrode line through the through hole; forming a lipophilic insulating layer pattern on the pixel electrode, and Exposed at least a portion of the at least one common electrode. 30. A thin film transistor substrate, comprising: a substrate; a plurality of gates, a plurality of scan lines, and a plurality of capacitor electrode lines disposed on the substrate; disposed on the plurality of gates, the scan lines, the capacitor electrode lines, and a gate insulating layer on the substrate; 29 is disposed on the gate electrode to be disposed on the semiconductor g: a semiconductor pattern and a plurality of data lines; a plurality of drains; U of the plurality of sources on the interpole insulating layer a passivation layer disposed on the gate insulating layer and the semiconductor pattern; χ, ', , ·, 〇 source, the drain and the bead disposed on the passivation layer; - a common electrode disposed on the pixel electrode And the body substrate is exposed to the at least _8; ^ bar layer layer pattern 'the film cell crystal 3'. As claimed in the patent range: at least a part of the 4 pole. The pixel electrode film transistor substrate is not so extreme. The first via hole of the 4th layer is electrically connected to the thin film transistor substrate described in paragraph 31 of Lifan (4), and wherein: the electrical connection: through the passivation layer and the gate insulating layer: the second electrical connection To the capacitor electrode line. The material f of the thin film electric f common electrode described in the third aspect of the patent is indium tin oxide or indium oxide.八中. 凊申凊 Patent Range No. 30 The pixel electrode is composed of at least one material to form a body substrate, wherein '3 at least one material and the material of the common electrode (four)'. The thin (four) crystal substrate of the present invention, wherein the connection structure comprises: a barrier layer disposed on the connection layer on the passivation layer, and a reflective layer disposed on the barrier layer And a protective layer placed on the reflective layer. The film dielectric substrate according to claim 35, wherein 30 1377368 is made of indium tin oxide or indium zinc oxide, and the barrier layer is made of indium, and the material of the reflective layer is The material of the protective layer is oxidized I. 37. An electrowetting display device, comprising: a pair of substrates; a thin film transistor substrate disposed opposite to the opposite substrate; a sealant disposed on the opposite substrate and the thin film transistor substrate And forming a receiving space with the opposite substrate and the thin film transistor substrate; a first liquid of a polarity disposed in the receiving space; and a non-polar second liquid disposed in the receiving The thin film transistor substrate includes: a substrate; a plurality of gates, a plurality of scan lines, and a plurality of capacitor electrode lines disposed on the substrate; a plurality of gates, the scan lines, and capacitor electrode lines disposed on the substrate And a gate insulating layer on the substrate; a semiconductor pattern and a plurality of data lines disposed on the gate insulating layer; a plurality of source and a plurality of drain electrodes disposed on the semiconductor pattern and the gate insulating layer; a gate insulating layer, the data line, the source, the drain, and a passivation layer on the semiconductor pattern; a plurality of pixel electrodes and a common electrode disposed on the passivation layer And a lipophilic insulating layer pattern disposed on the pixel electrode, the thin film transistor substrate exposing at least a portion of the at least one common electrode. 31 137.7368 %· As claimed in claim 37, the pixel electrode is formed by a through-type display device, which corresponds to a pole. The first pass of the gastric tooth secret layer is electrically connected to the electric m display & set, the middle 1 = common electrode is electrically connected to the purified layer and the closed first through hole through The capacitor electrode line. The fourth embodiment of the image is as described in the patent application No. 2, the electrowetting display device, wherein the material of the A electrode is indium tin oxide or indium zinc oxide. The invention relates to an electrowetting display device according to item 37 of the patent application. In the basin, the pixel electrode is composed of at least a kind of scorpion scorpion, which is composed of a few kinds of materials, wherein the pixel electrode has a v-type material and The electro-wet display device of claim 37, wherein the pixel electrode is a multi-layer structure comprising a connection layer disposed on the purification layer, a barrier layer disposed on the connection layer, a reflective layer disposed on the barrier layer, and a protective layer disposed on the reflective layer. 43. The electrowetting display according to claim 42 The material of the β-hai connection layer is indium tin oxide or indium zinc oxide, the material of the barrier layer is molybdenum, the material of the reflective layer is aluminum, and the material of the protective layer is aluminum oxide. A method for manufacturing a crystal substrate, comprising the steps of: providing a substrate; forming a plurality of gates, a plurality of scan lines, and a plurality of capacitor electrode lines on the substrate; forming the plurality of gates, the scan lines, the capacitor electrode lines, and the substrate a 32 1377368 gate insulating layer; an upper semiconductor layer and a plurality of data lines; 汲^; a0 and a closed-pole insulating layer forming a plurality of source and complex edge layers, the data line, the source, the Forming a purification layer on the semiconductor pattern; forming a plurality of pixel electrodes and a common electrode on the ===; and forming a lipophilic insulating layer pattern and forming at least one of the common electrodes The method for manufacturing a thin film transistor substrate according to claim 44, wherein the method for fabricating a thin film transistor substrate further comprises a step of forming a pair of drain electrodes and passing through the passivation layer. The first through hole ^ is a pair of capacitor electrode line positions and penetrates the subtraction layer and the second via hole of the gate insulating layer. 3333
TW97116297A 2008-05-02 2008-05-02 Thin film transistor substrate, fabricating method thereof, and electro-wetting display TWI377368B (en)

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