TWI376744B - Silicon film dry etching method - Google Patents

Silicon film dry etching method Download PDF

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Publication number
TWI376744B
TWI376744B TW097119800A TW97119800A TWI376744B TW I376744 B TWI376744 B TW I376744B TW 097119800 A TW097119800 A TW 097119800A TW 97119800 A TW97119800 A TW 97119800A TW I376744 B TWI376744 B TW I376744B
Authority
TW
Taiwan
Prior art keywords
dry etching
film
ruthenium film
etching method
gas
Prior art date
Application number
TW097119800A
Other languages
Chinese (zh)
Other versions
TW200901315A (en
Inventor
Hisao Tosaka
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Publication of TW200901315A publication Critical patent/TW200901315A/en
Application granted granted Critical
Publication of TWI376744B publication Critical patent/TWI376744B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Description

1376744 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種矽膜的乾式蝕刻法。 【先前技術】 例如，在以往的薄膜電晶體方面，有逆堆疊型者（參 照例如專利文獻1 )。在此薄膜電晶體中，在基板的上面設 置閘極電極。在包含閘極電極的基板之上面設置閘極絕緣 膜。在閘極電極上的閘極絕緣膜之上面設置由本徵非晶矽 所組成的半導體薄膜。半導體薄膜之上面兩側設置由η型 非晶矽所組成的歐姆接觸層。各歐姆接觸層的上面設置源 極電極以及汲極電極。 [專利文獻1]特開2007-79342號公報（第5圖） 然而，在上述以往的薄膜電晶體之歐姆接觸層以及半 導體薄膜形成方法方面，連續對在閘極絕緣膜之上面形成 的本徵非晶矽膜（半導體薄膜形成用膜）以及η型非晶矽膜 (歐姆接觸層形成用膜）進行乾式蝕刻。在此情況下，使用 SF〆六氟化離子）氣體來作爲蝕刻氣體（專利文獻1的第130 段落）。 【發明內容】 在這種乾式蝕刻法中使用的蝕刻氣體中之SF6，在近 幾年是地球溫暖化的一個原因而被認爲是問題，因此，選 擇將其代替的替代氣體就成了重要的課題。 因此，本發明之主要目的在於提供一種矽膜的乾式蝕 刻法，其能夠不使用SF6等之成爲地球溫暖化之一個原因 的氣體，並良好地對非晶矽等之矽膜進行乾式鈾刻。 1376744 本發明之較佳的態樣係砂膜的乾式餘刻法，其特徵 爲：藉由利用包含氟氣體以及氯氣體之混合氣體的平行平 板型之乾式蝕刻，來對矽膜進行乾式蝕刻。 此外本發明之較佳態樣之一係矽膜的乾式蝕刻法， 其特徵爲：準備已在基板上層積有矽膜的被加工物；將被 加工物搬入至平彳了配置有局頻電極及對向電極的平行平板 型之乾式蝕刻裝置內，將前述被加工物的基板載置於前述 高頻電極上或是對向電極上之任一方；將前述乾式蝕刻裝 置減壓，將氟氣體以及氯氣體導入至前述乾式蝕刻裝置 內；以及前述高頻電極上施加高頻，蝕刻前述矽膜》 【實施方式】 第1圖係.表示由包含本發明之乾式蝕刻法的製造方法 所製造的薄膜電晶體面板之一個範例的截面圖。此薄膜電 晶體面板係具備玻璃基板1。玻璃基板1之上面的既定處 設置由鉻等所組成的閘極電極2。包含閘極電極2的玻璃 基板1之上面設置由氮化矽所組成的閘極絕緣膜3。 在閘極電極2上的閘極絕緣膜3之上面的既定處設置 由本徵非晶矽所組成的半導體薄膜4。在半導體薄膜4上 面的既定處設置由氮化矽所組成的通道保護膜5。在通道 保護膜5之上面兩側以及此兩側的半導體薄膜4之上面設 置由η型非晶矽所組成的歐姆接觸層6、7»在歐姆接觸層 6、7之各上面設置由鉻等所組成的源極電極8以及汲極電 極9。 在此，由閘極電極2、閘極絕緣膜3、半導體薄膜4、 通道保護膜5、歐姆接觸層6' 7、源極電極8以及汲極電 1376744 極9，以逆堆疊型來構成通道保護膜型的薄膜電晶體1〇。 在包含薄膜電晶體10的閘極絕緣膜3之上面設置由 氮化矽所組成的覆蓋（overcoat)膜11。在與源極電極8之既 定處對應之部分的覆蓋膜11上設置接觸孔12。覆蓋膜11 之上面的既定處設置由IT0所組成之畫素電極13,該畫素 電極13係介由接觸孔12而連接於源極電極8。 接著，針對此薄膜電晶體面板的製造方法之一例來進 行說明。首先，如第2圖所示，利用光微影法來將以濺鍍 法所成膜且由鉻等組成的金屬膜進行圖案化，藉以在玻璃 基板1之上面的既定處形成閘極電極2。 接著，在包含閘極電極2的玻璃基板1之上面，藉由 電漿CVD法等，連續地形成由氮化矽所組成之閘極絕緣膜 3、本徵非晶矽膜（半導體薄膜形成用膜）21以及氮化矽膜（通 道保護膜形成用膜）2 2。接著，在氮化矽膜22之上面的通 道保護膜形成區域中，以光微影法對由印刷法等所塗布的 阻劑膜進行圖案化，藉以形成阻劑（resist)膜23。 接著，當以阻劑膜2 3作爲遮罩並對氮化矽膜2 2進行 乾式蝕刻時，就除去在阻劑膜2 3下以外之區域的氮化矽膜 22 ’如第3圖所示，在阻劑膜23下形成通道保護膜5。接 著，剝離阻劑膜23。 接著’如第4圖所示，在包含通道保護膜5的本徵非 晶矽膜21之上面，藉由電漿CVD法，來形成η型非晶矽 膜（歐姆接觸層形成用膜）24。接著，在η型非晶矽膜24之 上面，藉由濺鍍法’形成由鉻等所組成之源極、汲極電極 形成用膜25。 1376744 接著，在源極、汲極電極形成用膜25之上面的源極 電極形成區域及汲極電極形成區域中，以光微影法對由印 刷法等所塗布的阻劑膜進行圖案化，藉以形成阻劑膜26、 27 - 接著，當以阻劑膜26、27作爲遮罩並對源極、汲極 電極形成用膜25進行濕式蝕刻時，就除去在阻劑膜26、27 下以外之區域的源極、汲極電極形成用膜25，如第5圖所 示’在阻劑膜26、27下形成源極電極8以及汲極電極9。 接著，以阻劑膜26、27及通道保護膜5作爲遮罩， 連續對η型非晶矽膜24以及本徵非晶矽膜2 1進行如同後 述之乾式蝕刻時，除去阻劑膜26、27下以外之區域的η型 非晶矽膜24’且除去阻劑膜26、27以及通道保護膜5下以 外之區域的本徵非晶矽膜2 1，如第6圖所示，在源極電極 8以及汲極電極9下形成歐姆接觸層6、7，且在歐姆接觸 層6、7以及通道保護膜5下形成半導體薄膜4。接著，剝 離阻劑膜26、27。 接著，如第1圖所示，在包含薄膜電晶體1 〇的閘極 絕緣膜3之上面，藉由電漿CVD法來形成由氮化矽所組成 的覆蓋膜11。接著，在覆蓋膜11的既定處，藉由光微影法 來形成接觸孔1 2。 接著，在覆蓋膜11之上面的既定處，以光微影法對 由濺鍍法所形成之ΙΤΟ膜進行圖案化，使畫素電極13形成 爲介由接觸孔12而連接於源極電極8。於是，能獲得第1 圖所示的薄膜電晶體面板。 接著’針對在上述製造方法中用於進行乾式蝕刻之乾 1376744 式蝕刻裝置的一個範例，參照第7圖所示之槪略構成圖來 加以說明。此乾式鈾刻裝置是平行平板型，具備反應容器 31。在反應容器31內之下部設有下部電極32,在上部設有 上部電極33。在此情況下，下部電極32係連接於高頻電源 34，上部電極33則是接地。下部電極32之上面成爲載置 有被加工物35。反應容器31之下部的既定處係介由配設管 路36而連接於真空泵浦37。 在反應容器31之上部中央部，氣體導入管38係設置 成貫通上部電極33之中央部。氣體導入管38係連接於共 通配設管路39。共通配設管路39係連接有第1、第2配設 管路40、4卜第1、第2配設管路40、41中係介入有第1、 第2電磁閥42、43以及第1、第2質流（mass flow)控制器 44、45。第1、第2配設管路40 ' 41的各前端部係連接有 由氣瓶等所組成之氟氣體供給源46以及氯氣體供給源47。 接著，使用上述構成的乾式蝕刻裝置，就在下部電極 32之上面載置的被加工物35係處於第5圖所示的狀態，連 續對由氮化矽所組成之閘極絕緣膜3上的η型非晶矽膜24 以及本徵非晶矽膜2 1進行乾式蝕刻的情況進行說明。首 先，藉由真空泵浦37的驅動，排出反應容器31內的氣體， 將反應容器31內之壓力設爲10Pa。 接著，打開第1、第2電磁閥42、43，由氣體導入管 3 8，將從氟氣體供給源46以及氯氣體供給源47所供給之 氟氣體以及氯氣體的混合氣體導入至反應容器31內。在此 情況下，藉由第1、第2質流控制器44、45來調整氟氣體 以及氯氣體的各流量，將氟氣體之流量設爲lOOsccm，將氯 1376744 氣體的流量設爲100〜lOOOsccm。另外，從高頻電源34施 加13.56MHz的高頻電力700W。 於是’阻劑膜26、27及通道保護膜5下以外之區域 的η型非晶矽膜24以及本徵非晶矽膜2 1會連續地被乾式 蝕刻所除去，其蝕刻率是大約1500 A/m in »在此情況下，完 全除去本徵非晶矽膜21時，會露出基底之由氮化矽組成的 閘極絕緣膜3，此露出的閘極絕緣膜3會被某種程度之乾 式蝕刻所除去，但其蝕刻率是大約4 00 A/min。因此，此情 況下的選擇比是大約4倍，而可實際應用。而且，氟氣體 的溫暖化係數是零，對於抑制溫暖化氣體之排出量方面有 相當大的助益。 此外，氟氣體供給源46也可以是供給以氮、氦、氖、 氬等的惰性氣體之任一種或者複數種的氣體所稀釋而成的 稀釋氟氣體者。例如，以氮氣體而稀釋爲20 v 〇1%的稀釋氟 氣體之流量設爲500sccm(僅氟氣體的流量是lOOsccm)，將 氯氣體的流量設爲100〜lOOOsccm亦可。 另外，也可以設置與氟氣體供給源46不同的惰性氣 體供給源。另外|在上述的任一情況下，氯氣體相對於氟 氣體的流量比是1〜10,但只要是在1〜20的範圍內即可。 此外，只要反應容器31內的壓力在1〜100Pa的範圍內即 可。 另外，在第7圖所示之乾式蝕刻裝置中，對載置有被 加工物35的下部電極32施加高頻，容易產生接地之上部 電極33側，亦即陰極側，之陰極電壓降，將由放電所產生 之離子用於反應者，被稱爲反應式離子蝕刻（RIE)，亦即陰 -10- 1376744 極耦合的乾式蝕刻。 在此陰極耦合的乾式蝕刻方面，可以是旁側蝕刻（S1de etching)較少的異方性蝕刻。不過，在陰極耦合的乾式蝕刻 方面，陰極側之陰極電壓降的離子衝擊有時會對電晶體特 性造成損壞》所以，接著說明減低離子損害的情況。 第8圖係表示乾式蝕刻裝置之其他例之槪略構成圖。 在此乾式蝕刻裝置中，與第7圖所示之乾式蝕刻裝置不同 之處，在於使下部電極32接地，使上部電極33連接於高 頻電源34。因此，在此乾式蝕刻裝置中，相較於陰極耦合 之乾式蝕刻的情況，進行陽極耦合之乾式蝕刻而能夠減低 離子損害。 然後，調查陽極耦合之乾式蝕刻的情況與陰極耦合之 乾式蝕刻的情況之電晶體特性（Vg(閘極電壓）-Id(汲極電流） 特性）的結果，得到第9圖所示之結果。從第9圖中可明顯 看出，在實線所表示之陽極耦合的情況下，相較於以虛線 表示之陰極耦合的情況，沒有上升部分的隆起，可改善電 晶體特性。 另外，在此乾式蝕刻裝置中，使蝕刻條件與上述情況 相同，亦即，將反應容器31內之壓力設爲lOPa，將氟氣體 的流量設爲lOOsccm，將氯氣體的流量設爲1〇〇〜 lOOOsccm，從高頻電源34施加13.56MHz的高頻電力700W， 結果η型非晶矽膜24以及本徵非晶矽膜2 1的蝕刻率是大 約1 500A/min，基底之由氮化矽所組成的閘極絕緣膜3之蝕 刻率是大約500 A/mi η。因此，此情況下的選擇比是大約3 倍，而可實際應用。 -11 - 1376744 . 此外，在上述實施形態中，在使用非晶矽的薄膜電晶 體方面，已針對在由氮化矽組成之閘極絕緣膜3的上面形 . 成的本徵非晶矽膜2 1以及η型非晶矽膜24進行乾式蝕刻 ' 的情況進行說明，但並非侷限於此》 • 例如，在使用多晶矽的薄膜電晶體中，亦可對在氮化 矽膜之上面形成的多晶矽膜進行乾式蝕刻。另外，在使用 . 砂的薄膜二極體（TFD: Thin Film Diode)中，亦可對在氮化 砍膜之上面形成的矽膜進行乾式蝕刻。 另外，本發明並非侷限於以上的實施例，可以在不脫 ^ 離發明要旨的範圍內自由地變更、改良。 【圖式簡單說明】 第1圖係由包含本發明之乾式蝕刻法的製造方法所製 造的薄膜電晶體面板之一個範例的截面圖 第2圖係在第1圖所示之薄膜電晶體面板的製造方法 之一個範例，最初之步驟的截面圖。 第3圖係第2圖之後續步驟的截面圖。 第4圖係第3圖之後續步驟的截面圖。 Φ 第5圖係第4圖之後續步驟的截面圖。 第6圖係第5圖之後續步驟的截面圖。 第7圖係乾式蝕刻裝置之—個範例的槪略構成圖。 第8圖係乾式蝕刻裝置之其他範例的槪略構成圖。 第9圖係表示用以說明電晶體特性的圖。 [主要元件符號說明】 1 玻璃基板 2 閘極電極 -12- 13767441376744 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a dry etching method of a ruthenium film. [Prior Art] For example, in the case of the conventional thin film transistor, there is a reverse stack type (see, for example, Patent Document 1). In this thin film transistor, a gate electrode is provided on the upper surface of the substrate. A gate insulating film is provided on the substrate including the gate electrode. A semiconductor film composed of intrinsic amorphous germanium is disposed on the gate insulating film on the gate electrode. An ohmic contact layer composed of an n-type amorphous germanium is disposed on both upper sides of the semiconductor thin film. A source electrode and a drain electrode are disposed on the upper surface of each ohmic contact layer. [Patent Document 1] JP-A-2007-79342 (Fig. 5) However, in the ohmic contact layer of the conventional thin film transistor and the method of forming a semiconductor thin film, the intrinsic formation on the gate insulating film is continuously performed. The amorphous tantalum film (film for forming a semiconductor thin film) and the n-type amorphous tantalum film (film for forming an ohmic contact layer) are dry-etched. In this case, an SF hexafluoride ion gas is used as the etching gas (paragraph 130 of Patent Document 1). SUMMARY OF THE INVENTION SF6 in an etching gas used in such a dry etching method is considered to be a cause of global warming in recent years, and therefore, it is important to select an alternative gas to replace it. Question. Accordingly, it is a primary object of the present invention to provide a dry etching method for a ruthenium film which can perform dry uranium engraving on a ruthenium film such as amorphous ruthenium without using a gas which is one cause of global warming such as SF6. 1376744 A preferred embodiment of the present invention is a dry remnant method of a sand film characterized in that dry etching of a ruthenium film is carried out by dry etching using a parallel plate type containing a mixed gas of a fluorine gas and a chlorine gas. Further, one of the preferred aspects of the present invention is a dry etching method of a tantalum film, which is characterized in that a workpiece to be processed by laminating a tantalum film on a substrate is prepared; and a workpiece is carried into a flat surface and a local frequency electrode is disposed. And a parallel plate type dry etching device for opposing electrodes, wherein the substrate of the workpiece is placed on the high-frequency electrode or the counter electrode; and the dry etching device is decompressed to remove fluorine gas And introducing a chlorine gas into the dry etching apparatus; and applying a high frequency to the high-frequency electrode to etch the tantalum film. [Embodiment] FIG. 1 is a view showing a manufacturing method including the dry etching method of the present invention. A cross-sectional view of an example of a thin film transistor panel. This thin film transistor panel is provided with a glass substrate 1. A gate electrode 2 composed of chromium or the like is provided at a predetermined portion on the upper surface of the glass substrate 1. A gate insulating film 3 composed of tantalum nitride is provided on the upper surface of the glass substrate 1 including the gate electrode 2. A semiconductor thin film 4 composed of intrinsic amorphous germanium is provided at a predetermined portion above the gate insulating film 3 on the gate electrode 2. A channel protective film 5 composed of tantalum nitride is provided at a predetermined portion on the upper surface of the semiconductor thin film 4. An ohmic contact layer 6 and 7» composed of an n-type amorphous germanium is disposed on both sides of the upper surface of the channel protective film 5 and on the both sides of the semiconductor thin film 4, and chromium is provided on each of the ohmic contact layers 6, 7 The source electrode 8 and the drain electrode 9 are composed. Here, the gate electrode 2, the gate insulating film 3, the semiconductor thin film 4, the channel protective film 5, the ohmic contact layer 6'7, the source electrode 8, and the gate electrode 1376744 are formed in a reverse stacked type. The protective film type thin film transistor is 1 〇. An overcoat film 11 composed of tantalum nitride is provided on the gate insulating film 3 including the thin film transistor 10. A contact hole 12 is provided on a portion of the cover film 11 corresponding to a predetermined portion of the source electrode 8. A pixel electrode 13 composed of IT0 is disposed at a predetermined portion of the upper surface of the cover film 11, and the pixel electrode 13 is connected to the source electrode 8 via a contact hole 12. Next, an example of a method of manufacturing the thin film transistor panel will be described. First, as shown in FIG. 2, a metal film formed by sputtering and formed of chromium or the like is patterned by photolithography to form a gate electrode 2 at a predetermined position on the upper surface of the glass substrate 1. . Next, on the upper surface of the glass substrate 1 including the gate electrode 2, a gate insulating film 3 composed of tantalum nitride and an intrinsic amorphous germanium film (formation of a semiconductor thin film) are continuously formed by a plasma CVD method or the like. Membrane) 21 and a tantalum nitride film (film for channel protective film formation) 2 2 . Next, in the channel protective film formation region on the upper surface of the tantalum nitride film 22, the resist film coated by the printing method or the like is patterned by photolithography to form a resist film 23. Next, when the resist film 23 is used as a mask and the tantalum nitride film 22 is dry-etched, the tantalum nitride film 22' in a region other than the resist film 23 is removed as shown in FIG. A channel protective film 5 is formed under the resist film 23. Next, the resist film 23 is peeled off. Next, as shown in Fig. 4, an n-type amorphous germanium film (film for forming an ohmic contact layer) is formed on the upper surface of the intrinsic amorphous germanium film 21 including the channel protective film 5 by a plasma CVD method. . Then, on the upper surface of the n-type amorphous germanium film 24, a source/drain electrode forming film 25 composed of chromium or the like is formed by sputtering. 1376744 Next, in the source electrode formation region and the gate electrode formation region on the upper surface of the source and the gate electrode formation film 25, the resist film applied by the printing method or the like is patterned by photolithography. By forming the resist films 26, 27 -, when the resist film 26, 27 is used as a mask and the source and the gate electrode forming film 25 are wet-etched, they are removed under the resist films 26, 27. The source/drain electrode forming film 25 in the region other than the region, as shown in Fig. 5, forms the source electrode 8 and the drain electrode 9 under the resist films 26 and 27. Next, when the resist films 26 and 27 and the channel protective film 5 are used as masks, the n-type amorphous germanium film 24 and the intrinsic amorphous germanium film 21 are continuously subjected to dry etching as will be described later, and the resist film 26 is removed. The n-type amorphous germanium film 24' in a region other than 27 and the intrinsic amorphous germanium film 2 1 excluding the resist films 26 and 27 and the region other than the channel protective film 5 are as shown in Fig. 6, at the source The ohmic contact layers 6, 7 are formed under the electrode electrodes 8 and the drain electrodes 9, and the semiconductor thin film 4 is formed under the ohmic contact layers 6, 7 and the channel protective film 5. Next, the resist films 26 and 27 are peeled off. Next, as shown in Fig. 1, a cover film 11 composed of tantalum nitride is formed on the upper surface of the gate insulating film 3 including the thin film transistor 1 by a plasma CVD method. Next, at a predetermined portion of the cover film 11, the contact hole 12 is formed by photolithography. Next, at a predetermined point on the upper surface of the cover film 11, the ruthenium film formed by the sputtering method is patterned by photolithography, so that the pixel electrode 13 is formed to be connected to the source electrode 8 via the contact hole 12. . Thus, the thin film transistor panel shown in Fig. 1 can be obtained. Next, an example of a dry 1376744 etching apparatus for performing dry etching in the above manufacturing method will be described with reference to the schematic configuration shown in Fig. 7. This dry uranium engraving apparatus is of a parallel plate type and has a reaction vessel 31. A lower electrode 32 is provided in the lower portion of the reaction vessel 31, and an upper electrode 33 is provided on the upper portion. In this case, the lower electrode 32 is connected to the high frequency power source 34, and the upper electrode 33 is grounded. The workpiece 35 is placed on the upper surface of the lower electrode 32. A predetermined portion of the lower portion of the reaction vessel 31 is connected to the vacuum pump 37 via the distribution pipe 36. In the central portion of the upper portion of the reaction vessel 31, the gas introduction pipe 38 is provided to penetrate the central portion of the upper electrode 33. The gas introduction pipe 38 is connected to the common distribution line 39. The common distribution line 39 is connected to the first and second arrangement lines 40 and 4, and the first and second arrangement lines 40 and 41 are interposed with the first and second electromagnetic valves 42 and 43 and the first 1. A second mass flow controller 44, 45. A fluorine gas supply source 46 composed of a gas cylinder or the like and a chlorine gas supply source 47 are connected to the front end portions of the first and second distribution lines 40' to 41. Then, using the dry etching apparatus having the above configuration, the workpiece 35 placed on the upper surface of the lower electrode 32 is in the state shown in Fig. 5, and continuously on the gate insulating film 3 composed of tantalum nitride. The case where the n-type amorphous germanium film 24 and the intrinsic amorphous germanium film 21 are dry-etched will be described. First, the gas in the reaction vessel 31 is discharged by the driving of the vacuum pump 37, and the pressure in the reaction vessel 31 is set to 10 Pa. Then, the first and second electromagnetic valves 42 and 43 are opened, and the mixed gas of the fluorine gas and the chlorine gas supplied from the fluorine gas supply source 46 and the chlorine gas supply source 47 is introduced into the reaction container 31 by the gas introduction pipe 38. Inside. In this case, the flow rates of the fluorine gas and the chlorine gas are adjusted by the first and second mass flow controllers 44 and 45, the flow rate of the fluorine gas is set to 100 sccm, and the flow rate of the chlorine 1376744 gas is set to 100 to 1000 sccm. . Further, high frequency power of 700 W of 13.56 MHz is applied from the high frequency power source 34. Thus, the n-type amorphous germanium film 24 and the intrinsic amorphous germanium film 21 in the regions other than the resist films 26 and 27 and the channel protective film 5 are continuously removed by dry etching, and the etching rate is about 1500 A. /m in » In this case, when the intrinsic amorphous germanium film 21 is completely removed, the gate insulating film 3 composed of tantalum nitride is exposed, and the exposed gate insulating film 3 is somewhat to some extent The dry etching was removed, but the etching rate was about 400 A/min. Therefore, the selection ratio in this case is about 4 times, and it can be practically applied. Moreover, the warming coefficient of the fluorine gas is zero, which is quite helpful for suppressing the discharge amount of the warming gas. Further, the fluorine gas supply source 46 may be a diluted fluorine gas which is supplied by diluting any one or a plurality of inert gases such as nitrogen, helium, neon or argon. For example, the flow rate of the diluted fluorine gas diluted to 20 v 〇 1% with a nitrogen gas is set to 500 sccm (only the flow rate of the fluorine gas is 100 sccm), and the flow rate of the chlorine gas may be 100 to 1000 sccm. Further, an inert gas supply source different from the fluorine gas supply source 46 may be provided. Further, in any of the above cases, the flow ratio of the chlorine gas to the fluorine gas is 1 to 10, but it may be in the range of 1 to 20. Further, the pressure in the reaction vessel 31 may be in the range of 1 to 100 Pa. Further, in the dry etching apparatus shown in Fig. 7, a high frequency is applied to the lower electrode 32 on which the workpiece 35 is placed, and the cathode voltage on the grounded upper electrode 33 side, that is, the cathode side, is likely to occur. The ions generated by the discharge are used for the reaction, which is called reactive ion etching (RIE), that is, the dry-etching of the cathode--10-37644 pole coupling. In terms of dry etching of the cathode coupling, it may be an anisotropic etching with less side etching. However, in the dry etching of the cathode coupling, the ion impact of the cathode voltage drop on the cathode side sometimes causes damage to the characteristics of the transistor. Therefore, the case of reducing ion damage will be described next. Fig. 8 is a schematic block diagram showing another example of the dry etching apparatus. The dry etching apparatus differs from the dry etching apparatus shown in Fig. 7 in that the lower electrode 32 is grounded and the upper electrode 33 is connected to the high frequency power source 34. Therefore, in this dry etching apparatus, dry etching by anodic coupling can be performed to reduce ion damage as compared with the case of dry etching of cathode coupling. Then, the results of the graph shown in Fig. 9 were obtained as a result of investigating the results of the transistor characteristics of the dry-etching of the anode coupling and the characteristics of the transistor (Vg (gate voltage) - Id (the drain current)) in the case of dry etching of the cathode coupling. As is apparent from Fig. 9, in the case of the anodic coupling indicated by the solid line, there is no bulging of the rising portion as compared with the case of the cathode coupling indicated by the broken line, and the transistor characteristics can be improved. Further, in the dry etching apparatus, the etching conditions were the same as those described above, that is, the pressure in the reaction vessel 31 was set to 10 Pa, the flow rate of the fluorine gas was set to 100 sccm, and the flow rate of the chlorine gas was set to 1 Torr. ~ lOOOsccm, a high frequency power of 13.56 MHz is applied from the high frequency power source 34 to 700 W, and as a result, the etching rate of the n-type amorphous germanium film 24 and the intrinsic amorphous germanium film 21 is about 1 500 A/min, and the base is made of tantalum nitride. The etching rate of the gate insulating film 3 composed is about 500 A/mi η. Therefore, the selection ratio in this case is about 3 times, and it can be practically applied. -11 - 1376744. Further, in the above embodiment, in the case of using a thin film transistor of amorphous germanium, an intrinsic amorphous germanium film formed on the upper surface of the gate insulating film 3 composed of tantalum nitride has been formed. 2 1 and the case where the n-type amorphous germanium film 24 is dry-etched' is described, but is not limited thereto. • For example, in a thin film transistor using polycrystalline germanium, a polycrystalline germanium formed on the tantalum nitride film may be used. The film is dry etched. Further, in a thin film diode (TFD: Thin Film Diode) using sand, the ruthenium film formed on the nitriding film may be dry etched. In addition, the present invention is not limited to the above embodiments, and can be freely changed and improved without departing from the gist of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing an example of a thin film transistor panel manufactured by a manufacturing method including the dry etching method of the present invention. Fig. 2 is a thin film transistor panel shown in Fig. 1. An example of a manufacturing method, a cross-sectional view of the initial steps. Figure 3 is a cross-sectional view of the subsequent steps of Figure 2. Figure 4 is a cross-sectional view of the subsequent steps of Figure 3. Φ Figure 5 is a cross-sectional view of the subsequent steps of Figure 4. Figure 6 is a cross-sectional view of the subsequent steps of Figure 5. Fig. 7 is a schematic diagram of an example of a dry etching apparatus. Fig. 8 is a schematic diagram showing another example of a dry etching apparatus. Fig. 9 is a view for explaining the characteristics of the transistor. [Main component symbol description] 1 Glass substrate 2 Gate electrode -12- 1376744

3 閘 極 絕 緣膜 4 半 導 體 薄膜 5 通 道 保 護膜 6 歐 姆 接 觸層 7 歐 姆 接 觸層 8 源 極 電 極 9 汲 極 電 極 10 薄 膜 電 晶體 11 覆 蓋 膜 12 接 觸 孔 13 畫 素 電 極 2 1 本 徵 非 晶矽膜 22 氮 化 砂 膜 23 阻 劑 膜 24 η型: 非, 晶矽膜 25 源 極 ' 汲極電極形成用膜 26 阻 劑 膜 27 阻 劑 膜 3 1 反 應 容 器 32 下 部 電 極 33 上 部 電 極 34 咼 頻 電 源 3 5 被 加 工 物 3 6 配 設 管 路 3 7 真 空 泵 浦 -13- 1376744 3 8 氣 體 導 入 管 3 9 共 通 配 設 管 路 40 第 1 配 設 管 路 4 1 第 2 配 設 管 路 42 第 1 電 磁 閥 43 第 2 電 磁 閥 44 第 1 質 流 控 制 器 45 第 2 質 流 控 制 器 46 氟 氣 體 供 給 源 4 7 氯 氣 體 供 給 源 -14-3 gate insulating film 4 semiconductor film 5 channel protective film 6 ohmic contact layer 7 ohmic contact layer 8 source electrode 9 drain electrode 10 thin film transistor 11 cover film 12 contact hole 13 pixel electrode 2 1 intrinsic amorphous film 22 Nitride film 23 Resistive film 24 η type: non, wafer film 25 source 'thorium electrode forming film 26 resist film 27 resist film 3 1 reaction container 32 lower electrode 33 upper electrode 34 咼 frequency power supply 3 5 Workpiece 3 6 Dispensing line 3 7 Vacuum pump-13- 1376744 3 8 Gas introduction pipe 3 9 Commonly equipped piping 40 1st piping 4 1 2nd piping 42 1st electromagnetic Valve 43 2nd solenoid valve 44 1st mass flow controller 45 2nd mass flow controller 46 Fluorine gas supply source 4 7 Chlorine gas supply source-14-

Claims (1)

1376744 修正本 第097 1 1 9800號「矽膜乾蝕刻方法」專利案 (2012年5月22曰修正） 十、申請專利範圍： 1.—種矽膜的乾式蝕刻法，其特徵爲：藉由使用包含氟氣 體以及氯氣體之混合氣體的平行平板型之乾式蝕刻，來 對已形成在氮化矽膜上的矽膜進行以前述氮化矽膜作爲 阻止層（stopper)的乾式蝕刻。1376744 Amendment to the Patent No. 097 1 1 9800 "Dry Film Dry Etching Method" (Amended, May 22, 2012) X. Patent Application Range: 1. Dry etching method for enamel film, characterized by: The tantalum film formed on the tantalum nitride film is subjected to dry etching using the tantalum nitride film as a stopper, using a parallel plate type dry etching including a mixed gas of a fluorine gas and a chlorine gas. 2. 如申請專利範圍第1項記載之矽膜的乾式蝕刻法，其中， 前述乾式触刻是陽極稱合的乾式蝕刻。 3. 如申請專利範圍第1項記載之矽膜的乾式蝕刻法，其中， 前述混合氣體係進一步包含惰性氣體。 4.如申請專利範圍第1項記載之矽膜的乾式蝕刻法，其中 前述氯氣體相對於前述氟氣體的流量比係1〜1 0。 5.如申請專利範圍第1項記載之矽膜的乾式蝕刻法，其中， 前述氯氣體相對於前述氟氣體的流量比係1〜20。2. The dry etching method of the ruthenium film according to the first aspect of the invention, wherein the dry etch is a dry etch of the anode. 3. The dry etching method of the ruthenium film according to the first aspect of the invention, wherein the mixed gas system further comprises an inert gas. 4. The dry etching method of the ruthenium film according to the first aspect of the invention, wherein the ratio of the flow rate of the chlorine gas to the fluorine gas is 1 to 10. 5. The dry etching method of the ruthenium film according to the first aspect of the invention, wherein the ratio of the flow rate of the chlorine gas to the fluorine gas is 1 to 20. 6. 如申請專利範圍第1項記載之矽膜的乾式蝕刻法，其中， 前述乾式蝕刻係在1〜100Pa的真空環境下進行。 7. —種矽膜的乾式蝕刻法，其特徵爲： 準備已在基板上層積有矽膜的被加工物； 將被加工物搬入至平行配置有高頻電極及對向電極 的平行平板型之乾式蝕刻裝置內，將前述被加工物的基 板載置於前述高頻電極上或是對向電極上之任一方； 將前述乾式蝕刻裝置減壓，將氟氣體以及氯氣體導 入至前述乾式蝕刻裝置內；以及 1376744 修正本 _前述高頻電極施加高頻，蝕刻前述矽膜， 其中，前述準備已在基板上層積有矽膜的被加工物 的步驟包含··在前述基板上形成矽氮化膜，在前述矽氮 • 化膜上形成由前述矽膜所組成之被加工物， 前述蝕刻矽膜的步驟包含：以前述氮化矽膜作爲阻 止層來對前述矽膜進行乾式蝕刻。 8.如申請專利範圍第7項記載之矽膜的乾式鈾刻法，其中， 目IJ述f虫刻是陽極耦合的乾式餓刻。 φ 9.如申請專利範圍第7項記載之矽膜的乾式蝕刻法，其中， 前述氟氣體係以惰性氣體稀釋來使用。 10.如申請專利範圍第7項記載之矽膜的乾式蝕刻法，其中， 前述氯氣體相對於前述氟氣體的流量比係1〜10。 » 1 1 .如申請專利範圍第7項記載之矽膜的乾式蝕刻法，其中， 前述氯氣體相對於前述氟氣體的流量比係1〜20。 1 2.如申請專利範圍第7項記載之矽膜的乾式蝕刻法，其中， 前述蝕刻係在1〜lOOPa的真空環境下進行。6. The dry etching method of the ruthenium film according to the first aspect of the invention, wherein the dry etching is performed in a vacuum environment of 1 to 100 Pa. 7. A dry etching method for a ruthenium film, comprising: preparing a workpiece to which a ruthenium film has been laminated on a substrate; and carrying the workpiece into a parallel flat plate type in which a high frequency electrode and a counter electrode are arranged in parallel In the dry etching apparatus, the substrate of the workpiece is placed on the high-frequency electrode or the counter electrode; and the dry etching apparatus is decompressed to introduce fluorine gas and chlorine gas into the dry etching apparatus. And 1376744 modifying the high frequency electrode to apply the high frequency to etch the ruthenium film, wherein the step of preparing the workpiece having the ruthenium film laminated on the substrate includes: forming a ruthenium nitride film on the substrate A workpiece composed of the ruthenium film is formed on the ruthenium nitride film, and the step of etching the ruthenium film includes dry etching the ruthenium film with the tantalum nitride film as a stopper layer. 8. The dry uranium engraving method of the ruthenium film according to the seventh aspect of the patent application, wherein the worm is an anode-coupled dry stagnation. The dry etching method of the ruthenium film according to the seventh aspect of the invention, wherein the fluorine gas system is diluted with an inert gas and used. 10. The dry etching method of the ruthenium film according to claim 7, wherein the flow ratio of the chlorine gas to the fluorine gas is 1 to 10. The dry etching method of the ruthenium film according to the seventh aspect of the invention, wherein the flow ratio of the chlorine gas to the fluorine gas is 1 to 20. 1. The dry etching method of the ruthenium film according to the seventh aspect of the invention, wherein the etching is performed in a vacuum environment of 1 to 100 Pa.
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