TWI376116B - De-glitch circuit - Google Patents

Description

1376116 ___ P200809002-TW 29792twf.doc/n 98109174 (without scribe line) correction replacement page VI, invention description: [Technical field] The invention relates to a cancellation circuit, and in particular to a pulse interference Eliminate the circuit. [Prior Art] In high-speed wired transmission systems, such as universal serial bus (USB), PCI-E or serial advanced technology accessories

(serial advanced technology attachment, SATA), the receiver usually uses a high-speed comparator to determine whether the received data signal is valid or noise. If the differential amplitude of the data signal is greater than the reference voltage and is judged as "data" by the comparator, the comparator may output "〇," to indicate that the data key at this time is valid data. Conversely, if: the differential of the signal: When the amplitude is smaller than the reference voltage and the comparator determines "noise,", the comparator loses x "1" to indicate that the data signal at this time is noise.圃1 is a schematic diagram of the interference waveform generated by the knowing pulse. Please refer to the drawing worker. In the ideal condition T, the wire trust transmitted by the transmitting end (f the rise time and fall time of the material letter $ Dm are regarded as zero, so that the data 'is larger than the reference code is judged by the comparator' in the actual high-speed transmission The condition 'out. However, the number (differential signal to Dp and Dm) is past zero, and when the transmission line is longer, the door is called, and the method is closer to ^ will be more miscellaneous. When (4) money series 0 transition Electrolytic cuts occur for Lai 丨 3 98109174 (without scribe line) Correction replacement page P200809002-TW 29792twf.doc/n The difference between the rising edge and the falling edge of the material signal Dp/Dm (ie the differential amplitude during switching) It will be temporarily less than the reference voltage, so the actual output waveform of the comparator, SReal, will produce glitch during the voltage level switching of the data signal Dp/Dm. This phenomenon will cause the transmission system to receive data errors. Usually, the output of such a high speed comparator is subjected to a De-Glitch circuit to eliminate unwanted pulse interference. The most common pulse interference cancellation circuit is shown in Figure 2A, and Figure 2A is a conventional Pulse interference cancellation Referring to FIG. 2A, the pulse interference cancellation circuit 200 uses a delay circuit 201 to cause a time delay of the pulse interference, and then the logic circuit and the original output signal of the comparator perform a logic operation (here and the gate). 202 is an example) to achieve the purpose of pulse interference cancellation. Figure B is a schematic diagram of the waveform of Fig. 2A. Please refer to the figure and Figure 2B. 'Compared with the output signal Sq and the delayed signal = after the logic calculation, and please The output waveform is dry == The pulse interference width is limited. When the pulse dry 2 is too wide: no matter how delayed, the input signal Sqd' cannot be completely staggered. Therefore, all possible pulse skew disturbances cannot be eliminated. The delay time of the delay circuit will be delayed with the process, and the SSCG resistance will be long and short, which will cause the U to shout wide _ dry limbs. The faster the speed, the longer the transmission line When the data is raised in the rising light 1376116 98109174 (no ray) correction replacement page P200809002-TW 29792twf.doc / n the time of the fall will be higher in the cycle, thus producing a wider pulse interference 'making the pulse The interference cancellation circuit 2 is no longer sufficient. Another common practice is to use a Peak Detector as shown in Figure 3A. Figure 3A is a schematic circuit diagram of a conventional peak detector. Figure 3B is a diagram 3A signal waveform diagram. Referring to FIG. 3B and FIG. 3B, the principle of the peak detector 300 is to utilize the unidirectionality of the two-stage bodies D1 and D2, when the data signal Dp/Dm is larger than the lead of the second-order bodies D1 and D2. When the dust is energized, 1 charge the capacitor C, so that the dragon level of the capacitor c will rise. When the miscellaneous Dp/Dm is switched on the voltage level, since the one's and the bodies D1 and D2 are unidirectionally conductive, they will not discharge to the input terminal, and will only be discharged by the discharge current IL of the micrometer. Therefore, as long as the data signal Ο〆% is available, the voltage of the output 〇ut can be maintained above the voltage Va. >. When there is no data on the 5th 1)/〇111 of the field, the output signal Out(4) will be pulled to the (B) by the discharge current 1]1 to achieve the purpose of judging the data signal. The peak debt detector 3〇〇 has two shortcomings, one of which is = path, the transmission delay (Pn) pagatk) nDday) is related to the amplitude of the input signal (ie, the data #Dp/Dm). When the amplitude of the signal is small, the charging current of the capacitor through the polar bodies D1 and D2 is smaller, and the output is delayed by, and the longer, that is, the voltage of the output signal Qut is low. The time during which the voltage level is charged to the 冋 voltage level is elongated. In contrast, when the amplitude of the output signal is larger, the output signal is changed by 1", and the transmission delay is longer, that is, the output ^&amp The voltage of Out is extended from the high voltage level to the low voltage level. Therefore, the peak detector 300 has no way to effectively control the transmission delay. 5 1376116 P200809002-TW 29792twf.doc/n 98109174 (without line) Correction of the replacement page is generally not practical to use the ideal secondary body. If the MOS electric b body is used as the unidirectionality of the primary body, there will still be a slight reverse current, and the reverse current will The DC transition point cannot be controlled by precision. In the general high, the age, the ride has DC (four) points. If you want to use the peak detector 300 to avoid the pulse interference problem, it will make the DC (four) point and the AC transition point more difficult to design. And the transmission system will have the specifications of the transmission delay. The use of the peak detector 3 can not accurately control the delay of this transmission. Therefore, the peak detector 3 (9) 2 can meet the pulse of the 'but the shadow _ transmission pure other specifications of the design, so that the application There are still many restrictions. [Invention] The invention provides a pulse interference cancellation circuit, which can eliminate the data signal ~ the pulse interference generated by the comparator when performing voltage level conversion. ^Inventive Proposed - Kind of Pulse Dry (4) In addition to the circuit, it includes a plurality of signals. These signal transmission units are connected in series to each other to form a signal transmission = serial, and a transmission transmission unit serial (four) - a signal transmission unit is connected to a $bit signal. The signal transmission unit includes a first switch, a - a delay circuit switch. The first end face of the first switch is connected to the signal transmitting unit string feeding unit. The input end face of the first delay circuit is connected to the terminal & The output of the first delay circuit is between the voltages. When the digital signal is the first logic, the first switch flute-passes the second switch to be turned on. When the digital signal is the second logic, the brother-switch is turned on. The second switch is non-conducting. In the embodiment of the present invention, the first delay circuit includes P200809002-TW 29792twf.doc/n 98109174 (without scribe line) to correct the replacement page resistance and _. The first end of the first switch is connected to the second end of the first switch, and the second capacitor is between the second end of the first resistor and the second voltage. In the embodiment of the present invention, each of the signal transmitting units further includes - Buffer g 'the input end of the input terminal of the _ delay circuit of the input terminal (4) and the buffered output _ is connected to the money transfer unit string-level signal transmission unit. In an embodiment of the invention, each of the signal transmitting units further includes a first-inverter, a third switch, a second delay circuit, a fourth switch, and a second inverter. The input end of the first-inverter is the output of the delay circuit. The first end of the second switch - the wheel end of the inverter. The input end of the second delay circuit is coupled to the second end of the third switch. The first switch is connected between the output of the second delay circuit and the third voltage. The input end of the second inverter is connected to the output end of the second delay circuit, and the output of the second reverse: is mixed to the lower __ level signal transmission unit of the money transfer unit (four). When the digital signal is the first logic, the third switch is non-conductive. The four switches are conductive. When the digital signal is the second logic, the third switch is turned on, and the fourth switch is not turned on. In an embodiment of the invention, the second delay circuit comprises two resistors and a second capacitor. The first end of the third switch of the second resistor is the first end. The second capacitor is lightly connected between the second end of the second resistor and the second voltage. Based on the above-mentioned pulse interference cancellation circuit of the present invention, when the number is 第-logic, let these signals transmit a single (four) step output _ logic ^ and when the number is recorded at the second lag, Digital signal. In this way, when the digital signal generates pulse interference (that is, the digit: 1376116 P200809002-TW 29792twf.doc/n ----_______, 98109174 (without line) corrects the replacement page number as the first logic) When the signal transmission unit is shipped, and the digital signal is returned to the second logic, the pulse interference is eliminated due to the synchronous output of the signal transmission unit. In order to make the above features and advantages of the present invention more comprehensible, the following embodiments, as well as the related aspects, are set forth below. [Embodiment] A system diagram of a pulse interference canceling circuit of an embodiment of the invention is shown. = The pulse interference cancellation circuit 4A of Fig. 4A has a signal transmission early U~41〇-X. The signal transmitting units 410-1~410X serially transmit the serial strings of the units, and the signal transmitting unit string is ^^^5_the sending unit 4G1J receives the number sqing, wherein the digit HS: lgl = if it is a south speed transmission The output signal of the comparator under the system. When the number of slogans d*1 is changed to the first logic, the signal transmission unit ^"40-X @step_first logic 1 digit signal s zip to = logic =, the signal transmission unit is 410-x less The SDJ is passed in order. The signal transmission unit is arranged in the middle of a signal transmission in the middle of the array, and the output of the early detection signal is used as the output end of the pulse interference cancellation circuit 400 to provide the round-out signal Sout. ^ (4) Figure 2 is the waveform of the digital signal S〇igi and the output signal S(10) in Figure 4A. Figure 4A and Figure 4B, when the digit number is changed by the second logic (for example, the first logic (for example, logic 峨410J) ^l0~x. When the 'sequence number number SDigi changes to the logic low level, the 遽 运 70 70 70 ω χ χ 输出 输出 输出 输出 输出 输出 输出 输出 逻辑 逻辑 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 Marking) Correction Replacement Page P200809002-TW 29792twf.doc/n The falling edge time in the sDigi waveform Τ4ι is almost the same as the falling edge in the output signal s〇ut waveform. According to the operating principle of the comparator under the speed transfer system, It is assumed that the comparator generates a pulse interference PL1 at times T42 to T43, and assumes that the pulse interference PL1 is at a logic high voltage level, that is, the digital signal SDigi changes to a logic high voltage level at times T42 to T43, and the signal transmission unit 410_1 ~410_X will pass the digital signal SDigi in sequence, so that the pulse interference PL1 should appear in the output signal s〇ut at time T43~T44 (as indicated by the dotted line, the pulse interferes with PL2). However, at time Τ43, the digital signal SDigi Change back to the logic low voltage level so that The signal transmission units 41〇_1 to 41〇-X will synchronously output the logic low voltage level. Therefore, in the time T42 to T43, the signal transmission unit 41〇1~4ΐ〇_χ will transmit the pulse interference PL1 one by one. The logic high voltage level, and at time T43, the signal transmitting units 410_1~410-X synchronously output the logic low voltage level, so that the pulse interference PL1 is eliminated on the way of transmission, and the output signal s〇ut remains output. Logic low voltage level, where 'period TD is the length of time delay of the signal transmission unit string 41〇_1~41〇X. If the period Td is to be adjusted, the number of signal transmission units can be adjusted, or each signal transmission can be adjusted. The time of the unit delay. And when the period TD is greater than the bit time of one bit, regardless of the width of the pulse interference PL1, the digital signal will return to the output logic low voltage level. The synchronous output logic low voltage level of the transfer units 41〇_1~41〇X is eliminated. Next, how the signal transfer unit is implemented is described in detail so that the present invention is 98109174 (without scribe line) The correction replacement page P200809002-TW 29792twf.doc/n is further specific. The signal transmission unit 410-1 is taken as an example, and the signal transmission units 410_2~410-X are deduced by analogy. Fig. 5 is the signal transmission of Fig. 4A. A circuit diagram of the unit 410_1. Referring to FIG. 5, in the signal transmission unit 410-1, it includes a first switch SW1, a first delay circuit, and a second switch SW2. In this embodiment, the first delay circuit includes a first resistor R1 and a first valley C1. The first end of the first resistor R1 serves as an input terminal of the first delay circuit to consume the second end of the first switch SW1. The first capacitor ci is coupled between the second end of the first resistor R1 and the second voltage (here, the ground voltage is taken as an example). In other embodiments, the parasitic resistance and parasitic capacitance on the signal path can be utilized to implement the first resistor R1 and the first capacitor C1, respectively, thereby eliminating physical and physical capacitance. The first end of the mountain switch SW1 is the input h of the signal transmission unit 41〇J for light connection to the previous stage signal transmission unit in the serial transmission unit string. Since the signal transmitting unit 410-1 is the first signal transmitting unit of the signal transmitting unit string, the first end of the switch SW1 is used to receive the digital signal sDigi. The second end of the switch SW1 is lightly connected to the first end of the resistor R1. The switch SW2 is lightly connected between the second end of the resistor R1 and the first (fourth) (here, the ground voltage is =). In the present embodiment, the second end of the resistor R1 is the output end of the signal transport unit it__l for reduction to the lower-level mail feed unit (here, the money transfer unit 2) in the money transfer unit string. One of ordinary skill in the art can implement the above-described opening in any manner, SW1 and SW2. For example, the switch SW1 can be implemented by using a transfer gate to implement the switch SW1, and a gold-oxide semiconductor (NMOS) transistor.

Referring to FIG. 4B and FIG. In the signal transmission unit 410 2~410 X 1376116 98109174 (without line) correction replacement page P200809002-TW 29792twf.doc/n, when the digital signal SDigi is at a logic low voltage level (for example, time T41~T42), the first The switch SW1 is non-conducting, and the second switch tearing 2 is turned on, so that the signal transmitting units 410-1~410-X will synchronously turn off the grounding voltage (which is regarded as the logic low voltage level). When the digital signal 8 is called a logic high voltage level (for example, time T42~T43), the first switch SW1 is turned on and the second switch SW2 is non-conducting, so that the digital signal SDigi charges the capacitor C1 and uses the RC. The charging effect of the circuit causes the transmission delay of the digital nickname SDigi, which is a logic high voltage level. The transmission delay time can be adjusted by changing the resistance value of the resistor R1 and the capacitance value of the capacitor C1. When the bit number SDigi returns to the logic low voltage level again (for example, time T43~T44), the circuit operation of the 彳s number transmitting unit 41〇_1~410_X is the same as the time T41~T42, and the signal transmitting unit逻辑 Outputs a logic low voltage level at the same time. The circuit shown in Figure 5 is only one of the embodiments of the signal transfer unit. The embodiment shown in Figure 5 can be varied by one of ordinary skill in the art. For example, Fig. 6 is a schematic view of another circuit of the signal transmitting unit 410J of Fig. 4A. Here, only the signal transmission unit 41〇_1 is taken as an illustrative example, and it can be deduced by the ## transmission unit 410_2~41〇. Referring to FIG. 5 and FIG. 6, the difference is in the buffer 6〇1, and other similar functional elements use similar symbols, and are not described herein again. In the embodiment shown in Figure 6, the second end of resistor R1 is not the output of the signal transfer unit. The input end of the buffer 601 is coupled to the second end of the resistor R1, and the output end thereof is used as the round-out end of the signal transmitting unit 410_1 to be coupled to the next-stage signal transmitting unit in the string of signal transmitting units (here is signal transmission) Unit 41〇_2). Figure 11 1376116 98109174 (without scribe line) correction replacement page P200809002-TW 29792twf.doc/n 6 The circuit operation of the embodiment is the same as the embodiment of FIG. 5, and the addition of the buffer 〇1 can increase the transmission of the signal transmission unit 410-1 Delayed time. The embodiment shown in Fig. 5 can be modified in other ways than those of ordinary skill in the art, in addition to the signal transfer unit of Fig. 6. For example, Fig. 7 is a schematic diagram of still another circuit of the signal transmitting unit 410-1 of Fig. 4A. Here, only the signal transfer unit 410_1 is taken as an example, which can be deduced by the signal transfer unit 410-2~410-X. Referring to FIG. 5 and FIG. 7, similar components are used for similar functions, and will not be described again. The difference from FIG. 5 is that the signal transmission unit of the embodiment shown in FIG. 7 further includes a first inverter 701, a third switch SW3, a second delay circuit, a fourth switch SW4, and a second inverter 7〇. 2. In this embodiment, the second delay circuit includes a second resistor R2 and a second capacitor C2. The first end of the second resistor R2 is coupled to the second end of the third switch SW3. The second capacitor C2 is coupled between the second end of the second resistor R2 and the second voltage (here, the ground voltage is taken as an example). In other embodiments, the parasitic resistance and parasitic capacitance on the signal path can be utilized to implement the second resistor R2 and the second capacitor C2, respectively, thereby eliminating physical and physical capacitance. As shown in Fig. 7, the second end of the first-resistor R1 is not the output terminal of the signal transmission unit 41〇_1. The input end of the inverter 7〇1 is lightly connected to the second end of the resistor R1, and the output end thereof is connected to the first end of the switch SW3. The first end of the resistor R2 is connected to the second end of the switching period. The capacitor C1 is coupled between the second end of the resistor R2 and the ground voltage. The switch SW4 is connected between the = terminal of the resistor R2 and the third voltage (here, the system voltage Vcc is taken as an example). The input terminal of the inverting S 702 is connected to the second end of the resistor R2, and the output thereof is 12 1376116 98109174 (without a line). The replacement page P200809002-TW 29792twf.doc/n is the output of the ## transmission unit 410-1. The next level signal transmission unit (here, the signal transmission unit 410-2) is used to be connected to the signal transmission unit string. Referring to FIG. 4B and FIG. 7 , when the digital signal sDigi is at a logic low voltage level (for example, time T41 to T42), the switches SWi and SW3 are non-conductive, and the switch SW2 is SW4, so that the capacitor C1 is via the switch SW2. The discharge is performed, and the system voltage Vcc charges the capacitor C2 via the switch SW4. At the same time, the inverter 7〇1 receives the Lu ground voltage (which is regarded as the logic low voltage level) via the switch SW2 and outputs a logic high voltage level, and the inverter 702 receives the system voltage Vcc via the switch SW4 (considered Logic high voltage level) and output logic low voltage level. Therefore, the signal transmitting units 410-1 to 410-X simultaneously output logic low voltage levels. When the digital signal SD jgj transitions to the logic high voltage level (for example, time T42~T43) 'the switches SW1 and SW3 are turned on, and the switch (4) is non-conducting, so that the digital signal sDigi will be connected to the capacitor via the switch SW1 and the resistor R1. Cl is charged. At this time, the inverter 701 still outputs a logic high voltage #$ bit' and the inverter 702 rotates the logic low voltage level because the capacitor C2 maintains its input terminal at a logic high voltage level. When the voltage of the capacitor C1 is charged to a voltage level sufficient for the inverter 701 to switch the output, the inverter 701 converts the output logic low voltage level. After the output of the inverse 〇1〇1 is converted to the logic low voltage level, the charge of the capacitor C2 begins to discharge to the output of the inverter 701 via the resistor R2 and the switch SW3. When the voltage level of the capacitor C2 is discharged to a voltage level sufficient for the inverter 7〇2 to convert the output, the inverter 7〇2 will convert the output logic high voltage level 13 1376116 P200809002-TW 29792twf.doc/n |~ 98109n7^ underline) Correction of the substitution. The signal transmission unit 4101 transmits a delay_ due to the charging of the capacitor C1, the discharge of the capacitor C2, and the shifting of the voltage level. Therefore, the domain transmission delay can be adjusted by changing the resistance values of the resistors R1 and R2 and the capacitance values of the capacitors α and C2. When the digital signal SDigi reverts to the logic low power leveling time T43~T44), the money transmission element, the full circuit operation will be the same as the time Τ41~Τ42, so that the signal transmission unit 41 χ χ 同步 synchronous output Logic low voltage level. In addition, in the embodiment of FIG. 7, the switches SW1 and SW3 can be completed by using a transfer gate, and the _SW2 can be implemented by using a NM〇s transistor, and the switch S W4 can be a P-type metal oxide semiconductor (pM). The transistor is completed. And 'the resistors R1 and R2 can be the parasitic resistance of the circuit, and the capacitors C1 and C2 can be the parasitic capacitance of the wire to the ground. According to the above, an embodiment will be further described below. FIG. 8A is another embodiment of the present invention. A schematic diagram of a system of a pulse interference cancellation circuit according to an embodiment. Referring to FIG. 8A', in the present embodiment, the pulse interference cancellation circuit 800 is connected in series with three signal transmission units tl 810_1 810 810 - 3 to form a signal transmission unit string. In addition, in this embodiment, the first delay circuit and the second delay circuit are implemented by using the parasitic resistance and the parasitic electric valley of the signal path and the component, thereby eliminating the physical resistance and the physical capacitance. In the signal transmission unit 810J, The input terminal of a switch (here, the transmission gate T1) receives the digital signal. The positive control terminal and the negative control terminal of the transmission gate T1 receive the digital signal SDigi and the signal SDigiB, respectively. s〇igiB is the inverted signal of the digital signal sDigi. The second switch (here ^ 1376116 P200809002-TW 29792twf.doc/n ----- 98109174 (without scribe line) correction replacement page NMOS transistor Ml) is controlled by The signal sDigiB, wherein the gate of the t crystal M1 receives the signal sDigiB, the source of which is coupled to the ground voltage, the drain of which is coupled to the output of the transmission gate T1. The input of the inverter 801 is coupled to the output of the transmission gate T1. The input end of the third switch (here, the transmission gate T2) is coupled to the output end of the inverter 8〇 1. The positive control terminal and the negative control terminal of the transmission gate 2 receive the digital signal sDigi and the signal sDigiB, respectively. (here, PM〇s transistor M2) is controlled by the digital signal sDigi. Among them, the gate of the transistor M2 receives the digit 彳5 by S〇igi, and its source is connected to the system voltage VCC, which is inexhaustly transmitted. The output terminal of the gate T2. The input end of the inverter 8〇2 is coupled to the output end of the transmission gate T2, and the output end thereof is the output end of the signal transmission unit Woj for coupling to the next stage of the signal transmission unit string. The first switch (not shown) of the signal transmission unit 810-2. The signal transmission unit 81 〇_2 and 81 The circuit structure of 3 is similar to that of the signal transmission unit 810_1, and therefore will not be described again. Fig. 8B is a waveform diagram of the digital signal and the output signal of Fig. 8A. Referring to Fig. 8A and Fig. 8B, at time T81, the digital signal 80 is old. For the logic low voltage level, the transmission gates T1 and T2 are non-conducting, and the transistors M1 and are turned on, so that the parasitic capacitance (not shown) of the signal path PATH1 is discharged through the transistor M1, and the system voltage Vcc will be The parasitic capacitance (not shown) of the signal path PATH2 is charged via the transistor M2. At the same time, the inverter 801 receives the ground voltage (which is regarded as the logic low voltage level) via the transistor M1 and outputs a logic high voltage level, and the inverter 8〇2 receives the system voltage Vcc via the transistor M2. The same logic high voltage revenge) and output logic low voltage level. Therefore, the rounding signal S1 of the signal transmitting unit 810_1 •, the output signal S2 of the signal transmitting unit 81〇_2, and the letter 15 P200809002-TW 29792twf.doc/n 98109174 (without a line) correct the replacement page number transmitting unit 810 The output signal s〇ut of 3 will be synchronously converted to the logic low voltage level. At time T82, 'the digital signal sDigi transitions to the logic high voltage level', the transmission gates T1 and T3 are turned on, and the transistors M1 and M2 are non-conducting, so that the digital signal SDigi will pass through the transmission gate T1 and the signal path ^ATH1. A parasitic resistance (not shown) charges the parasitic capacitance (not shown) of the signal path pATH1. At this time, the inverter 8〇1 still outputs a logic high voltage level' and the inverter 802 outputs a logic low voltage level due to the parasitic capacitance of the signal path PATH2 (not shown) maintaining its input terminal at a logic high voltage level. Bit. Therefore, at time T82, the output signals SI, S2, and Sout of the signal transfer unit remain at the logic low voltage level. When the voltage level of the parasitic capacitance (not shown) of the signal path PATH1 is charged enough to cause the inverter 8〇1 to switch its output voltage level, the output of the inverter 801 is switched to the logic low level. After the output of the inverter is converted to a logic low level, the parasitic capacitance of the PATH2 (not shown) begins to be discharged to the reverse phase via the parasitic resistance (not shown) of the signal path pATH2 and the transfer gate T2. The output of the 8〇1. When the electrostatic dust level of the parasitic capacitance (not shown) of the signal path PATH2 is discharged enough to allow the inverter 802 to switch its output (four), the inverter will convert its output to the logic level. Due to the charging of the signal path ρΑτΗΐ parasitic electric valley (not shown), the parasitic capacitance of the signal path ΡΑΤΗ2 (the unillustrated discharge, the electric f, and the voltage level of the inverters 8〇1 and 802 are converted to cause the k transmission The transmission delay time of the unit 810_1 is (1). That is to say, when the digital signal SDigi is switched from the logic (4) logic high power level 1376116 P200809002-TW 29792twf.d〇c/n ________, due to the signal transmission unit 81 ( L1 No. S1 is delayed by a period of τ only #, so that its output signal can be pushed in the same way, and should be grounded to the logic high electric scale. After the output signal 81 of the pressure level, the same delay is given to one = logic, electrical output signal S2 transitions to a logic high level. ^ 810" receives an output signal that is at a logic high voltage level =

For example, the output of the signal transmission unit should be = the signal S2 is delayed - the period Td3 is converted to the logic high voltage level. However, since the digital signal SDigi transitions to a logic low level at time T83, the signal transmission unit 810_3 expects the logic high voltage level to turn out after the end of the period τ 〇 3 'signal bit signal SDigi transition to logic The synchronous output caused by the low voltage level is eliminated, and the output signal Sout of the signal transfer unit 81〇3 is maintained at the logic low voltage level.

In addition, the pulse interference PL 1 to be eliminated is a logic low voltage level, which can be achieved by changing the connection relationship and circuit operation according to the circuit of the embodiment of Fig. 7. Figure 9 is a further circuit diagram of the signal transfer unit 410j of Figure 4A. Referring to Fig. 7 and Fig. 9', the biggest difference lies in the switches SW2 and SW4 of this embodiment. In this embodiment, the switch sw2 is connected between the second end of the resistor R1 and the system power Vcc, and the switch SW4 is coupled between the second end of the resistor R2 and the ground voltage. When the digital signal is at the logic high voltage level, the switches SW1 and SW3 are non-conducting, and the switches SW2 and SW4 are turned on, so that the inverter 701 receives the system voltage Vcc (which is regarded as the logic high voltage level) and the output logic is low. The voltage level, and the inverter will receive the ground voltage (as the logic low 17 1376116 98109174 (without line) correction replacement page P200809002-TW 29792twf.doc / n voltage level) and output logic high voltage level. Also, the system voltage Vcc charges the capacitor C1. When the digital signal is at the logic low voltage level, the switches SW1 and SW3 are turned on, and the switches SW2 and SW4 are not turned on, so that the capacitor C1 and the over resistor R1 are discharged. At this time, since the voltage of the capacitor C1 is still at the logic level, the inverter 7〇1 outputs a logic low voltage level, and the inverter 702 still outputs a logic high voltage level. When the voltage level of the capacitor C1 is discharged to a voltage level sufficient for the inverter 7〇1 to convert the output,

Phaser 701 converts the output logic high voltage level. At this point, capacitor c2 begins to charge. When the capacitor C2 0 is charged to a voltage level sufficient to allow the reverse phase stomach to turn 7〇2, the inverter will convert the output logic low voltage by 2 bits. The transmission delay time of the signal transmission unit is caused by the discharge of the capacitor C1, the charging of the capacitor C2, and the conversion of the inverter. The transmission delay (4) can be adjusted by changing the resistance value of R2 and the capacitance values of capacitors C1 and C2.

Coincidentally, in other real-time t, the inverting 11 or age = power supply can be replaced by a precision current source. Thereby, the transmission extension and movement can be reduced to make the circuit design of the high-speed transmission system more complicated. ’ ί Γϊ Γΐ Γΐ Γΐ ’ 让 让 让 让 让 让 让 让 让 让 让 让 让 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些 这些P200809002-TW 29792twf.doc/n Logic low-powered bit' then modify the circuit so that the operation of the pulse-interfering yang circuit is opposite to the above, and the pulse-interference can be eliminated as well. Although the present invention has been disclosed in the above embodiments, it is not used. In the present invention, any one of ordinary skill in the art, in the spirit and scope of the invention, may make some changes and refinements, so the scope of protection of the present invention is defined by the (4) patent (4). [Simple diagram of the diagram] Hungary + Figure 1 is a schematic diagram of the generation of pulse interference waveforms. 2A is a schematic diagram of a system of a conventional pulse interference cancellation circuit. FIG. 2B is a schematic diagram of a signal waveform of FIG. 2A. 3A is a circuit diagram of a conventional peak detector. FIG. 3B is a schematic diagram of the signal waveform of FIG. 3A. 4A is a schematic diagram of pulse interference cancellation according to an embodiment of the present invention. Illustrated, dead Figure 4B is a waveform diagram of the digital signal and the output signal in Figure 4A. FIG. 5 is a circuit diagram of the signal transfer unit 410_1 of FIG. Fig. 6 is another circuit diagram of the signal transmission unit Doukawa-丄 of Fig. 4A. FIG. 7 is still another circuit diagram of the signal transmission unit 41〇j of FIG. 4A. FIG. 8A is a schematic diagram of a pulse interference cancellation circuit according to another embodiment of the present invention. Figure 8 is a waveform diagram of the digital signal and the output signal in Figure 8. Figure 9 is another circuit diagram of the signal transmission unit 41〇j of Figure 411376116 P200809002-TW 29792twf.doc/n -------- 98109m (without line) correction replacement page [main component symbol description] 200, 400, 800: pulse interference cancellation circuit 202: and gate 300: peak detector 410-1~410-X '81〇_1~81〇 ”: Signal transmission unit 601: Buffers 701, 702, 801, 802: Inverters C, Cl, C2: Capacitors D1, D2: Secondary body IL: Current Va: Voltages PL1, PL2: Pulse interference Td, TD丨, TD2, TD3: period Rl, R2: resistance SW BU2, SW3, SW4: switch Sideal, SReai, Sdg. Waveform

Sq, SqD, Out, SDigi, SDigiB, Sout, Dp/Dm, SI, S2: Signal T4, T42, T43, T44, T81, T82, T83: Time ΊΠ, T2: Transmission gate Ml, M2: Transistor Vcc:糸 system voltage 20

Claims (1)

1376116 1376116 98109丨74 (without line) correction replacement page P200809002-TW 29792twf.doc/n VII. Patent scope ·· I A pulse interference cancellation circuit, including: ^ a transmission unit, these signal transmission units are connected in series The serial number of the transmission unit is serialized and the first unit of the signal transmission unit is received by the unit, wherein the signal transmission unit includes the ... column; the -_ 'the first end thereof The W-level (four) transfer unit is reduced to the money transfer unit string logic, wherein when the number is - the first series is turned on, when the digital signal is - the second logical second end; the delay circuit, the input end _ a first switch to the first switch of the first switch, coupled to the rim of the first delay circuit, wherein the digital signal is the first logic; (2):;: through 'when the digital When the signal is the second logic, the first and the first resistors are lightly connected to the second end of the first switch; and the second capacitor is coupled to the second end of the first resistor. The second power is that (4) 2 depends on the _ read cancellation circuit, and the 冤 resistor is parasitic resistance. 21 1376116 P200809002-TW 29792twf.d〇c/n 4. As stated in the pulse described in her second item, where the _th capacitor is a parasitic capacitance. (4) Circuits' 5. The pulse interferences as recited in the application of the patent specification n each of the signal transmission units further include a buffer wheel that connects the wheel: the output of the circuit and the output of the buffer = The 忒托号 transmits the next level of signal transmission unit in the early 兀 string. 6. The pulse drying method as described in claim 1 of the patent scope of the invention, wherein each of the signal transmission units further comprises: a recording circuit, a phase. The input end face is connected to the first delay circuit of the wheel 9 and the second switch 'the _th terminal minus the first-inverter, wherein when the digital signal is the first logic, the third pass When the digital signal is the second logic, the third switch is a derivative=lead-first-delay circuit, and its input terminal is supplemented to the third-second of the third switch, and the output of the second delay circuit is lightly connected to the second delay circuit. The terminal and the second voltage d ', the middle and the Wei position signal are the first logic, the switch is turned on, when the digital signal is the second logic, the current is non-conducting; and the fourth switch * the reverse ΪΓ 'the input end thereof The rounding end of the second delay circuit is lightly connected, and the output end of the second inverter is lightly connected to the next stage signal transmitting unit in the signal transmitting unit t. Flat π series 7. If the application is specifically _ 6 received, the third delay circuit includes: 22 1376116 P200809002-TW 29792twf.doc/n 98109174 (without line) correction replacement page a second end of the third switch; and a second capacitor coupled between the second end of the second resistor and the second voltage. The pulse interference cancellation circuit of claim 7, wherein the second resistance is a parasitic resistance. A pulse interference cancellation circuit as described in claim 7 wherein the second capacitance is a parasitic capacitance. 1) The pulse interference cancellation circuit of claim 7, wherein the second voltage is a ground voltage. 11. The pulse interference cancellation circuit of claim 6, wherein the first voltage and the third voltage are a ground voltage and a system voltage, respectively. 12. The pulse interference cancellation circuit of claim 6, wherein the first and the third switches are each a transmission gate. 13. The pulse interference cancellation circuit of claim 6, wherein the second and fourth switches are an N-type metal oxide semiconductor (NMOS) transistor and a p-type gold-oxygen semiconductor (pM). 〇s) transistor. The pulse interference cancellation circuit of claim 1, wherein the first logic and the second logic are a logic high level and a logic low level, respectively. twenty three