TWI376017B - Method of forming and operating an assisted charge memory device - Google Patents

Description

1376017 IX. Inventive Note: [Related References for Related Applications] This application claims the priority of US Provisional Application No. 60/633,415, filed December 7, 2004, entitled "Auxiliary Charged Nitride. Memory Element and Its Operation (Assisted Charged Nitride-Trap

Memory Device and its Operation.)". TECHNICAL FIELD OF THE INVENTION Non-volatile memory (N V Μ) refers to a semiconductor memory that continuously stores information (eg, data) even when the power supply is removed. NVM includes masked read-only memory (Mask ROM), programmable read-only memory (PROM) 'erasable programmable read-only memory (EPR〇M) and electronic erasable programmable read-only Memory (EEPROM). Traditionally, the N VM has been programmed to store data that can be stored for long periods of time and that can be read, erased, and reprogrammed multiple times. [Prior Art] Traditional EPROM tunnel oxide (ΕΤ〇χ) and nitride trap read-only • Memory (NR0M) uses channel hot electron (CHE) injection to program memory cells to a threshold voltage ( Vt) level. By using channel hot electron (CHE) injection to quickly program a memory cell, a large stylized current is required because of the poor stylized efficiency of the che. As a result, the memory unit programming rate is limited due to its high power consumption. Another example is the injection of nitride electrons by thermoelectric holes (H〇t H〇1 e

Injection Nitride Electron storage ; PHINES) is a unitized program that uses a band-to-band thermoelectric hole (Band_t〇Band wrist; P930193 1376017 BTBHH) to inject a bamboo edge 7L into a low threshold voltage (Vt) level. . However, the BTBHH 4 . > _ n master entry system is extremely slow and requires a long stylization time to program the rate of the unit, which makes the PHINES single 疋 not efficient.

To overcome these shortcomings, the memory unit provided has an auxiliary charge (ac) in the electrical (four) layer of the memory element (AC: L-body). Auxiliary charge change for the total operational rate and rate of nitride trapped memory cells in AC 5 memory elements.

[Summary of the Invention] / Quanjia specific embodiment in a charge trap AC memory element

An auxiliary charge memory (AC memory) unit is formed in ^ for storing lean material and performing memory operations. The Ac memory unit has a -p-type substrate formed in a source region and a drain region in the substrate portion. The channel is inserted between the source and the drain region in a portion of the substrate, and a first dielectric device A layer is formed over the channel on the substrate. The AC memory further includes two: (ie, the AC side and the data side) charge trapping layer, which is formed in the first system formed on the first:::::: on the charge trap layer and - the control gate is sufficient Xi v - two electric layer. In addition, the data side of the charge trapping layer can be electrically operated as long as the data side can have various degrees of charge representing different levels of potential; (:) level. In order to prepare for the formation of the source region or; and the region of the pole region to the ground potential is supplied to the potential), the system is also connected to the region. - Operating voltage (eg, at least one of the source region or the drain region of the bias voltage source), and the power plant line is supplied to the control electrode. The charge is formed on the side of the AC memory Ρ 930193 1376017: the charge trapping layer At least in part - the side of the charge is stored on the AC side of the destructive layer and has a fixed high threshold voltage, and the far charge is used for the auxiliary charge of the AC memory cell. One side is used to store data and perform memory: set F < data AC memory unit AC side is fixed at - high threshold voltage (vt) level by trapping charge in charge trapping layer. Use = auxiliary data, which can be at any threshold voltage level according to the memory operation. The memory operation includes stylization, reading and erasing. By making the = memory in the Ac side fixed at a high level The voltage limit (Vt) level, an abrupt electric field = help between the Ac side and the data side. The steep electric field enhances the stylized efficiency of the AC memory unit for the AC memory unit. The fixed side of the Ac side is high. The voltage-limited cow level limits the stylized current required for the hot metal (HE) stylization operation on the AC memory. As a result, the charge trap AC memory cell achieves a low programmed power requirement and thus has a higher stylized efficiency and higher rate. Preferred embodiments of the AC memory of the present invention include channel hot electrons (CHE AC memory), Fowler-Nordheim (FN AC memory) and mixed AC memory. To form CHE AC memory, the channel hot electron injection system is used on one side (AC side) of the AC memory unit to increase it to a fixed high threshold. Voltage (Vt) while preserving the other side of the two-sided memory cell (data side) at low threshold voltage (Vt). To form FN AC memory, use positive FN injection (+FN) or negative FN injection ( -FN) to program the entire charge trapping layer. The FN implant is uniformly applied to the entire charge trapping layer of the AC cell by applying a positive or negative bias between the P901193 7 field 017 and the substrate. Threshold voltage (Vt). To complete the formation of FNAcr = early ' 'band-to-band thermoelectric hole (BTBHH) injection system to reduce the second side to low threshold voltage while maintaining the auxiliary charge in the AC side

Threshold voltage. After using Βτ_, the data side is now available for storage. This information may be at any threshold voltage level. In order to form a mixed AC# memory, the channel hot electrons (CH-printing is used to bring the side to a very high threshold voltage (10) level. Then use the other side of the two sides ac memory 7L early (bean side) Band-to-band thermoelectric hole injection] is used to reduce the data side to a low threshold voltage (10) level, which can be any threshold voltage (Vt) level used to store data. [Embodiment]

DETAILED DESCRIPTION OF THE INVENTION Reference numerals are used to refer to like elements throughout the drawings. FIG. 1 shows a preferred embodiment of an AC memory unit 1A in accordance with the present invention. The AC memory unit 1A has a p-type substrate 1〇5, and the substrate 105 has a source region 110, a drain region 115, and a channel 120 interposed between the source 11 and the drain 115 region, which is attached to the substrate. 105 - part of it. The unit also includes a first dielectric layer 125 on the substrate 1 and above the channel 120, and a two-sided charge trap layer 130 on the first dielectric layer 125. A second dielectric layer 140 is disposed on the charge trap layer 130, and a control gate 145 is disposed over the second dielectric layer 140. Preferred embodiments of the present invention use an oxide as the first and second dielectric layers, but other dielectric materials can be used as the first or second dielectric layer. It is used as a charge trapping layer, but other local trapping materials (such as nano P930193 8 1376017 crystal) can be used instead of or in combination with tantalum nitride. In order to form the CHEAC memory cell, the voltage is supplied to the ground potential (for example, % supply and pole region 115, with Vs=4V bias potential voltage supply) domain 110, and with Vg=5V bias potential voltage supply control Closed-pole ^ Use one-channel hot electrons on the AC side I% (ch-injection, side 135 is increased to a high threshold voltage (10) level, and data side (6) is held at - low threshold voltage (Vt). The steep electric field 15〇 region is generated between the gossip side 135 and the data side in the channel 120 between the infinite electrode and the source 11〇 region, thereby forming a CHE AC memory i00. One side channel hot electron (CHE) injection system The shape/auxiliary charge 155 is used in the Ac side 135 by generating a path 16 from the drain region 115 through the channel 120 and the first oxide layer ι25 to the AC side 135. = = providing an auxiliary charge 155 from 汲The pole 115 is connected to the charge trapping layer 13A for the conduction path of J 135. The auxiliary charge 155 is stored in the AC side, and the multiple lines are constantly maintained at a fixed high threshold voltage (vt) level. The other side of the trap is the data side 165, which is maintained at a low threshold voltage (Vt) and can be used for any threshold voltage level. The data is stored and the memory operation is performed. Since the auxiliary charge 155 is fixed at the high threshold voltage (Vt) level, there is a steep electric field 0 AC between the AC side 135 and the data side 165 of the memory cell 100. The steep electric field 150 is raised at Stylized efficiency and rate on the data side during memory operation. The memory operation includes stylization, erasing, and reading of data in the data side 165 of the memory unit 1. In addition, the auxiliary side charge 155 is fixed in the AC side 135. Existence, limiting the stylized current during hot metal (HE) stylization operations' thereby reducing power requirements and making programming more efficient. 93 93 193 9 1376017 Figures 2A and 2B are another preferred embodiment of the present invention FIG. 2A and FIG. 2B show a two-step method of forming an FN AC memory 200 unit using the same memory cell 100 structure as that shown in FIG. 1. To form a FN AC memory 200 unit, a bungee Both the ι15 and source 110 regions are supplied with a ground potential (eg, Vd=Vs=〇v), while the control gate 145 is biased with the potential Vg=-20V as shown in Figure 2A. Negative Fowler-Nordheim (- FN) the use of injection by means of the control gate A negative bias voltage is applied between 145 and the substrate 105 to uniformly increase the threshold voltage (Vt) of the charge trap layer 130 of the memory cell 1. This generates an FN charge 180' which occupies the entire charge of the FNAC memory cell 200. The sinking layer 130. The data side 165 is used to erase the FN charge 180 from the data side 165 by using a side band to the band thermal hole injection. Meanwhile, the FN charge 180 in the AC side 135 is maintained at the fixed level shown in FIG. 2b. High threshold voltage (vt) level. Before the BTBHH injection, a ground potential (vs = 0 V) is supplied to the source u 〇 region, and a Vd = 4 5 V bias potential voltage is supplied to the drain 115 region. The control gate 145 bias potential is changed to Vg = _8V as shown in Fig. 2B. The band-to-band thermoelectric hole injection system is used to erase the side 165 (eg, data side) of the two-side charge trapping layer 13 of the memory cell while maintaining the other side 135 (AC side). At a fixed high threshold voltage (vt) level. By using the BTBHH implant, the resulting via 160 is routed from the drain 115 region through the via 12 and the first oxide layer 125 to the data side 165 of the charge trap layer 130. The via allows a hole carrier charge 17〇 to be conducted to the tributary side 165' and erases the FN charge placed there by the FN implant P930193 1376017 M〇° This erase only clears the data side 165 and keeps the AC side 135 fixed at high Threshold voltage (vt) level. Since the auxiliary charge 155 is fixed at a high threshold voltage (Vt) level, the steep electric field 150 is generated between the AC side 135 and the data side 165 of the memory unit 200, as shown in Fig. 2B. Steep electric field boost. = Stylized efficiency and rate of data side 165 during memory operation. The remember-memory operation includes stylization, erasing, and reading of data stored in the data side 165 of the memory unit 100, 200, 300. The auxiliary charge 155 appearing at the high threshold voltage (Vt) level in the AC side 135 limits the stylized current during the hot electron (he) program operation. This reduces the stylized power requirements and makes the programmed FN AC memory more efficient. Another preferred embodiment of the invention uses a positive F〇wler-N〇rdheim (+FN) implant to form the FN Ac 5 recall unit 2〇〇 shown in Figure 2A. The use of positive Fowler-Nordheim (+FN) implants is by applying a positive bias voltage between control gate 145 and substrate 105. The +FN implant uniformly increases the threshold voltage (Vt) level of the charge trap layer 13 of the memory cell 200. This technique produces an FN charge of 180 which occupies the entire charge trap layer 13 of the FNAC memory unit 200. The above -BTBHH injection for _FN injection can also be used to erase the FN charge 180 of the material side 165 of the +FN AC memory cell 200. To form a +FN AC memory cell, a bias potential voltage is supplied to the drain 115 region, and the control gate 145 is changed to a different control voltage as shown in Fig. 2B. Band-to-band thermal hole (BTBHH) injection is used to erase one side of the memory cell side 165 (data side) while maintaining the other side 135 (AC side) at a high threshold voltage (vt) Level. The steep electric field 丨5〇 region P930193 11 1376017 produces the ... side 135 and the poor material (4) in the channel (10) between the electrode 115 and the source 110 region, thereby forming a FNac memory thin. The mixing of the (4) I preferred financial example and the 3B display use the same as the one shown in Fig. 1 to form a mixed AC memory cell. In order to form a hybrid AC memory cell, the bias potential voltage is supplied to the source u to obtain a supply-ground potential (eg, Vd, £ domain, and the 115-pole voltage level to the control dragon 145, as shown in FIG. And ^4—^=^ on the 135 uses the -side channel hot electrons (c^. By a high threshold voltage (four) level on the AC side, and ^HAC side 135 increases to the voltage (Vt). Side 165 is maintained in a low threshold source 110 region through channel 12 〇褙田座玍135, and on AC side 135; =^^ path (10) is provided for auxiliary 155 H into auxiliary charge 155. The AC side of the charge trapping layer 130 and the AC memory pass through a single hot electron (the conduction path of the CHE surnamed n. The channel is used in the domain, with a ground potential two domain, and the control gate 145 is changed. V 5 V) is supplied to the source (10) zone 3B. Refer to Figure 3B for the bias potential 'as shown in the injection system to erase the two-sided charge trapping hole. The hole is kept on the AC side 135 at a fixed = Then 165, at the same time, the region will generate the pole 115 and (4) n^(Vt) level. The steep electric field 150 and the source U0 region between the channels 12〇Ac P930193 12 1376017 • side 135 and data side Between 165, thereby forming a hybrid AC memory cell 3. The data side 165 of the charge trapping layer 130 is maintained at a low threshold voltage (vt) level and can have any threshold voltage and is used to store a Data charge. Since the AC side 135 fixes the auxiliary charge 155 at a high threshold voltage (Vt) level, a steep electric field of 15 〇 is generated between the AC side 135 and the data side 165 of the hybrid ac memory unit 3' As shown in Figure 3B, the steep electric field 150 boosts the stylized efficiency and rate of the data side 165 during memory operation. The memory operation includes a program of data charges stored in the material side I65 of the mixed AC memory 300 unit. Auxiliary, erase and read. The auxiliary charge 155 in the AC side U5 limits the stylized current during the hot metal (HE) stylization operation. Since this current is limited, this reduces the stylized power requirements and makes the program more Figure 4A is a schematic diagram of the AC memory cells 1, 200, 300 of Figures 1-3 'showing the hot electron (HE) injection for the programmed AC memory cells 1 , 200, 300. AC memory Units 1〇〇, 2〇〇, 300 are set to use one connection The potential (Vs = 0V) is supplied to the source 11 () region, a bias of vd = 4V _ the piezoelectric voltage is supplied to the drain 115 region, and is supplied to the control gate with a bias voltage of Vg = 5V. The pole 145. Before the stylized data side 165, when the *AC brother recall unit 100, 200, 300 is formed, the AC side 135 is set to a fixed-direction threshold voltage (Vt) level which is used as the current limiting area. The ac side 135 is set at a fixed high threshold voltage (vt) level. Then use HE left to program the AC memory units 1〇〇, 2〇〇, 3〇〇. A steep electric field 15 is generated between the data side 165 and the Ac side 135, which assists in programming the data side 165. One of the paths ι6 is generated from the source region through the steep electric field 150 in the channel 12 〇 P930193 13 Ϊ 376017 and the first dielectric layer 125 to the data side 165 of the charge trap layer 130. Thermal electron (HE) stylization causes a data charge 175 to pass from the source 110 region through the steep electric field 150 in the channel 120, through the first dielectric 125 (e.g., 'oxidized) layer, and stored in the AC memory unit 1〇〇. 20 years old,

The data side 165 of 300 is shown in Figure 4A. The steep electric field 150 increases the stylized efficiency and rate of the AC memory cells 1, 200, and 300. Since the AC side 135 is fixed at a high threshold voltage (vt) level, it produces a current limiting region in which the HE stylizes less current to program the data side 165 'and thus reduces the AC memory cells 100, 2〇〇 3, the power consumption. Since the auxiliary charge 155 limits the stylized current of the AC memory, there is no over-stylization problem associated with any particular embodiment and a tight stylized state distribution is provided in the AC memory unit. 4B is a schematic view of the AC memory cells 1 〇〇, 2 〇〇, 3 图 of FIGS. 1-3, which all have the same structure, and show the craving for erasing the AC memory cells 1 , 200 , 300 . The frequency band of side 165 is injected into the band thermowell. The setting of the AC memory unit 1〇〇, 2〇〇, 3〇〇 is supplied to the source 11〇 region using a ground potential (such as 'VS=〇V), and a Vd=4.5V=bit voltage is supplied to the pole. 115 area, and bias control material 145. - The short path of the general tangential channel 12〇 and the data side 165 gates of the layer 丨60 is in the area of the bungee 115 and the system is formed by the "through the charge" (3. === Into a bungee 115 area test Fu Dang ^ 16U 棺戍 conduction hole carrier charge 170 erase data side Ρ 930193 14 1376017 165 〇 Figure 5 Figure 1-3 ac memory unit loo, 200, 3 A schematic diagram of 〇〇, which is specific to all AC memory cells loo, 200, 300. The embodiment performs a read operation with Vs on the AC side 135. Ac memory list; the setting of the element 1 〇〇, 200, 300 A bias potential voltage of Vs 6.6V is supplied to the source 110 region, a ground potential (eg, Vd=〇v) is used for the drain 115 region, and a bias potential voltage of Vg=3V is used. Control gate 145. Once the suffix unit 100, 200, 300 has been set and properly biased, the data # is readily readable and stored on the data side 165 of the AC memory unit 1 〇〇, 2 〇〇, 300. The read operation does not affect the auxiliary charge 155 level that has been set to a fixed high threshold voltage (Vt) and remains in the AC side 135. The auxiliary in the AC side 135 The charge 155 reduces the read disturb of the AC memory cell or component 'which limits any read operation errors. The memory operation for the preferred embodiment requires less than a typical charge trap memory cell (eg, non-AC memory). Operating current, thus increasing the overall efficiency of the AC memory 100, 200, 300. In addition, the φ rate of the AC memory is also increased and the lower current is reduced for power consumption for operation. Furthermore, all AC § memories are implemented For example, the memory operation can be performed by a multi-level cell, wherein the data side of the charge trap layer can have various degrees representing the threshold voltage (Vt) level of the stored data. FIG. 6 shows a comparison of the general charge memory unit. The experimental data graph of the stylized rate and AC level of the AC memory 200 and the mixed AC memory 300 unit is 6. The graph 600 is graphically compared with Shot (which is defined as AVt sh〇t=〇)叩Display and compare each record P930193 15 1376017 Recall the different AC levels of the unit type. AVtCV) is used for the stylization of the memory unit and the data side Vt difference of the erased state. The general charge memory cell structure voltage bias system is provided with a gate overdrive voltage set to Vg_od = 〇v, a control gate voltage set to Vg = 2V, and a drain region voltage set to Vd = 4.75V. The gate overdrive (Vg_〇d) refers to the voltage difference between the gate voltage and the AC side threshold voltage. A typical charge memory unit does not have an AC side. Therefore, the AC level = 〇v indicates the threshold voltage (Vt) difference between the AC side and the data side of the memory unit. The data of the general charge memory unit is the bottom data curve 15 (labeled IX) displayed on the graph 600 by the solid line with the black circle ® in FIG.

The auxiliary charge 155' appearing in the AC side 135 of the charge trap layer 130. The FNAC memory 200 unit of Fig. 2 has an AC level equal to 2.4V. The gate overdrive voltage system Vg_od = 0V, the control gate 145 dust Vg = 4.4V and the drain 115 region voltage vd = 4.75V. The FN AC memory 200 unit is indicated by an intermediate data curve displayed on the graph 600 by a dotted line having a blank circle in Fig. 6 as 21 Χ). In comparison, due to the AC level of 2.4V, the positive and negative FN AC memory 200 units are 21 times faster than the general memory single unit, as shown in Figure 6. The hybrid AC memory 300 unit of Figure 3 due to the auxiliary charge 155 appearing in the AC side 135 of the charge trapping layer 130 has an AC level equal to 2.9V. The gate overdrive voltage system vg_od=〇v, the control gate 145 voltage Vg-4.9V and the drain 115 region voltage ν (^=4.75ν. The mixed AC memory 300 unit is represented by the dotted line with the black triangle in Fig. 6 Figure 6 shows the top data curve 5 (labeled 32Χ). In comparison, the mixed AC memory 300 unit is twice as fast as the general charge memory unit, as shown in Figure 6. P930193 16 1376017 Figure 7 is an experiment The data graph 700 compares the mixed AC memory 300 unit of FIG. 3 to the ι〇, 〇〇〇 stylized and erase cycle threshold voltage (Vt) for P/E (eg, stylized/erased) The mixed AC memory 3〇〇 unit has an initial AC level of 3V. The AC level is the difference between the AC side 135 of the memory unit 3 and the threshold voltage (Vt) of the data 杰 f 曰1. During the operation, the source no region is supplied with a ground potential (eg, Vs=〇v), the drain H5 region is supplied with Vd=4.75V, and the bias potential of −Vg=5v is supplied to the control gate 145. During the erase operation, the source UG region supplies the ground potential (eg, VS: 0V), the drain region is supplied with vdM5v, and the bias voltage is vg=-8V. Bit supply to control gate i45 is collected to achieve H) 5 〇 _ / E cycle remaining test to display a threshold voltage (window, which is the hybrid AC memory unit 3 of Figure 3 on the data side 165 high and low The threshold voltage V t state is between 2 0 and 25 5. The high threshold voltage state is the top data curve 2G and is displayed by the dotted line with a blank circle. The low threshold voltage state is the bottom data curve 25 and is shown in FIG. The solid line of the black circle on the graph 7〇〇 is displayed. As a result, the high threshold state 2〇 is maintained at the threshold of 4v, and the low state, 25 is maintained at a threshold voltage of about 19V. The window generally has the same size as the AC memory unit 300 throughout the 1M clear/E cycle. Figure 8 shows a tape 800 for the ready-to-use AC memory unit of Figure 3, as shown in Figure 7 1〇, 〇〇〇ρ/Ε后环,和;; room temperature (RT) threshold voltage (Vt) drift relative to stress time experimental data ^ its effect on the tributary side 165. Hybrid AC memory unit 3(8) Figure H), after the _P/E cycle is completed, there is a P930193 ground potential Vd=OV on the Qianji 115 area, and batch, _ seconds and Threshold voltage window: ^ = Vg ♦ stress on the time lines for the shell mixture Tu-based AC voltage memory state data 300 == blank entry portion 3 curved lines. And by and with 圄S ^. The low threshold voltage state is the bottom data curve 35 and is shown by the solid line indicating the voltage state of Figure 3 on the graph 80 on Figure 8. High and low 〇 0 0 AC memory 300 threshold voltage window for the graphic display is not on the side of the feed 3 〇 and low 35 limit power can make up „“ to / dish (RT) / do not move where to ask No change. This data shows that in the 1,000-second stress time, the σ AC memory 300 unit has a fairly good data retention throughout the operation. Figure 9 _ shows the pattern of the mixed AC memory unit of the pin _ 3, in the graph shown in Figure 7, after the _p/E cycle, compare the threshold voltage (vt) offset (eg, drift) Relative to the stress time of the control gate m, and its effect on the batting side 165. The control gate 145 is subjected to a stress time of 1 sec. with a bias potential of Vg = -5 V, and the data of the threshold window is observed. The low threshold voltage state 45 is the bottom data curve and is shown by the solid line with a black circle, which remains substantially constant throughout the stress time of the leap seconds. The high-limit current state 4 〇 system top material curve is displayed by a blank circle _ dotted line, which shows the loss in the data W65j^7〇〇mV after a stress time of 1 〇〇〇. This shows that if the stress is present for a long time, the mixed AC memory 3〇〇 unit is sensitive to the stress of the control gate 145. Figure 1 is a diagram showing the pattern of the mixed ACb memory cell 3〇〇 of Figure 3, in the case of the pattern 700 shown in Figure 7, and the erase cycle P930193 18 1376017 The voltage (10) offset is relative to the pole 145 with a bias on the billiard side 165 of Vg = 5V. The control asks the bias potential voltage supply of Vs=1, and the supply voltage of the partial potential of the source 110 region > is maintained at i,000 private for 2 hours. The low threshold voltage state 55 is based on the bottom data curve with black display and shows a stress time of up to 2 seconds = material side 165 1 increases · mV. The high threshold voltage state % is the top data curve displayed by the dotted line with a blank circle, and the stress in the second is ^

In general, it is maintained. As a result, the threshold voltage window is wider at the beginning of the stress time (e.g., larger full) and has a smaller AVt at the end of the stress time. Those skilled in the art will appreciate that the above-described embodiments may be practiced without departing from the broad inventive concepts. Therefore, it is understood that the invention is not limited to the specific details of the invention, and is intended to cover the modifications and the scope of the invention as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS [0009] The foregoing summary of the invention, as well as the detailed description For the purposes of illustrating the invention, various embodiments are shown in the drawings. It is to be understood that the invention is not limited to the precise arrangements and device arrangements depicted. In the drawings: FIG. 1 is a schematic diagram showing a structure and an exemplary method for forming an AC memory by side channel hot electron (CHE) implantation according to a preferred embodiment of the present invention; P930193 19 FIG. 2A shows A schematic diagram of an exemplary method for forming a Fowler_Nordheim (FN) AC memory by filling a germanium trap with FN charges in accordance with another preferred embodiment of the present invention. FIG. 2B shows the use of a sideband to band thermocouple ( BTBHH) is a schematic diagram of an exemplary method for erasing a portion of the trap for completing the formation of Fowler-Nordheim (FN) AC memory (as shown in Figure 2A); Figure 3A shows another preferred embodiment in accordance with the present invention. The embodiment uses a side channel hot electron (CHE) at the AC side of the AC memory, a schematic diagram of an exemplary method for forming a hybrid AC memory; Figure 3B shows the use of a sideband pair for the data side of Figure 3A. Schematic diagram of an exemplary method for erasing a mixed AC memory by a band thermoelectric hole (BTBHH); Figure 4A is a thermoelectric (HE) stylization using AC memory for the specific embodiment of Figures 1-3 to be at the data side Stylized exercise Schematic diagram of an exemplary method; FIG. 4B is a schematic diagram of an exemplary method of erasing a band thermoelectric hole (BTBHH) to erase operation at the data side using the frequency of the AC memory for the embodiment of FIGS. 1-3; Figure 5 is a schematic diagram showing an exemplary method for reading operations on the data side of an ac memory (Vd on the AC side) for the specific embodiment of Figures 1-3; ~ Figure 6 shows when compared to general charge memory When the structure is compared, a graph of experimental data comparing the stylized rate of the FN AC memory of the memory structure of FIG. 2 and the mixed memory of the memory structure of FIG. 3 is shown; P930193 20 1376017 FIG. 7 is a graph showing experimental data. It shows the voltage window of the high and low threshold voltage states at the data side during the 10,000 P/E cycle (eg, stylization/erase cycle) for the hybrid AC memory cell used in the memory structure of FIG. 3; A graph showing the experimental data of the room temperature (RT) voltage at the data side of the mixed AC memory of the 10K cycle of the memory structure of FIG. 3; FIG. 9 is a graph showing the experimental data, which is an example of FIG. Memory structure in Vg The threshold voltage shift after the Vg stress at -5 V; and Fig. 10 is a graph showing the experimental data of the threshold voltage shift after the read disturb test of the memory structure of Fig. 3. [Main component symbol description] 100 AC memory cell 105 P-type substrate 110 source region 115 > and polar region 120 channel 125 first dielectric layer 130 two-sided charge trap layer 135 AC side 140 second dielectric layer 145 control Gate 150 Steep electric field P930193 21 1376017 155 Auxiliary charge 160 Path 165 Data side 170 Hole carrier charge 175 Data charge 180 FN charge 200 FNAC memory unit 300 Mixed AC memory

P930193 22

Claims (1)

1376017 August 3, 101, Nuclear Replacement Page 2012; 8/3_la Application & Amendment 10, Patent Application Range: 1. An auxiliary charge memory (AC) formed in a charge trap memory element that performs a memory operation A method of a memory cell comprising: (1) a P-type substrate, (ii) a source region in a portion of the substrate, (iii) a drain region in a portion of the substrate, (iv a channel inserted between the source and drain regions and in a portion of the substrate, (v) - a first dielectric layer on the substrate and above the channel, (vi) - at a two-sided charge trapping layer on the first dielectric layer, (vii) # a second dielectric layer on the charge trapping layer, and (viii) a control gate on the second dielectric layer The method comprises: (a) supplying a ground potential to the drain region; (b) supplying a bias potential voltage to the source region; (c) supplying a control voltage to the control gate; and d) forming a charge in at least a portion of the two-sided charge trapping layer, wherein one side of the two-sided charge trapping layer (AC side) has a high threshold voltage (Vt) level, the charge is used for the auxiliary charge of the AC memory unit, and the other side (data side) is used for memory operation; The memory gymnastics as a erase operation, the step (a) further comprises supplying a ground potential to the source region, and the step (b) further comprises supplying a bias potential voltage to the drain region, and the step (d) Forming a path from the drain region through the channel for a hole carrier charge to be conducted from the drain region to the data side for injecting a band-to-band thermoelectric hole (BTBHH) for erasing the two sides The charge is set to 094143726 1013295655-0 23 1376017 _, on August 3, 101, according to the replacement page 2012/8/3_la, the application side of the correction trap. 2. The method of claim 1, wherein the memory gymnastics is a read operation, and: step (8) further comprises supplying a ground potential to the drain region, and step (b) further comprises supplying a bias potential And the voltage is applied to the source region, the method further comprising: (e) reading the data from the data side of the two-sided charge trapping layer. 3. The method of claim 2, wherein the memory operation of the two-sided charge trapping layer of the AC memory is a multi-level cell, and the data side can have a threshold voltage (Vt) level The various levels of charge levels. 4. The method of claim 1, wherein step (d) uses a one-way channel hot electron (CHE) on the AC side to increase to the high threshold voltage (Vt) level, the data side being at a low level A threshold voltage (Vt), wherein a steep electric field region is generated between the AC side and the data side in the channel between the drain region and the source region, thereby forming a CHE AC memory. 5. The method of claim 1, wherein: step (a) further comprises supplying a ground potential to the source region and the drain region * step (c) further comprising supplying a bias potential voltage to the control gate, Step (4) by uniformly applying a negative 094143726 1013295655-0 24 丄j/ου丄/August 03, 101 correction replacement page β = f between the control gate and the substrate in the charge trapping layer Forming one of the charge limits voltage (Vt), upper # to use - negative Fowler-Nordheim (-FN) injection + charge system is formed in the entire charge trap layer, plus by (b) by The drain region is removed by the ground potential and the eight-hearted bias voltage is repeated to the drain region, and the step (c) is repeated by changing the control voltage to a different control voltage, and Step (d) injecting a band-to-band thermoelectric hole (BTBHH) for erasing the data side of the two-sided charge trap while maintaining the ▲ side at a high threshold voltage (Vt) level, one of which The steep electric field region is generated between the AC side and the data side in the channel between the pole and the source region, thereby forming a "FN Ac memory." 6. The method of claim 1, wherein: step (a) further comprises supplying a ground potential to the source region and the gate region, Step (c) further comprising supplying a bias potential voltage to the control gate, and step (d) uniformly increasing the charge trap by applying a positive bias between the control gate and the substrate One of the charges, Ss, is formed in the layer, and is charged with a positive F〇wier_Nordheim (+FN), which is formed in the two-sided charge trap layer, and step (b) is performed by The drain region is removed from the ground potential and supplied with a bias potential voltage to the drain region, and step (c) is performed by changing the control voltage to a different control voltage 094143726 ·····. ♦ 1013295655 -0 25 1376017 On August 3, 101, Shuttle was replacing the 2012/8/3_la application and correction; and step (d) using a band-to-band thermoelectric hole (BTBHH) injection to erase the memory. The data side of the two side charge trapping layers of the cell while maintaining the AC side at a threshold voltage (vt) level, wherein a steep electric field region is in the channel between the drain and source regions The AC side and the data side are generated to form an FN ac body. 7. The method of claim 1, wherein: step (a) further comprises supplying a ground potential to the drain region, the step (b) further comprising supplying a bias potential voltage to the source region, β, step (d) is increased to a high threshold voltage by forming a charge in one side of the charge trap layer using a side channel hot electron (C Η E) injection. In the AC side of the trapping layer, step (a) is repeated by removing the ground potential and supplying a bias potential voltage to the drain region, and reading step (b) is performed by shifting from the source. Taking the bias potential and supplying a ground potential to the source for repetition, step (c) is repeated by changing the control voltage to a different control voltage, and step (4) is using a band-to-band thermoelectric hole (BTBHH) injection For erasing the data side of the two side charge trapping layers of the AC memory unit while maintaining the AC side at a fixed high threshold voltage (Vt) level, 094143726 26 1013295655-0 137-6017 101 years 08 On the 03th of the month, the shuttle is replacing the page 2012/8/3_la Shen Fu & A steep electric field region is created between the AC side and the data side in the channel between the gate and source regions to form a hybrid AC 'memory. 8. The method of claim 1, wherein the memory gymnastics acts as a stylized operation and: step (a) further comprises supplying a ground potential to the source region, and step (b) further comprises supplying a bias voltage a bit voltage is applied to the 汲-polar region, and step (d) conducts electrons from the source region to the data side by forming a path from the source region through the channel to use hot electron (HE) implantation. The data side of the two-sided charge trapping layer is programmed, wherein a steep electric field region is generated between the AC side and the data side in the channel between the drain and source regions. Step (d), by forming a path from the drain region through the channel, for a hole carrier charge to be conducted from the drain region to the data side for use in band-frequency-band thermal tunnel (BTBHH) injection The data side of the two side charge trap layers is erased. 9. The method of claim 1, wherein the charge trapping layer is a nitride charge trapping layer. 10. A method of forming an auxiliary charge memory (AC memory) cell in a charge trap memory element that performs a memory operation, the cell comprising (1) a P-type substrate, (H) - in one of the substrates The source region in the portion, (iii) a drain region in a portion of the substrate, (iv) - insert 1013295655-0 0941437.26 .· · · · ^ 27 1376017 101 August 101, according to the replacement page 2012 /8/3_laclaim & corrects the channel between the source and drain regions and in a portion of the substrate, (v) - the first dielectric layer on the substrate and above the channel, Vi) a two-sided charge trapping layer on the first dielectric layer, (vii) - a second dielectric layer on the charge trapping layer, and (viii) - on the second dielectric layer Controlling the gate, the method comprising: (a) supplying a ground potential to the source region; (b) supplying a bias potential voltage to the drain region; (c) supplying a control voltage to the control gate And (d) forming a charge in at least a portion of the two-sided charge trapping layer, wherein one side of the two-sided charge trapping layer AC side) has a high threshold voltage (Vt) level, the charge is used for the auxiliary charge of the AC memory unit, and the other side (data side) is used for memory operation; wherein when the memory Gymnastics as a wiping operation, step (a) further comprises supplying a ground potential to the drain region, step (b) further comprising supplying a bias potential voltage to the source region, and step (d) by forming a From the source region through the path of the channel, a hole carrier charge is conducted from the source region to the data side, and the band thermoelectric hole (Β Β Η Η Η) is injected to erase the two side charges The data side of the trapping layer. 11. The method of claim 10, wherein the memory gymnastics is a read operation, and: the step (8) further comprises supplying a ground potential to the source region, and the step (b) further comprises supplying a bias potential voltage To the 汲094143726 1013295655-0 28 1376017 101. August 03 revision replacement page 2012/8/3_la application & correction pole region, the method further comprises: (e) from the two side charge trapping layer The data side reads the data. 12. The method of claim 10, wherein the two-sided charge of the AC memory. The memory operation of the trap layer is a multi-level cell, and the data side may have a threshold voltage (Vt) The various levels of charge level. 13. The method of claim 10, wherein: step (a) further comprises supplying a ground potential to the source region and the non-polar region, - step (c) further comprising supplying a bias potential voltage to the control gate a step (d), by applying a negative bias between the control gate and the substrate to uniformly increase a threshold voltage (Vt) of the charge in the charge trap layer to use a negative Fowler - Nordheim (-FN) implant 'the charge is formed in the entire charge trap" step (b) by removing the ground potential from the source and supplying a bias voltage to the source Repeating in the region, step (c) is repeated by changing the control voltage to a different control voltage, and step (d) is using a band-to-band thermoelectric hole (BTBHH) implant to erase the two-sided charge trapping layer The data side maintains the AC side at a high threshold voltage (Vt) level, wherein a steep electric field region is generated between the AC side and the data side in the channel between the drain and source regions Thereby forming an FN AC memory. 0941437.26 plus 13295655-0 29 1376017 on August 3, 101, according to the replacement page 2012/8/3" 5* Shen Fu & Amendment 14. The method of claim 1 wherein: step (a) further includes supply one Grounding potential to the source region and the non-polar region, 'Step (C) further comprises supplying a bias potential voltage to the control gate, step (d) by applying a voltage between the control gate and the substrate Positive biasing to uniformly increase a threshold voltage (Vt) of the charge formed in the charge trap layer to use - Fowler-Nordheim (-FN) implant, the far charge is formed on the two side charge traps In the layer, Φ step (b) is repeated by removing the ground potential from the source and supplying a bias potential voltage to the source region, and step (c) is to change the control voltage into a different one. Controlling the voltage and repeating, and step (4) uses a band-to-band thermoelectric hole (BTBHH) to be applied to erase the data side of the two-sided charge trapping layer of the memory cell while maintaining the AC side at a high threshold voltage ( Vt) level, one of the steep electric % regions is at the & pole and source The region between Lai # A C side and the data side of the napkin generating channel, thereby forming a FNAC memory. 15. The method of claim 10, wherein: step (4) further comprises supplying a ground potential to the source region, and step (b) further comprises supplying a bias potential voltage to the drain region, step (4) by The electric charge is formed in one side of the charge trapping layer. 094143726 30 1013295655-0 1376017 101. 08. oh oh day correction replacement page 20J2/8/3_r Shen & correction charge to use one side channel hot electron (CHE) injection To increase to a high threshold voltage, the charge is formed in the AC side of the charge trapping layer, the step scale (a) is by removing the ground potential and supplying a bias potential voltage to the source Repeatedly, the region V is shifted from the non-polar region by the bias potential and supplies a ground potential 5 ▲ > · to the drain region and repeats, pressing and repeating The control voltage is changed to a different control to erase the SC band-to-band thermoelectric hole _HH) injected into the supply side while maintaining the data of the two-side charge trapping layer of the early element, one of the steep/曰忒/AC sides is fixed at a fixed The high threshold voltage (Vt) level, the AI% region in the bungee and The channel between the memory region. The side and the data _produced to form a hybrid AC such as the request item 1 操作, operation, method, wherein when the memory gymnastics is used as a stylized Ή-I domain step (a); 隹_ji., ^ 匕 contains supply one Ground potential to the polar region, and) progress includes supplying a bias potential voltage to the source path to supply d) by forming an electron from the drain region through the channel (CH from the drain The region is conducted to the data side to use the hot side, wherein E) is programmed to program the data of the two-sided charge trapping layer, and a steep electric field region is between the drain and source regions. 3726 101329565.5-0* 31 1376017 On August 3, 101, according to the replacement page 2012/8/3_la, the application of the AC side and the data side in the correction channel is generated. 094143726 1013295655-0 32