1375401 依據本發明之另—實施例，其係提供了-時脈/資料恢復電路 的時脈產生方法。該時脈產生方法包含有下列步驟：對接收自一 傳送介面的-輸人資料進行—除頻運算以產生—參考時咖號； .。以及利用該時脈/資料恢復電路依據錄人㈣以及該參考時脈訊 號的其中之一來產生一輸出時脈訊號。 【實施方式】 • 在說明書及後續的申請專利範圍當中使用了某些詞彙來指稱 特定的元件。賴領域中具有通常知識者應可理解，硬體製造商 • 可月b會用不同的名詞來稱呼同一個元件。本說明書及後續的申請 - 專她圍並科名翻差絲作為區分元件的方式，而是以元件 在功能上的差異來作為區分的準則。在通篇說明書及後續的請求 項當中所提及的「包含」係為一開放式的用語，故應解釋成「包 含但不限定於」。此外，「輕接」—詞在此係包含任何直接及間接 • 的電氣連接手段’因此，若文中描述U置墟於一第二裝 置’則代表該第-裝置可直接電氣連接於該第二裝置，或者透過 其他裝置或連接手段間接地電氣連接至該第二裝置。 請參考第2圖。第2圖所示係依據本發明一時脈產生置朋 的一實施例示意圖。時脈產生裝置200包含有一第一除頻器2〇2 以及一時脈/資料恢復電路204。第一除頻器2〇2具有一輪入端凡 耦接於一顯科(DisplayPort)206，以依據從該顯示埠接收到的一 輸入資料Ddata來產生-參考時脈訊號Fr£f。時脈/資料恢復電路2〇4 具有一貢料輸入端Ns耦接於顯示埠206以及一參考時脈輸入端 N2輕接於第-除頻器2〇2的一輸出端化，用來依據在資料輸入端 %處所接收_輸人f料Ddata以及在參考雜輸人端N2處所接 收到的參考時脈訊號Fref的其中之—來產生—輸出時脈訊號 Four。時脈/資料恢復電路204包含有一相位偵測器2〇42、一多工 器2044、一電荷泵電路2046、一低通濾波器2〇48、一壓控振盪器 2050、一相位/頻率偵測器2〇52、一鎖定偵測電路2〇54以及一第 二除頻器2056。請注意，時脈/資料恢復電路2〇4内元件與元件之 間的連接方式已揭示於第2圖中，熟悉此項技術者應可輕易瞭解 時脈/資料恢復電路204的運作，因此為了方便起見，在此省略了 對時脈/資料恢復電路204内細部元件的說明。此外，本發明的時 脈產生裝置200並不局限於利用和時脈/資料恢復電路204 一樣的 電路來實作，任何具有時脈/資料恢復特性的電路均為本發明的範 脅所在。 根據顯示痒206的規格可以得知，當輸入資料Ddata内的一實 際輸入資料還未被傳送至時脈/資料恢復電路204之前，一些具特 定形式的訊號係可以透過輸入資料Ddata被傳送到時脈/資料恢復電 路204中’亦即所謂的鍵結訓練過程(Link Training Process)，其中 一種特定形式的訊號就是上述所提及的時脈恢復(Cl〇ck Rec〇very， CR)形式訊號。該時脈恢復形式訊號係用來提供一參考時脈給一等 化電路(EqualizingCircuit)，其中該等化電路係耦接於時脈/資料恢 復電路204。請注意’熟悉此項技術者應可瞭解該等化電路與時脈 1375401 :· L〇〇P，PLL)來取代時脈/資料恢復電路2〇4亦可以達到本發明之目 的，因此，此亦落入本發明之範缚所在。 "月> 考第3圖。第3圖所示係依據本發明一時脈/資料恢復電 路的一時脈產生方法之一實施例流程圖。為了方便起見，該時脈 產生方法係以上述第2圖所揭示的時脈產生裝置2〇〇來搭配說 明。此外，倘若大體上可達到相同的結果，並不需要一定照第3 籲騎不之流程中的步驟順序來進行，且第3圖所示之步驟不一定 要連續進行’亦即其他步驟亦可插入其中。該時脈產生方法包含 有： 步驟302 :從顯示琿206處接收-輸入資料Ddata ; 步驟304 :當時脈/資料恢復電路2〇4處於該頻率鎖定的模式 時，對透過該輸入資料Ddata傳送的該時脈恢復形 式訊號進行除頻以產生參考時脈訊號1?11£1；; 步驟306:利用時脈/資料恢復電路2〇4的該第一迴路依據參考 ^ 時脈訊號Fref來產生輸出時脈訊號FOUT ; 步驟308:中止該第一迴路並啟動時脈/資料恢復電路2〇4的該 第二迴路以對輸入資料Ddata内實際的輸入資料進 行鎖相。 於步驟302中，本發明的該時脈產生方法係不局限於從顯示埠 2〇6接收輸入資料Ddata，亦即任何其他可以產生一連續高電位(亦 即1)和低電位(0)交錯形式的訊號的傳輸介面均落入本發明之範缚 • 所在。在步驟304中，當時脈產生裝置200處於該頻率鎖定的模 10 1375401 第3圖係依據本發明該時脈/資料恢復電路的一時脈產生方法之一 實施例流程圖。 【主要元件符號說明】 100、204 時脈/資料恢復電路 102'2042 相位偵測器 104、2044 多工器 106、2046 電荷泵電路 108 、 2048 低通遽波器 110、2050 壓控振盪器 112、2052 相位/頻率偵測器· 114、2054 鎖定偵測電路 116 除頻器 118 振盪器 200 時脈產生裝置 202 第一除頻器 206 顯示埠 2056 第二除頻器 121375401 In accordance with another embodiment of the present invention, a clock generation method for a clock/data recovery circuit is provided. The clock generation method comprises the steps of: performing a frequency division operation on the input data received from a transmission interface to generate a reference time coffee number; And using the clock/data recovery circuit to generate an output clock signal according to one of the recording (4) and the reference clock signal. [Embodiment] • Certain terms are used in the specification and subsequent claims to refer to specific elements. Those with ordinary knowledge in the field should understand that hardware manufacturers can use the same noun to refer to the same component. This manual and subsequent applications - specializes in her name as a means of distinguishing components, but as a criterion for distinguishing between functional differences of components. The term "including" as used throughout the specification and subsequent claims is an open term and should be interpreted as "including but not limited to". In addition, "light" - the term contains any direct and indirect electrical connection means 'so that if the description of U is in a second device', then the device may be electrically connected directly to the second The device is indirectly electrically connected to the second device through other devices or connection means. Please refer to Figure 2. Figure 2 is a schematic illustration of an embodiment of a clock generation in accordance with the present invention. The clock generating device 200 includes a first frequency divider 2〇2 and a clock/data recovery circuit 204. The first frequency divider 2〇2 has a wheeled terminal coupled to a DisplayPort 206 for generating a reference clock signal Fr£f based on an input data Ddata received from the display port. The clock/data recovery circuit 2〇4 has a tributary input terminal Ns coupled to the display port 206 and a reference clock input terminal N2 connected to the output of the first frequency divider 2〇2 for The output clock signal Four is generated at the data input terminal % and the reference clock signal Fref received at the reference terminal N2. The clock/data recovery circuit 204 includes a phase detector 2〇42, a multiplexer 2044, a charge pump circuit 2046, a low pass filter 2〇48, a voltage controlled oscillator 2050, and a phase/frequency detection. The detector 2〇52, a lock detecting circuit 2〇54 and a second frequency divider 2056. Please note that the connection between components and components in the clock/data recovery circuit 2〇4 has been disclosed in FIG. 2, and those skilled in the art should be able to easily understand the operation of the clock/data recovery circuit 204, so For the sake of convenience, the description of the detailed components in the clock/data recovery circuit 204 is omitted herein. Furthermore, the clock generating apparatus 200 of the present invention is not limited to being implemented by the same circuit as the clock/data recovery circuit 204, and any circuit having a clock/data recovery characteristic is a symptom of the present invention. According to the specification of the itching 206, it can be known that when an actual input data in the input data Ddata has not been transmitted to the clock/data recovery circuit 204, some specific types of signals can be transmitted through the input data Ddata. In the pulse/data recovery circuit 204, the so-called Link Training Process, a specific form of signal is the above-mentioned clock recovery (CR) form signal. The clock recovery form signal is used to provide a reference clock to an equalizing circuit (Equalizing Circuit), wherein the equalizing circuit is coupled to the clock/data recovery circuit 204. Please note that the person familiar with the technology should be able to understand the circuit and the clock 1755401: L〇〇P, PLL instead of the clock/data recovery circuit 2〇4, and thus the object of the present invention can be achieved. It also falls within the scope of the invention. "Month> Test Figure 3. Figure 3 is a flow chart showing an embodiment of a clock generation method for a clock/data recovery circuit in accordance with the present invention. For convenience, the clock generation method is described in conjunction with the clock generation device 2A disclosed in Fig. 2 above. In addition, if the same result can be achieved in general, it is not necessary to follow the sequence of steps in the third step, and the steps shown in Figure 3 do not have to be performed continuously. Insert it. The clock generation method includes: Step 302: Receive-input data Ddata from the display port 206; Step 304: When the clock/data recovery circuit 2〇4 is in the frequency lock mode, transmit the data through the input data Ddata The clock recovery form signal is divided to generate a reference clock signal 1?11£1; Step 306: The first loop using the clock/data recovery circuit 2〇4 generates an output according to the reference ^ clock signal Fref The clock signal FOUT; Step 308: Suspend the first loop and start the second loop of the clock/data recovery circuit 2〇4 to phase lock the actual input data in the input data Ddata. In step 302, the clock generation method of the present invention is not limited to receiving the input data Ddata from the display 〇2〇6, that is, any other may generate a continuous high potential (ie, 1) and a low potential (0) interleaving. The transmission interface of the form of the signal falls within the scope of the present invention. In step 304, the pulse generation device 200 is in the frequency locked mode. The first diagram is a flow chart of an embodiment of a clock generation method of the clock/data recovery circuit according to the present invention. [Main component symbol description] 100, 204 clock/data recovery circuit 102'2042 phase detector 104, 2044 multiplexer 106, 2046 charge pump circuit 108, 2048 low-pass chopper 110, 2050 voltage-controlled oscillator 112 2052 Phase/Frequency Detector · 114, 2054 Lock Detection Circuit 116 Frequency Demultiplexer 118 Oscillator 200 Clock Generation Device 202 First Frequency Divider 206 Display 埠 2056 Second Frequency Demultiplexer 12