TWI373954B - Bridge dc/dc power converting apparatus and bidirectional communication method thereof - Google Patents

Description

1373954 〇7(β)Α039 24682twf.doc/n A, the coil between the turns), the rectifier circuit 9〇 and the impedance modulation circuit ΐ5 are connected to the secondary coil of the transformer 100 (between the terminals C and D) Coil). With continued reference to ® 1, the transformer H 100 provides an isolation mechanism. When the forward data is allowed to be transmitted, the forward data will generate several controls~, and use the control signal s, ~s4 to control the bridge switch circuit 5G = phase modulation of the supply 4 electric ^, and then generate the first modulation The signal is in the first lap, and the voltage of the first modulation signal is VAB. The voltage VAB = (or polarity, ie positive voltage or negative) contains the forward data, and Cli 1GG will - The energy of the modulation signal is transmitted by the primary coil to produce a voltage VCD. The rectifier circuit rectifies the voltage V3 to a direct voltage to generate a supply of power to the secondary circuit, in which supply =2 is V. . The impedance of (4) (4) and the capacitance 65 (capacitance of the capacitor or the parasitic capacitance of the circuit) form a resonant circuit. When the reverse transmission wheel is reversed, the reverse data generates a control signal s5 to control the resistance == way 150 to change the impedance of the transformer 100, thereby modulating the resonant vibration signal to generate a second difficult signal. Among them, the second modulation: the voltage of 遽 is VCD, and the voltage VCD contains the information of the reverse data. The change signal is changed by the secondary coil of the transformer (10) and the primary coil. m Vab ° Lei Zheng's, / 'The two-way core-activated bridge switch that generates the first-signal signal, in addition to the full-bridge type architecture, can also be half Bridge switching circuit, push = 1 bridge _ architecture. The embodiment of Figure 1 uses a full bridge, and is fully illustrated and is not intended to limit the invention. The θ switch circuit 50 includes switch transistors 10, 20, 30 and 40, 11 1373954 07 (specific) A039 24682 twf.doc/n The switch transistors 10, 20, 30 and 40 respectively have parasitic diodes. When the forward data is to be transmitted, the control signals S! S4 generated according to the forward data can be used to control the on/off of the respective switching transistors 10, 20, 30 and 40 of the full bridge switching circuit 5A to supply the voltage V1N. The phase modulation is performed to generate a first modulation signal on the primary coil of the transformer. The voltage Vab of the first modulation signal is coupled to the secondary coil by the transformer 100 to generate an electric magic VCD, and the voltage VCD on the secondary coil is converted into a DC supply voltage 透过 through the rectifying circuit 90 to provide power to the secondary The circuit is used. At the same time, the information of the forward data contained in the phase of the first modulated signal is also transmitted from the primary coil of the transformer 100 to the secondary coil. When the forward data is “0”, the voltage vAB of the first modulation signal generated by the full bridge switching circuit 50 is a positive value; when the forward data is “,, the voltage Vab is a negative value. The information of the forward data can be obtained by detecting the phase ' of the voltage signal Vcd of the secondary coil of the transformer 1 . In addition, the rectifier circuit 90 of the embodiment of FIG. 1 includes the diodes 73, 75, 77, 79 and Capacitor 85. The rectifying circuit 90 converts the voltage VCD of the signal of the secondary winding of the transformer 1〇〇 into a DC voltage v〇 to provide power to the secondary circuit. However, the embodiment of the rectifier circuit 90 of FIG. 1 is only For convenience of description, it is not intended to limit the present invention. When the reverse data is to be transmitted, the resonance is generated by the inductance of the transformer 100 itself and the independent capacitor 65 parasitic or externally added to the circuit. During the resonance period, the impedance modulation circuit 150 The transformer impedance is changed according to the control signal S5 generated by the reverse data, thereby modulating the resonance signal on the resonance circuit to generate the second modulation signal. When the reverse data is to be transmitted, the switch of the full bridge switching circuit 50 is generated. The crystals 10~40 will all be cut off, and the inductance of the transformer @1〇〇12 1373954 07 (special) A039 24682twf.doc/n and the electric valley 65 constitute the resonance station (res〇nant). When the reverse data is 'switching electricity' The crystal 165 maintains an off state; when the reverse data is "1", the switching transistor 165 is turned on, so that the internal resistance of the secondary winding of the transformer ι and the switching transistor 165 are connected in series with the two diodes 173, 175. The impedance value of the transformer 100 is changed, and the energy of the first modulation signal (the voltage of which is vcd) on the secondary coil can be transmitted to the primary coil by the transformer 1 to generate the voltage vAB. The voltage VAB of the signal of the primary coil can be used to read the information of the reverse data. The apparatus 1000 provided by the above embodiment can have four modes Model, Mode2, Mode3 and Mode4 in one cycle. The mode Model is the forward data mode. Mode Mode2 is the demagnetization mode, mode Mode3 is the reverse data mode, and mode Mode4 is the periodic synchronization mode. Among them, the control signals S1 to S4 generated in each mode Model~Mode4 are as shown in the following table. Condition A: Forward data is “0” -—------- Mode Model Control signal Si~S4 value Si=l S2=0 s3=i s4=o Condition B: Forward data is “1” Mode Model Control signal Si~s4 value τ· Si=〇S2=l s3=〇s4=i Mode Mode2 Si=0 S2~0 SfO S4=0 Mode Mode2 Si=〇S2=〇S3=〇S4=〇 mode Mode3 Sj=0 S2~0 S3=0 S4=l Mode Mode3 Si=〇S2=〇83=1 S4=〇Mode Mode4 Sj^O S2=0 S;j=l Sfl Mode Mode4 Si=〇S2=〇S3 —I S4=l 13 1373954 〇7(Special) A039 24682twf.doc/n Eye Referring to FIG. 2' FIG. 2 is a circuit diagram of an embodiment of a primary communication control circuit for generating control signals Si to S4. The primary communication control circuit 2 〇〇 • is used to transmit the forward data RXi and the receive reverse data TX, to generate the above control signals S!~S4 and control the device 1 〇〇〇 which mode is in. Model~Mode4. The primary communication control circuit 200 includes a communication unit '210, a serial bus interface 220, a clock signal generator 230, a mode controller 240, a level decoder 250, and a phase modulation circuit 290. The communication unit 70 210 is coupled to the computer (Host), and the serial bus interface 220 is coupled to the communication unit 210, the level decoder 250, and the phase modulation circuit 29, and the level decoder 250 is coupled. Connected to the two ends A and B of the primary coil of the transformer 100, the mode controller 240 is coupled to the clock signal generator 23, the level decoding benefit 250 and the phase modulation circuit 290, and the phase modulation circuit 29〇 It is coupled to the bridge switch circuit 50. The clock signal generator 23 is used to generate the clock signal ck]. The communication unit 210 is configured to transmit the reverse data to the computer and receive the forward data RXi from the computer. The serial bus interface 22 is used to receive the forward data RXi and the reverse data τχ from the communication unit 210 to the communication unit 210. In the mode M 〇 de3, the level decoder 25 is used to say that the voltage v is changed by ' to thereby solve the inverse data ΤΧι. The mode control .. system""240 generates mode signals Mii, Mi2, Mi3 and ' according to the % pulse signal CKi to control the length of each mode M〇del~M〇de4. The mode signal ‘for the M14 respectively represents the mode Mode 2、de2, Mode3 and Mode4, for example, when in the mode M〇del, Μιι=1, =12-〇 ’ M13=〇 ’ Ml4=0. In the mode M〇del, the phase modulation circuit 290 generates the control signal Si-Sc according to the forward data and the mode signals Mu~Mi4 (please refer to the table of 1373954 〇7 (special) A039 24682twf.doc/n). Referring to Figure 3, Figure 3 is a circuit diagram of an embodiment of a secondary communication control circuit. The primary communication control circuit 3 is configured to transmit the reverse data to receive the forward data TX2, and to control the synchronization between the primary communication control circuit 2 and the secondary communication control circuit 300. The secondary communication control circuit 3 includes a communication unit 310, a serial bus interface 32A, a voltage regulator 34A, a phase decoder 350, an impedance modulation control circuit 39A, and a synchronization controller.

The communication unit 310 is coupled to the serial bus interface 32, and the serial bus interface 320 is coupled to the phase decoder 35 and the impedance modulation control circuit 390'. The synchronization controller 4 is coupled to the phase decoder. 35〇 and impedance modulation control circuit 390.通讯 The communication unit 310 receives the reverse data from the 1/0 end and will

^^_1^2 Red __ 排 面 32 ()' tandem bus 〇 \ 〇 used to receive and transmit reverse data RX2 and forward data τ χ 2 . The stable 340 provides a stable supply voltage to the secondary communication control circuit. The phase decoder 350 receives the voltage ν(3) of the secondary winding of the transformer 1〇〇, the f-mode, and the phase decoder 35〇 is received by the primary communication control circuit 2〇〇 by detecting the voltage v^D. The news of the forward information. When the voltage Vcd detected by the phase decoder 350 is positive = then the forward data TX2 is judged as T; otherwise, if the voltage ^ is 3 3%, i = Λ 2 is "1". Thereafter, phase decoder 320. The resistance (4)% is transmitted to the serial bus interface w, and the 6th circuit is used to generate the control signal S5 for controlling the impedance modulation circuit to turn off the power body 165, and according to the inverse of the intended transmission 1373954 07(ί) Α039 24682twf.doc/n Change the impedance value of transformer 100 to the data to complete the signal transmission of the reverse data. The synchronous controller 400 is responsible for generating the mode signals M21 to M24 to enable the primary and secondary communication control circuits 200 and the secondary communication control circuit 300 to operate in synchronization. The mode signals M21 to M24 respectively represent the current mode Model~Mode4, for example, when in the mode Mode3, M21=0, M22=0, M23=l, M24=0.

Referring to FIG. 1 and FIG. 2, when the 1000 device is in the mode Model, the communication unit 210 retrieves the forward data of the computer and sends the forward data RX to the serial bus interface 220. The serial bus interface 220 will allow the forward data RXi to pass, and the forward data will be sent to the phase modulator circuit 290. The phase modulator circuit 29 generates the control signals si~S4 according to the above table. Forward data RXi is,, 〇", then control signal

'Sfi, SfO' causes the voltage Vab to be a positive voltage. On the other hand, if the forward lean material ^ is "1", the control signal SfO, S2 = 1, S3 = 0, S4 = Bu makes the voltage VAB a negative voltage. The voltage Vab is the energy of the voltage VAB by the transformer i The primary coil is transmitted to the secondary coil to generate a voltage VCD. Referring to FIG. 3, the phase decoder 35 detects the forward data Τχ2 by detecting the phase of the voltage vcD, and when the voltage is a negative voltage, it indicates a smooth The data TX2 is "1"; conversely, if the voltage vcD is a positive voltage, it means that the Shundian shell material TX2 is. The phase calculus horse 3s 〇 sends the forward data τ χ 2 to the = bus bar interface 32 〇, string The bus bar interface 32 () sends the solution = to the bus τ χ 2 to the communication unit 31 〇, and the communication unit 31 〇 re-enters the decoded forward data TXs to the 17 〇 end. 1, when the device 1000 is in mode Mode2, 16 1373954 07 (special) A039 24682twf.doc/n 4, the dust collector loo this element to ground magnetically, to avoid the transformer I. The phenomenon of magnetic saturation. Because the transformer Then it can completely re-magnetize y, so in the next, the mode Mode3 makes the reverse data 1〇 (the transmission of 2 will save more power. After the transformer 1〇〇 is demagnetized, the inductance of the transformer 1 itself and the energy of the capacitor generate a resonance signal. Therefore, in the mode M〇de3, the impedance of the transformer 100 can be changed by the impedance modulation circuit 150. The Q factor of the ugly vibration is changed, and then the amplitude of the resonance voltage is changed. The amplitude of the amplitude hides the information of the reverse data RX2. Since the transformer lion inductance and the capacitance 65 are co-existing, the volume is the silk recovery. The energy used for reuse, and _£, the impedance modulation circuit 15 has a low rate when the reverse data RX2 is transmitted. Therefore, the device 1〇00 of the present invention is a highly energy-saving transmission device. Referring to FIG. 1 and FIG. 2, In the mode M〇de2, the control signal generated by the phase modulator circuit switch 290 is Si=〇, s corpse, heart=〇, heart=〇, so the 'switching transistors 10~40 are all turned off' transformer 1〇〇 The magnetic 4 can be demagnetized via the parasitic diode path of the transistors 10 to 40, and the capacitor 65 can thereby generate a square vibration. The tenth "°σ" is changed by the electric vibration. ^Generation, vibration, voltage Vab Will be followed by a total of 'please refer to Figure 1 and Figure 3 'When the device 1〇〇〇 enters the unit Μ"" will take the inverse of the 1/end 4 and send it to the serial flow interface 320, and the serial bus 2 will send the reverse data 2 to the impedance modulation The control circuit 39. The impedance read circuit 39G is based on the control signal of the reverse f-modulation circuit 15G. When the reverse data rx2 is & 17 1373954 07 (special) A039 24682twf.d〇c/n control signal S5= 0; conversely, when the reverse data is T, the control signal s5 -: ι. Therefore, the 'impedance modulation circuit 150 can control the on/off of the transistor 165 according to the reverse data team to change the impedance of the transformer, and generate the second modulation signal. The voltage is Vw. Please refer to FIG. 2 The signal is transmitted to the primary coil via the transformer, and the voltage Vab' level decoder 250 detects the change of the voltage ν, and thereby solves the reverse data TX1. Then, the serial bus interface interface 21 is connected to the reverse data TXi solved by the quasi-decomposer 250, and the reverse data TX" is sent to the communication unit 210' and is solved by the communication unit 21〇. The reverse lean 13⁄4 is sent to the f brain, so that the user on the computer can obtain the information of the reverse data. + Qing continued with reference to Fig. 1 and Fig. 2. In the mode M〇de3, if the forward data previously input to the mode Model is ,,,,,, when the transformer 1 is turned on, the sense and capacitance 65 begin to resonate, and the transformer 1 The voltage Vab of 〇〇 is a negative voltage _. The phase modulation circuit 290 outputs a control signal Si=〇, S2=〇, S3j, 'S4==1' to thereby turn on the switching transistor 40 to ground the terminal A, and measure the signal of the end point B. It is possible to judge whether the impedance of ', has changed according to the change of voltage v. The level decoder 250 measures the terminal S = -., 疋 = lower than the reference voltage VRef, and if so, the level decoder 25 determines that the j-direction data TXi is "1" ', and vice versa, the reverse data ΤΧ is "〇, If the forward data RXl of the mode Model input is "Γ,", when the inductance of the transformer 1〇〇 and the capacitor 65 start to resonate, the voltage vAB of the transformer 100 is a positive voltage, and the phase modulation circuit 290 The output control signal Si=〇, S2=〇, Sfl 'S^o' turns on the switching transistor 30 to ground the terminal B. At this time, the signal of 18 07 pass) Α 039 24682twf.doc/n can judge whether the voltage change (4) is higher than the test voltage according to the change of voltage I, ?? heart 25 (^ 端点 八 right 的 REF right 疋, Then, the level decoder 250 determines the reverse lean TW; otherwise, the reverse data TXi is "Γ,. Wide: = 5. Will the voltage VAB be large" 2 = the absolute value of B is greater than the reference voltage, then the level solution The horse called 250 reversed data τχ! For, 〇,,; vice versa, if the electricity house V solution

The absolute value of the reference is less than the reference voltage vREF, and the quasi-solution 2 AB is "!" to the data TX1. The group decoding pirates 250 solved the inverse "month"', Figure 2 and Figure 3 'When the device 1〇〇〇 will advance the coil will continue to make the change (four) 100 from the electric castle AB to zero 'wait mode' mode4 knot Take two vP new synchronous controller _ detect _ VcD change, to find the starting point of ===, and then let the primary communication control power (four) two-person, and the control circuit 3 can work synchronously Referring to FIG. 4, FIG. 4 is a leveling decoder 25A of the level decoder 25A, including two comparators, sources 255 and _, wherein the reference voltage is connected to the 260 The positive input terminal is connected with the comparator 27 milk handle = off the transistor such as the pole, the comparator and the 278 ^ capacitor ^ electric 曰 f 283 of the pole and the capacitor 285, a way to limit the invention, using This embodiment is only for the convenience of 19 1373954 〇7 (special) A039 24682twf.doc/n. The negative input of the comparator 260 and the positive input of the comparator 270 respectively receive the end of the transformer 100 into 3 The voltage is compared to a reference voltage Vref. Current source 280 charges the capacitor 285. Or gate 272 is based on comparator 260. The output of 270 produces an 'on/off signal' that controls transistor 283. When transistor 283 is turned on, current source 280 discharges capacitor 285. Gate 278 is coupled to capacitor 285 and coupled to mode controller 240. Mode signal Mi3, when the capacitor 285 ^ voltage signal rises to logic "", and the Μη signal is also logic, ¥, represents the period of mode Mode3, the primary communication control circuit · the received reverse data value TXl is "〗 The inverted data obtained by the level decoder 25 is "1", and is output by the gate decoder 278 of the level decoder 250; otherwise, the output signal of the gate 278 is ,, 〇,,. Please refer to FIG. 5. FIG. 5 is a flow chart showing the operation of the phase modulation circuit 29A. At step S292, the phase modulation circuit 290 reads the forward data and judges its value. When it is judged that the forward data RXi is ,, 〇,, the process proceeds to step 1 S293; otherwise, the process proceeds to step S294. In step S293, the phase modulation circuit 29 generates control signals S1 to S4 according to the mode signals Mu~Mi4 and the forward data (see the table of the foregoing table), thereby controlling the respective powers of the bridge switching circuit 50. The on/off of the crystal 1〇~4〇. In step 4, the phase modulation circuit 290 generates a control signal Si~\ according to the mode signal !!!~ with the forward data RX! (see the condition B of the above table), and the control bridge switch circuit 5 The on/off 曰 of the crystal i 〇~4〇. The length of each mode Model~Mode4 is determined by the mode signal generated by the mode controller 24〇20 1373954 〇7(special) A039 24682twf.doc/n]Vru~Μ4. After the end of step S293 or S294, the operation of the phase modulation circuit 29 is completed. Referring to Fig. 6', Fig. 6 is a circuit diagram of an embodiment of a phase desorption. This phase decoding II 35 includes a comparator 36, a reference voltage source 355 and a AND gate 368. The negative input of the comparator 360 is connected to the reference voltage source 355' and the gate 368 is switched to the output of the comparator 36(). However, the ® 6 is only one embodiment of the phase decoder 35, and is not intended to limit the invention. The positive input of the comparator 360 is connected to the terminal d of the transformer 1〇〇, with the voltage of the terminal D and the reference voltage Vr. And the gate 3 邡 pair comparator 360 output signal and mode signal Μ〗! Logical operations. ^, + When the mode signal is 1, 1, it represents the current mode M〇del. When the mode is prepared, the comparator compares whether the voltage of the terminal 〇 is greater than the reference voltage VR^. If the voltage of the terminal D is greater than the reference voltage %, the secondary communication control circuit 300 receives the forward data Τχ 2 as “丨”. The reverse data obtained by the phase decoding ϋ 350 decoding is “Γ, and is output by the phase decoder 350 and the gate 368; otherwise, the gate output signal is,, 0,,.

Next, referring again to FIG. 3, the synchronization controller 400 includes a periodic detection side σ. 450. Synchronous control signal generator and timing reduction circuit 55〇. The period detector 450 detects the change of the voltage Vcd. When the voltage Vcd changes from the low level to the high level, the pulse signal PLS is generated to indicate that the starting point of the new cycle is detected. The synchronous control signal generator 500 generates a charging control signal CHG and a sampling control signal SMP 21 1373954 〇7($)A039 24682 twf.doc/n signal by using the positive and negative edges of the pulse signal PLS, thereby controlling the timing reduction circuit 550 to operate. The timing reduction circuit 5s generates a ramp signal during the cycle, and uses a resistor divider and a relationship between the capacitor charging time and the battery to generate a mode signal that enables the secondary communication control circuit 3 to synchronize with the primary communication control circuit. M2i~m24. Referring to Figure 7, Figure 7 is a circuit diagram of an embodiment of a cycler 450. The period product detector 450 includes a reference voltage source 355, a comparator 360, 460, an inverse OR gate 462, and a pulse generator 47A. The pulse generator includes a reverse gate 484, a current source 490, a switching transistor 493, a capacitor still 5, a hysteresis gate 486 and a gate. Wherein, the reference voltage source milk is at the negative input end of the comparators 360 and 460, the inverse gate 462 is coupled to the output terminals of the comparators 36 and 460, the reverse gate 484 is coupled to the gate 4 and the reverse or gate The input terminal, the current source 490 and the drain of the switching transistor 493 are coupled to the capacitor 495, the gate of the switching transistor 493 is coupled to the output of the inverse or gate 462, and the source of the switching transistor 493 is coupled to the capacitor 495. The hysteresis switch 486 is coupled to the drain of the switch transistor 493 and the gate 488. However, the above-mentioned hysteresis switch 486 can also be a general reverse gate, and the hysteresis reverse gate 486 is only used to make the output waveform more stable. 7 is only one embodiment of the period detector 45A, and is not intended to limit the present invention. Comparators 360, 460 compare the voltages of terminals D and C with the magnitude of reference voltage VR, respectively. The inverse OR gate 462 controls the turn-on and turn-off of the switching transistor 493 in the pulse generator 470 based on the comparison of the comparators 36A and 46A. Current source 490 is used to charge capacitor 495, and capacitor 495 is discharged when switching transistor 493 is turned "on". When the period detector 450 " (measured to the voltage of the known points C and D' is simultaneously lower than the reference voltage (mode 22 1373954 〇 7 (^) A039 24682twf.d〇c / n

Mode4) When the voltage at one of the endpoints c or D is higher than the reference voltage Vr (mode Model), the pulse signal PLS is output and the 481 is output. Referring to Fig. 8', Fig. 8 is a circuit diagram of a synchronous control signal generator. The synchronous control signal generator 5A includes current sources 510, 530, hysteresis gates 506, 526, and gates 5, 8, 528, switching transistors 513, 533, capacitors 515, 535, and a gate 504. The output terminal of the reverse gate 5〇4 is coupled to the gate of the switching transistor 513 and the gate 528. The current source 510 is coupled to the drain of the capacitor 515 and the switching transistor 513, and the current source 530 is coupled to the capacitor 535. The hysteresis switch 506 is coupled to the capacitor 515 and the gate 508. The hysteresis gate 526 is coupled to the capacitor 535 and the gate 528. However, the above-described hysteresis gates 506 and 526 can also be general reverse gates. The hysteresis gates 506 and 526 are used only to make the output waveform more stable. 8 is only one embodiment of the synchronous control signal generator 5' and is not intended to limit the present invention. The reverse gate 504 receives the pulse signal PLS from the period detector 450, and the signal at the output thereof controls the transistor 513 to be turned on/off. The current source 510 is used to charge the capacitor 515. When the switching transistor 513 is turned on, the capacitor 515 can be discharged by the switching transistor 513. When the synchronous control signal generator 500 detects the positive edge of the pulsed PLS signal, the AND gate 508 generates the sampling control signal SMP. The output signal of the reverse gate 504 is used to connect the turn-on/turn-off of the control switch transistor 533. The current source 530 is used to charge the capacitor 535. When the transistor 533 is turned on, the capacitor 535 can be de-energized by the switching transistor 533. When the synchronous control signal generator 500 detects the pulse 23 1373954 07 (special) A039 24682twfdoc/n, the gate will generate the charging control signal CHG. Referring to FIG. 9', FIG. 9 is an implementation of the timing reduction circuit 55A. The timing reduction circuit 550 includes a time integrator, a sample maintenance circuit 7〇0, and a mode distributor_. The time integrator 600 includes a switching transistor (1), a capacitor 615, and a current source 610. Time integrator • _ less than 雑 sustain circuit 7GG and mode points g & | | Qing, sampling dimension ^ ^ Lu is lightly connected to the mode splitter 8 〇〇. The current source 61 is connected to the capacitor 615 and the switching transistor 613, and the capacitor 615 is connected to the switching transistor 613. The sample hold circuit 700 includes a buffer 73 〇, a switch 7 brother, and a valley 715. The controlled switch 753 is coupled to the output of the capacitor 715 and the buffer. The mode distributor 800 includes a buffer 81 〇, a resistor 8 〇 8 8 〇 6, 804, a 匕 comparator 840, 83 〇, 82 〇, a reverse gate m, a helium, a (10) and a gate 898, 888. The resistor 808 is coupled to the output of the buffer 81A and the resistor 806. The resistor 806 is coupled to the resistor 804. The resistor 804 is coupled to the resistor 802. The negative input of the comparator 84 is coupled to the resistor 8〇8. 806, the negative input end of the comparator 830 is coupled to the resistors 8〇6 and 8〇4, and the negative input end of the comparator 820 is coupled to the resistors 8〇4 and 8〇2. The reverse gate 874 is coupled to the output terminal of the comparator 840. The reverse gate 864 is coupled to the output terminal of the comparator 83, the reverse gate 854 is connected to the output terminal of the comparator 820, and the gate 898 is connected to the output terminal. The output of the comparator 840 and the reverse gate 864, and the gate 888 are coupled to the output of the comparator 830 and the reverse gate 854. However, Figure 9 is only one embodiment of the timing reduction circuit 550 and is not intended to limit the invention. The time integrator 600 controls the current source 610 to charge the capacitor 615 according to the charging control signal CHG, so that the capacitor 615 can obtain a relative voltage vei accumulated in a period of 24 1373954 〇7 (specific) A039 24682twf.doc/n. The sample-and-hold circuit is equipped with the highest voltage value of the voltage and the capacitance is 7!5. The nuclear distribution $8GG is based on Ohm's law (V=IR) resistance proportional to voltage, and Coulomb's law (Q:=AVc*c=Ic*At), which will be proportional to each mode Model~Mode4 The required time is converted into a ratio of resistances to generate a mode signal '~4, which is synchronized with each working mode Model~M〇de4 of the primary communication control circuit 2, thereby synchronizing the signals

M2!~M24 enable the primary communication control circuit 2 to be synchronized with the secondary communication control circuit 300.

When the charge control signal CHG is "1", the switching transistor 613 is turned on, and the capacitor 615 is discharged by the turned-on switching transistor 613, thereby resetting the integrating circuit 600. When the charging control signal CHG is ",", the switching transistor 613 will be turned off, the current source 61 充电 charges the capacitor 615, and the capacitor 615 starts to accumulate a relative voltage within a period of time. [This relative voltage VC1 is in The signal waveform in the period is a ramp signal. The value of the ramp signal generated by the current source 610 charging the capacitor 615 at a time At is Vcl=(I6*At)/C, where 16 is provided by the current source 61〇. The power supply value, C! is the capacitance value of the capacitor 615, so Vci is proportional to the relative charging time At. The buffer 730 causes the voltage of the capacitor 615 to be unaffected by the conduction of the controlled switch 753. When the sampling signal SMP is "1" When the controlled switch 753 turns on the voltage before the capacitor 615 is reset, the voltage of the capacitor 715 is close to the highest voltage of the capacitor 615, that is, Vc is MAX(Vc)). At this time, the voltage of the capacitor 71s is VcfCUU/Ci' Ts is the length of the cycle time equivalent to the operation of the primary communication control circuit 25 1373954 07 (special) A039 24682twf.doc/n 200, that is, the cumulative time length of the mode M〇del~M〇de4. The buffer 810 makes the resistor 808 Terminal voltage %, etc. In the mouth, and the voltage Vo is reduced by the resistors 802, 8〇4, 806 and 8〇8. The ratio of the resistors 802, 804, 806 and 808 is designed to be equivalent to the working time of each mode Model~Mode4 Length, ie R8〇2: R8〇4: R8〇6: R8〇8 = τ]: τ2: τ3: τ4 ' where 'r802, Rs〇4, R8〇6, — respectively, resistances 802, 804, 806 With the resistance value of 808, τ, T2, T3, T are the working time lengths of mode Model~Mode4 respectively. Since the series resistance value is proportional to the voltage difference between the two ends of the resistance' and the voltage difference on the capacitor 615 is proportional to the current Ie to the capacitance The charging time of 615. Therefore, the working time length of each mode M〇del~Mode4 will be proportional to the voltage difference between the resistors 8〇2, 804, 806 and 808, ie T]: T2 : T3: T4 = Vw : (Vx - Vw) : CVY- νχ): (VZ-VY)' where Vw, VX, VY, VZ represent the terminal voltages of the terminals W, X, Y, Z, respectively. The ends of the resistors 802, 804, 806, 808 The endpoint voltages Vw, VX, VY, VZ of the points W, X, Y, and Z are compared with the voltage VC1 of the capacitor 615 by the comparators 820, 830, and 840, respectively. The comparator 820 outputs the generation mode Model. The mode signal M21, when in the mode of the mode Model, the mode signal m21 is "1", and vice versa is "〇". When in the mode of mode Mode2, the mode signal y [22 is, T, and vice versa "0" . When in the mode of mode Mode3, the mode signal M23 is 'Τ' and vice versa. When in the mode of mode Mode4, the mode signal Μ24 is "1", and vice versa is "0". The mode signals Μ21 to Μ24 control the timing of the secondary communication control circuit 300 so that the circuit of the secondary communication control circuit 300 can be synchronized to the primary communication control circuit 200 by 26 1373954 〇7 (special) A039 24682 twf.doc/n. Before the device provided by the present invention starts bidirectional communication, the primary communication control circuit 200 can transmit a plurality of cycles of "〇" or "丨" synchronous forward data as the primary communication control circuit and the secondary. The communication control circuit 300 performs the initial setting of the synchronous communication (111 out & 1), so that the period detector 450 can capture the correct new cycle start point. After the communication transmission continues for a while, the initial setting time of the synchronous communication between the primary communication control circuit 2 and the secondary communication control circuit 300 can also be increased to ensure the communication quality. Please refer to FIG. 10. FIG. 10 is a waveform diagram of each input, output= and internal signal of the synchronous controller 4. The pulse signal PLS, which can determine the start point of the cycle, is generated by detecting a change in the voltage VCD of the transformer 1〇〇. The sampling control signal SMp is generated by using the pulse signal PLS positive edge; the charging control signal CHG is generated by the negative edge of the PLS signal. The ramp signal voltage vcl generated by the capacitor 615 is compared with the voltages Vw, Vx, Vy to generate analog signals Μ21~Μ24. Please refer to Fig. 11, which is a control flow chart of the impedance modulation control circuit 39. At step S392, the impedance modulation circuit 390 reads the reverse data RX2 and judges its value. When the reverse data RX2 is ,, 〇,, the process proceeds to step S393; otherwise, the process proceeds to step S394. At step S393, the impedance modulation control circuit 390 generates the Ss signal to turn off the switching transistor 165 of the impedance modulation circuit 15A. Therefore, the impedance modulation circuit 15 does not modulate the impedance of the transformer 100. At this time, the level decoding β 250 of the primary communication control circuit 2 detects the resonance signal voltage of the terminals a and B, and if the voltage Va 27 ^73954 〇7 (special) A039 24682twf.d〇C/n is detected. Or vB is less than the reference voltage Vref, and the reverse data τι is interpreted as, ι". ^ At step S394, the impedance modulation control circuit causes the switching transistor 165 L and the impedance modulation circuit 150 to operate, thereby modulating the transformer When the impedance 1 switch transistor 165 is turned on, the impedance of the transformer & is changed. The level decoder 250 in the primary communication control circuit 2 detects the resonance signal voltage of the Baye Ih point A and B. When the measured voltage is greater than the reference voltage, the reverse data is judged as “〇.” After the step Μ% or S394 ends, the impedance modulation circuit 15 performs the work in one cycle. Please refer to FIG. 12 and FIG. It is a signal wave opening when the device 1000 performs two-way communication. The primary communication control circuit 2 controls the working timing of the internal circuit according to the clock signal. When the forward data RXi is read as, 〇,,, then the phase adjustment Variable circuit according to condition A (like the aforementioned table The control signal SrS4 is generated, and the bridge switch circuit 15 is controlled to generate a first modulation signal. The voltage of the first modulation signal is Vab, and the voltage VAB is transmitted from the primary coil to the secondary via the transformer 100. The level coil generates a voltage VCD. In the mode of Model, &, the heart signal is,, 丨,, (high potential), S2 two signal is low) 'so that the voltage VAB on the primary coil of the transformer 1 is positive Value, at this time, the voltage on the secondary coil of the transformer is also positive, and the secondary communication circuit 3 determines that the forward data TX2 is transmitted to the 1/0 terminal. In the mode, the waste device 100 is demagnetized to Avoid the phenomenon of magnetic saturation. At this time, 'control signals S!~S4 are all, 〇”. In the mode Mode3, the control signal S4 is 1" 'control signal Si, heart, heart signal is, 〇", and when the reverse resource 28 1373954 07 (special) A039 24682twf.doc/n material RX2 is judged as "0" ", the signal S5 will be made "〇", and the impedance modulation circuit 150 will not operate. When the reverse data RX2 is interpreted as "1", the signal heart is "1" and the impedance modulation circuit 150 is activated to change the resonance signal. At this time, the measurement voltage VAB at the primary coil end of the transformer 1〇〇 is lower than the reference voltage • VREF, and if it is 'the primary communication circuit 200 will judge the value of the reverse data TXi to be '1'' (high potential) 'Transfer the reverse data TX1 to the computer. In the mode Mode4, the synchronous controller 400 will synchronize the primary communication control circuit 2 and the secondary communication control circuit 300, and the control signals S3, S4 are ' '1', control signal s!, S2 is ''0'. March refers to Figure 13 'Figure 13 is another signal waveform when the device 1 〇〇〇 two-way communication. When the forward data is "丨,, When the phase modulation circuit 290 outputs the control signals Si to S4 according to the situation (refer to the table above), the bridge switch circuit 150 generates the first modulation signal by using the control signals s1 to s4, and the first modulation is performed. The voltage of the signal is Vab, and the voltage Vab is transmitted from the primary coil to the secondary coil via the transformer 100 and generates a voltage Vci. When the mode is Model, 'Sl, S3 signal is Γ, (high potential), S2, S4 signal is, 〇 "(low • potential), making the transformer 1〇〇 The voltage vAB on the primary coil is a negative value, and at this time, the voltage VCD on the secondary coil of the transformer 100 is also a negative value, then the secondary communication terminal 300 determines that the value of the forward data TX2 is 1, 1, And send the forward data τχ, 2 to the I/O end. In the mode M〇de2, the control signals &~& are all 〇. In the mode Mode3, the control signal S3 is "Γ, and the control signals S" to S4 are "〇". The material 'measured at the primary coil end of the transformer 1〇〇 is lower than the reference voltage'. If the primary communication circuit 2 (8) will judge the value of the reverse data TX1, τ, (high potential), and the reverse data Qiu 29 U73954 07 (; special) A039 24682twfdoc / n ^ to pure end. In the case of the MGde4, the control _Sl, S2 is,, 〇,, and the S4 is 1 ′. The difference between Fig. 12 and Fig. 13 is that the polarities of the modes Vab and Vgd are different according to the previous mode ^m #m. ® 12 is in the mode MQden (four) and the camera is 〇, so in the mode M〇de3i house. Figure 12 is the direction of the model Model = (3) 乂 3 mode ^le3 _Vab, v (3) is positive ^ 吼 is 1 ’ so

Setting: The installation with electric conversion and two-way communication = the switching principle of the bridge power supply, the core communication with the phase modulation, and the inductance and capacitance resonance of the transformer (LCres〇nance ) Period, 1 impedance woman completes the inverse (four) message, the device of the present invention is simple and ii. Moreover, the present invention only uses the "group suspension" as the domain off-machine, so j has less circuit_product and Yinglin DAA. Briefly stated, the apparatus and method for power supply to two-way communication provided by the present invention can achieve high voltage isolation communication and supply of power to the secondary circuit.

Although the present invention has been disclosed in the above embodiments, it is not intended to be used in the present invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram of an embodiment of an apparatus 1000 for power conversion and two-way communication of the present invention. Figure 2 is a control signal generation Circuit diagram of a first embodiment of the S1 to S4 primary control circuit. 30 1373954 07(^)A039 24682twf.doc/n One embodiment of the picture control circuit 2〇〇 Figure 5 is the operation flow of the phase modulation circuit I 】 Two = one embodiment of the encoder 35 。 Figure 7 疋 a loop detector 45 〇 a port 8 is a synchronous control signal generator '-

Fig. 9 is a timing reduction circuit 5, and Fig. 10 is a circuit diagram of a synchronous control crying. Waveform diagram. UG's input, output and internal signals

FIG. 11 is a control flow chart of the impedance modulation control circuit 390. ^ Shirt set 1_ signal waveform diagram for two-way communication. Figure 13 is a two-way orbital signal wave with a job. [Main component symbol description] 1〇〇〇. Device with power conversion and two-way communication 100: Transformer 50. Bridge switch circuit 9〇: Rectifier circuit 150: Impedance modulation Road H 30 ' 40 : Switching transistor 65 ' 85 : Capacitor 73, 75, 77, 79, 173, 175: Diode 165 : Transistor 2 〇〇: Primary control circuit 31 1373954 07 (Special) A039 24682twf.doc /n 210: communication unit 220: bus transceiver interface 230: clock signal generator 240: mode controller 250: level decoder 290: phase modulation circuit 300: secondary communication control circuit 310: communication unit 320: Tandem bus interface 340: voltage regulator 350: phase decoder 390: impedance modulation control circuit 400: synchronous controller 260, 270: comparator 272: or gate 280: current source 283: switching transistor 285: capacitor 255 : reference voltage source 278: and gate S292, S293, S294: step flow 360: comparator 355: reference voltage source 368: and gate 32 1373954 〇 7 (special) A039 24682twf.doc / n

355: Reference Voltage Source 360 '460: Comparator 462: Reverse OR Gate 470: Pulse Generator. 484: Reverse gate 490: Current source 493: Switching transistor 495: Capacitor 486: Hysteresis gate 488: Gates 510, 530: Current source 506, 526: Hysteresis gates 508, 528: and gates 513, 533: Switching transistor 515, 535: capacitor 504: reverse gate 600: time integrator 700: sample maintaining circuit 800: mode distributor 613: switching transistor 615: capacitor 610: current source 730: buffer 753: switch 715: capacitor 33 1373954 07 (specific) A039 24682twf.doc/n 810: buffers 808, 806, 804, 802: resistors 840, 830, 820: comparators 874, 864, 854: reverse gates 898, 888: and gates S392, S393 , S394: Step flow

34

Claims (1)

1373954 99-10-28 Fine correction replacement page X. Patent application scope: 1. A full-bridge DC-to-DC power conversion device with power conversion and two-way communication functions, the device includes: a transformer including at least a first coil And a second coil for transmitting energy and providing an isolation barrier, the transformer and a capacitor form a resonant circuit; a full-bridge (fiill-bridge) switching circuit coupled to the first coil, Generating a first modulation signal according to a first data; a rectifier circuit coupled to the second coil for generating a supply voltage; and an impedance modulation circuit coupled to the second coil, according to A second data changes the impedance of the sigma transformer, and then modulates the resonance signal on the resonant circuit to generate a second modulation signal; The energy of the first modulation signal is transmitted from the first coil to the second coil by the transformer, so that the rectifier circuit generates the supply voltage; and the energy of the first modulation signal and the first Data substance ^ the full bridge switching circuit; , β, and 仉碉 电路 ,, according to the signal 'to control the impedance of the impedance 35 1373954 101-4-2 variable circuit to change the impedance of the transformer; ± where the first communication control circuit is more The first coil is used to buy the signal on the first coil to judge the information of the second reading of _, · ' with =; the second communication control circuit is further reduced by the number of the dead line: for reading The signal on the second coil is used to determine the information of the first data carried by the five-week change signal. (4) = The full-bridge DC-to-DC/Train, conversion, and set-up according to Item 1 of the T-Scope, wherein the hybrid anti-modulation circuit includes at least a transistor, ^ to switch the electricity according to the second data Crystal, to borrow the impedance. And X text i-free, such as the full-time catalogue of the i-class full-bridge type direct-mixed DC power ^ turn-by-turn, its towel 'this is the parasitic capacity of the circuit _ stand-alone capacitor. 5. In the case of f-materials (4), the full-bridge DC-to-DC power conversion device of the 2nd position, wherein the first communication control circuit comprises: - a phase modulation circuit 'for generating the bridge switch control signals according to the fourth (4); and a bit quasi decoder for intercepting the signal on the first coil to interpret the second key Information about the second data carried by the change signal. 6. The full bridge type DC to DC power conversion device according to claim 5, wherein the first communication control circuit further comprises: a mode controller for generating a plurality of mode signals to borrow This determines the timing at which the first data is transmitted and the second data is received. 7. The full-bridge DC-to-DC 36 u/3954 W year/month>"曰 revision replaces the purchase of a 1 M-2 source conversion device as described in claim 6 of the patent scope, wherein the mode signals include : a first data transmission mode signal for controlling the first control circuit to transmit the first (four); communication, a demagnetization mode signal for controlling the first communication control circuit to cause the variable to be demagnetized Avoid the phenomenon of magnetic saturation of the transformer; a second data receiving mode signal 'to control the first control circuit to determine the receiving_the second: and the communication ^ cycle synchronization preparation mode signal for controlling the first communication control circuit to change the first coil The voltage, in turn, causes the second communication control circuit to operate in synchronization with the first communication control circuit. 8. The full bridge type DC to DC power conversion device according to claim 2, wherein the second communication control circuit comprises: an impedance modulation control circuit, and the impedance modulation is generated according to the second data control Variable control signal a phase decoder for receiving a signal on the second coil to thereby read information of the first data carried by the first modulation signal; and synchronizing control, engaging the phase decoder with the The impedance modulation control circuit Μ is on the second coil to synchronize the first communication control circuit with the second communication control circuit and generate a plurality of synchronization mode signals. The first data receiving mode signal is used to control the second communication control 37 1373954 99-10-28 The mode signal is used to control the second communication control-second data transmission mode signal circuit to transmit the second data. The voltage step signal ' is used to detect the change of the voltage on the second coil to generate a cycle start signal, thereby allowing the control circuit to operate in synchronization with the first communication control circuit. Μ a s 10. The full bridge type direct power conversion device of claim 9, wherein the synchronization controller comprises: a 1 ^ period detector for detecting a change in voltage on the second coil Generating a cycle start signal; a synchronous control signal generator coupled to the cycle detector for receiving the cycle start signal, and generating a sample control signal and a charge control signal according to the cycle start signal; And a timing reduction circuit coupled to the synchronous control signal generator for use The generating signals are generated according to the sampling control signal and the charging control signal. 11. The full bridge type DC to DC power conversion device according to claim 10, wherein the timing reduction circuit comprises: a time integrator, generating a ramp voltage signal according to the charging control signal; The circuit has a sustaining capacitor coupled to the time integrator, sampling the maximum value of the ramp voltage signal according to the sampling control signal, and storing the maximum value of the ramp voltage signal in the maintaining capacitor 38 JIJI 99-10 -28 ------—I ~ month is the correction replacement page; and connected to; = device two: = with most comparators 'turn => = the maximum value of the oblique _ signal == voltage should be Jing voltage...比较 Some comparators compare the size of the proportional electric power, and % generate the time mode signals. 雔L Γ Transfer to money, transpose, with power conversion and two-way communication functions, the device includes: (4) 'With - primary coil And a secondary coil for transmitting the energy of the secondary coil, providing an isolation mechanism, wherein the transformer forms a resonant circuit with a capacitor; The primary system generates a first modulation signal according to the majority of the thirst control signal; the first level is difficult to observe the road, the difficult bridge switching circuit generates the bridge switch control according to the material, thereby controlling the bridge a switching circuit; a voltage-rectifying circuit coupled to the secondary coil for generating a supply circuit, an impedance modulation circuit coupled to the secondary coil, and controlling the mosquito to change the transformer according to an impedance modulation An impedance-to-generate-number; and a beta-secondary communication control circuit coupled to the impedance modulation circuit to generate the impedance modulation control signal according to a reverse data; wherein the energy of the first modulation signal is The transformer is transmitted to the secondary coil by the primary 39 泞 修正 修正 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 99 Simultaneously transmitting 2 'the impedance modulation circuit modulating the impedance of the transformer to modulate the resonance signal on the resonant circuit, and thereby generating the second modulation signal, the second modulation signal Changing the voltage of the primary coil by the transformer; the primary communication control circuit is further coupled to the primary coil for reading a signal on the primary coil to determine information of the reverse data carried by the second modulation signal; The secondary communication control circuit is further coupled to the secondary coil for reading a signal on the secondary coil to thereby determine information of the forward data carried by the first modulated signal. 13. The bridge type DC-to-DC power conversion device according to claim 12, wherein the bridge switch circuit is a full bridge switch circuit, a half bridge switch circuit or a push pull switch circuit. 14. The bridge type DC-to-DC power conversion device of claim 1, wherein the impedance modulation circuit comprises at least one transistor for switching the transistor according to the reverse data to thereby adjust Change the impedance of the transformer. 15. The bridge type DC-to-DC power conversion device described in claim 12 is 'where' the parasitic capacitance of the circuit or an external independent capacitor. The bridge type DC-to-DC power conversion device of claim 12, wherein the primary communication control circuit comprises: a phase modulation circuit for generating the signal according to the primary data and the plurality of mode signals Some bridge switch control signals; and 1373954 〇 修正 修正 correction page 99-10-28 a quasi-decoder, by detecting the signal on the primary coil, interpreting the reverse data carried by the second modulating signal Information. The bridge type DC-to-DC power conversion device of claim 16, wherein the primary communication control circuit further comprises: a mode controller for generating the mode signals, thereby determining to transmit the mode Forward data and the timing of receiving the reverse data. 18. The bridge type DC-to-DC power conversion device of claim 17, wherein the mode signals include: a forward data transmission mode signal for controlling the primary communication control circuit to transmit the primary data; a magnetic release mode signal for controlling the primary communication control circuit to cause the transformer to be magnetically oscillated to avoid magnetic saturation of the transformer; the bamboo is used for the signal of the team; the control circuit interprets the received reverse And a batch offset-synchronization preparation mode signal for controlling the primary communication to change the voltage on the primary coil, thereby allowing the primary communication control circuit to operate in synchronization with the secondary communication control circuit. The original conversion splitting 'the towel', the secondary communication control circuit includes. Variable control: control secret, according to the reverse data generation Na Na, this interpretation of the first-modulation signal carried; ^73954 (four) coffee day correction replacement page a synchronization controller that is lightly connected to the phase decoder and the impedance modulation control circuit for detecting a signal on the secondary coil to thereby allow the initial communication control circuit and the secondary The communication control circuit works synchronously and generates a plurality of synchronization mode signals. 20. The bridge type DC to DC power conversion device of claim 1, wherein the synchronization mode signals comprise: a forward data reception mode signal for controlling the secondary communication control circuit to interpret the received The forward data; a magnetic release mode signal; and a reverse data transmission mode signal for controlling the secondary communication control circuit to transmit the reverse data. . A periodic synchronization preparation mode signal is used to detect a change in voltage on the secondary coil to generate a weekly detection signal, thereby allowing the primary communication control circuit to operate in synchronization with the secondary communication control circuit. 21. The bridge type DC to DC power conversion device of claim 2, wherein the synchronization controller comprises: a period detector for detecting a change in voltage on the secondary coil' And generating a start signal of the cycle; a synchronous control signal generator coupled to the period detector for receiving the cycle start signal, and generating a sample control signal and a charge control signal according to the cycle start signal And a timing reduction circuit that is lightly connected to the synchronous control signal generator for controlling the mode signal according to the sampling control. 42 101-4-2 〆 修正 修正 替换 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 The charge control signal generates a ramp voltage signal; the eight_one sample hold circuit has a sustain capacitor coupled to the time product state: the maximum value of the ramp voltage signal is sampled according to the sample control signal, and the slope is The maximum value of the voltage signal is stored on the sustain capacitor; and the mode distributor has a voltage dividing circuit and a plurality of comparators coupled to each other. a time-integrator and the sample-and-hold circuit, wherein the voltage-dividing circuit is used to allocate a ratio of the maximum value of the ramp voltage signal on the sustain capacitor to generate a multi-proportional voltage and to compare the ratios. The voltage and the magnitude of the ramp voltage signal are used to generate the sync mode signals. 23. A method for power conversion and two-way communication: Tiger generation - forward data 'generates a plurality of bridge switch control signals according to the forward data, thereby controlling - the bridge switch circuit generates - the first modulation signal Providing a transformer having an isolation mechanism, the energy of the first modulation signal is converted from the energy of the first modulation signal to the secondary coil of the slot _ level line _ and the _ (four) real f Simultaneously transmitted, providing-signing circuit, thereby influencing the signal on the secondary coil to generate a supply voltage; and generating - reverse data, according to the reverse data generation - impedance modulation control 1373954 Positive replacement page · · system signal ' to || this (four) impedance modulation Wei Wei Wei suspension _ impedance, and then modulate the resonance signal on the resonance circuit of the transformer | | to generate a second modulation signal, the first The second modulation signal changes the voltage of the primary ring via the transformer. 24. A method for power conversion and two-way communication as described in claim 23, the method further comprising: Reading the signal on the primary coil to determine the information of the reverse data carried by the second modulated signal; and reading the signal on the secondary coil to thereby determine the carried by the first modulated signal Information on the forward information. ° 25. A method for power conversion and two-way communication as described in claim 24, the method further comprising: generating a plurality of mode signals to control the transmission of the forward and reverse data. The method of power conversion and two-way communication described in the '25', wherein the synchronization mode signals include: a forward data mode signal for instructing the method to transmit the forward data and interpreting the received forward data; and a mode signal for indicating that the transformer is demagnetized to avoid magnetic saturation of the transformer Phenomenon; a reverse data mode signal for indicating that the method transmits the reverse data and interprets the received reverse data. The one-cycle synchronous preparation mode signal is used for synchronous operation required for two-way communication, and generates a cycle start signal to inform the method to sequentially generate the mode signals at the starting point of the next cycle. 44